JPH02151052A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make possible an increase in the density of a circuit by a method wherein an isotropic etching is performed on a first interlayer insulating film, a thin second interlayer insulating film is formed on the base of a through hole and the through hole is formed. CONSTITUTION:A nitride film 4 at a through hole formation place is removed by anisotropic dry etching, a hole is formed to etch part of the surface of a SOG(SPin On glass) film 3 and the film 3 is etched by an isotropic etching method using the film 4 as an etching mask until a first-layer Al wiring 2 is exposed. Then, the organic and low-softening point SOG film 3 is fluidized by e heat treatment and a SOG film 6 is adhered on the upper part of the wiring 2 at a through hole opening part. Then, the film 6 is etched by an anisotropic dry etching method in the size of an opening part in the film 4 to expose the surface of the wiring 2 and a second-layer Al wiring 7 is formed. Thereby, even if a matching margin is decreased, there is no possibility of generating a disconnection trouble and an increase in the density of a circuit can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device having a multilayer interconnection structure, and particularly to a method for manufacturing a semiconductor device that enables high density integrated circuits.

[Prior Art] A conventional method for manufacturing multilayer wiring will be described with reference to FIGS. 3(a) to 3(d). First, a first layer aluminum wiring 2 is formed on a SiO2 film 1 formed by the CVD method on a semiconductor substrate (not shown), and then an organic coating film 5OG (SPIN ONGLASS) M3 is deposited. 0 Next, photoresist 5 is applied and patterned to form a through hole connecting the first and second layer aluminum wiring [Fig. 3(a)]. , The SOG film 3 is subjected to isotropic etching to open a through hole [Fig. 3(b)]. The reason why isotropic etching is used here is to prevent the second layer aluminum wiring from being disconnected at the through hole part. In order to loosen the step, the photoresist 5 is removed,
An aluminum layer 7a is formed on the entire surface. A new photoresist 8 is formed on it and patterned [
3(c)], then anisotropic dry etching is performed on the aluminum layer 7a to form the second layer aluminum wiring 7.
is formed and the photoresist 8 is removed [FIG. 3(d)
Ko.

[Problems to be Solved by the Invention] The conventional multilayer wiring manufacturing method described above has the following drawbacks. That is, although the aluminum layer 7a is etched in the steps from FIG. 3(C) to FIG. 3(d),
In this case, in the portion where the aluminum layer 7a of the through-hole opening is etched away, the first layer aluminum wiring 2 is also etched, and a disconnection occurs in this portion 2a.

This situation may occur when the opening of the through hole becomes too wide, but it may also occur when the alignment accuracy is insufficient. Therefore, in the past, in order to prevent wire breakage even if some misalignment occurred,
A sufficient alignment margin was required. However, ensuring a sufficient alignment margin hinders increasing the density of 4A precision circuits.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that does not cause a disconnection accident even when the alignment margin is reduced, thereby achieving higher density of integrated circuits.

[Means for Solving the Problems] A method of manufacturing a semiconductor device having multilayer wiring according to the present invention includes a step of forming a first layer wiring on an insulating layer of a semiconductor substrate, and forming a first interlayer insulating film thereon. furthermore, forming a mask material having etching properties different from that of the first interlayer insulating film thereon;
A step of forming an etching mask by etching away the connecting portion between the layer wiring and the upper layer wiring, and isotropically etching the first interlayer insulating film through the etching mask to form a through hole. forming a thin second interlayer insulating film on the bottom surface of the through hole on the first layer wiring using a material with etching properties different from the mask material; and forming the second interlayer insulating film using the etching mask as a mask. The method includes the steps of exposing the surface of the first layer wiring by subjecting the layer to anisotropic etching, removing the etching mask, and forming a second layer wiring.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(i) are cross-sectional views showing the order of steps in an embodiment of the present invention. First, a 5i02 film 1 formed by CVD on a semiconductor substrate (not shown) is coated with a film thickness of 0.
0th order to form the first layer aluminum wiring 2 of 6 μm,
An organic SOG film 3 used as an interlayer insulating film is deposited to a thickness of 1.0 μm, and a nitride film 4 made by plasma CVD, which will later be used as an etching mask, is deposited on top of it to a thickness of 0.2 μm. . Next, a photoresist 5 is applied and patterned to form through holes [FIG. 1(a)].

Next, the nitride film 4 at the location where the through hole is to be formed is removed by anisotropic dry etching to form a hole having a side of 1.0 μm [FIG. 1(b)]. Here, 5OGIIi3
If the conditions are such that a part of the surface is etched, the nitride film will be completely removed even if the etching rate varies. Next, the photoresist 5 is removed [FIG. 1(c)
)], then the SOG film 3 is etched by isotropic etching using a dry method using the nitride film 4 as an etching mask until the first layer aluminum wiring 2 is exposed [FIG. 1(d)], and then , a heat treatment is performed at 300 to 400°C in a nitrogen or argon atmosphere. Through this heat treatment, the organic SOG film 3, which has a low softening point, becomes fluidized and forms a part of the through-hole opening, as shown in FIG. 1(e). An SOG film 6 is attached on top of the first layer aluminum wiring 2. The thickness of this SOG film 6 increases as the heat treatment temperature increases and as the heat treatment time increases.

Next, by anisotropic dry etching, 300M6 is etched to the size of the opening in the nitride film to expose the surface of the first layer aluminum wiring 2 [FIG. 1(f)], and then nitrided by dry etching. Remove only the film 4 [
1(g)], then an aluminum layer 7a is deposited on the entire surface by sputtering, a photoresist 8 is applied thereon, and this is buttered [FIG. 1(h)]
]. Finally, the aluminum layer 7a is subjected to anisotropic dry etching to form the second layer aluminum wiring 7.
Figure 1(i)].

Next, other embodiments of the present invention will be described with reference to FIGS. 2(e) and 2(f).

This embodiment uses the steps corresponding to FIGS. 1(a) to (C) and FIGS. 1(g) to (i) of the previous embodiment as they are.

In this embodiment, after the steps shown in FIGS. 1A to 1C, the SOG film 3 is subjected to isotropic etching using plasma. At this time, the plasma gas is selected from a gas that does not cause chemical reactions, such as argon. If you do that,
Since the etched SOG is reattached to the surrounding areas, an SOG film 6 is formed on the first layer aluminum wiring 2 and on the lower surface of the nitride film 4, as shown in FIG. 2(e). Next, 300M6 is subjected to anisotropic dry etching to expose the surface of the first layer aluminum wiring 2 [FIG. 2(f)]. The subsequent steps are similar to those in the previous example.

This embodiment has the advantage that stress migration is less likely to occur because it does not require high-temperature heat treatment unlike the previous embodiments.

In the above embodiments, a nitride film was used as an etching mask for the SOG film, but since this film only needs to have a different etching property from that of the SOG film, it may be etched using other materials such as sputtering. It may also be made of silicon or the like. Further, in the above embodiments, the first layer and second layer aluminum wiring have been described, but the present invention can be applied to any number of layers of wiring. Furthermore, as the material for the wiring, other than aluminum, other materials such as tungsten and silicide can also be used.

[Effects of the Invention] As explained above, the present invention forms an etching mask having holes at the through-hole formation locations on the first interlayer insulating film, and uses this to form an etching mask isotropically on the first interlayer insulating film. This method involves performing anisotropic etching, forming a thin second interlayer insulating film on the bottom surface of the through hole, and performing anisotropic etching on this using the etching mask to form the through hole, so that the following effects are achieved. be able to.

■ The dimensions of the through holes are determined by anisotropic etching of the thin film, so they can be made precise. Therefore, it is possible to reduce the margin for alignment in patterning when forming through-holes or forming second-layer wiring, and it becomes possible to increase the density of integrated circuits.

■ Anisotropic etching is performed only on thin interlayer insulating films, and isotropic etching is performed on thick interlayer insulating films, so the through-hole is formed with a gentle slope as a whole, and Disconnection accidents in two-layer wiring can be prevented.

(2) Even if the through hole is made too large in the first interlayer insulating film, the first layer wiring will not be etched due to the presence of the second interlayer insulating film, and the first layer wiring will not be disconnected.

[Brief explanation of the drawing]

FIGS. 1(a) to (i) are cross-sectional views showing the process order of one embodiment of the present invention, and FIGS. 2(e) and (f) show intermediate steps of another embodiment of the present invention. The sectional views and FIGS. 3(a) to 3(d) are sectional views showing the process order of a conventional example. 1...5i02JI! , 2... First layer aluminum wiring, 3... SOG film, 4... Nitride film, 5
...Photoresist, miniram wiring. 6... SOG film, 7... Second layer Al8.-7 odoresist.

Claims (1)

[Claims] forming a lower layer wiring on an insulating layer on a semiconductor substrate;
a step of forming a first interlayer insulating film thereon; and a step of forming a first interlayer insulating film on the first interlayer insulating film using a material having a different etching property from that of the first interlayer insulating film, and then using a material having a different etchability from that of the first interlayer insulating film so as to be transparent to the through-hole forming portion of the first interlayer insulating film. forming an etching mask having holes;
Isotropically etching the first interlayer insulating film using the etching mask to form a first through hole in the first interlayer insulating film, and applying the etching mask to the bottom of the first through hole. is a step of forming a thin second interlayer insulating film made of a material with different etching properties, and performing anisotropic etching on the second interlayer insulating film through the etching mask to form the second interlayer insulating film. forming a second through hole; removing the etching mask; and forming an upper layer wiring connected to the lower layer wiring through the first and second through holes. A method for manufacturing a featured semiconductor device.