JPS6297348A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6297348A
JPS6297348A JP14702385A JP14702385A JPS6297348A JP S6297348 A JPS6297348 A JP S6297348A JP 14702385 A JP14702385 A JP 14702385A JP 14702385 A JP14702385 A JP 14702385A JP S6297348 A JPS6297348 A JP S6297348A
Authority
JP
Japan
Prior art keywords
film
aluminum
alloy
silicon
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14702385A
Other languages
Japanese (ja)
Inventor
Tetsuro Matsuda
哲朗 松田
Shohei Shima
昇平 嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP14702385A priority Critical patent/JPS6297348A/en
Publication of JPS6297348A publication Critical patent/JPS6297348A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To suppress the yield of protruded parts on the surface of a wiring layer, by forming a wiring layer pattern, thereafter forming a second metal layer on the entire surface, forming an alloy part at a part, where the wiring pattern and the second metal layer are contacted, forming a coated layer, and imparting insulating property to the second metal layer on an insulating film in the main time. CONSTITUTION:A silicon dioxide film 102 is formed on the surface of a silicon substrate 101, which is formed on a specified element region, as an insulating film. Thereafter, aluminum-silicon alloy 103 is deposited. The alloy is patterned into a specified shape by a photoetching method. Thus an aluminum-silicon alloy pattern 103' is formed. Then, a thin tantalum film 104 is formed on the entire surface. Thereafter, heat treatment is performed in a diluted oxygen atmosphere. Then, the thin tantalum film on the aluminum-silicon alloy pattern 103' reacts with the aluminum-silicon alloy, and an aluminum-silicon-tantalum alloy film 105 is obtained. Meanwhile, the thin tantalum film on the silicon dioxide film 102 is completely oxidized and a tantalum oxide film 106 is obtained and insulating film is formed. Thus the wiring layer pattern is completed.

Description

【発明の詳細な説明】 [発明の属する技術分野] 本発明は半導体装置の製造方法に係り、特に配線層の形
成に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to the formation of a wiring layer.

[従来の技術およびその問題点] 半導体技術の進歩と共に超LSIはじめ半導体装置の高
集積化が進められてきており、配線層の形成においても
高精度の微細パターン形成技術が要求されている。
[Prior Art and its Problems] With the progress of semiconductor technology, the integration of semiconductor devices including VLSIs has been increasing, and highly accurate fine pattern forming technology is also required in the formation of wiring layers.

従来、集積回路における配線層の形成に際しては、一般
に次に示すような方法が知られている。
Conventionally, the following methods are generally known for forming wiring layers in integrated circuits.

まず、例えば所定の素子領域(図示せず)の形成された
基板201上に絶縁膜として二酸化硅素膜202を形成
する。続いてアルミニウムー硅素合金をスパッタ法によ
り堆積せしめた後、写真食刻法により所望の形状にバタ
ーニングし、第2図(a)に示す如く配線層パターン2
03を形成する。
First, for example, a silicon dioxide film 202 is formed as an insulating film on a substrate 201 on which a predetermined element region (not shown) is formed. Next, an aluminum-silicon alloy is deposited by sputtering, and then patterned into a desired shape by photolithography to form a wiring layer pattern 2 as shown in FIG. 2(a).
Form 03.

ところで、この方法では、上述の如くして配線層パター
ン203を形成した後、通常は配線層の電気的特性を向
上させるだめの熱処理工程すなわちシンタ一工程を施す
。また、更にその他の熱工程を施すことも多いが、熱処
理工程で、配線層表面が溶けて第2図(b)に示す如く
突起204が発生し、近隣の導体層(配線パターン)あ
るいは上層配線等と電気的短絡Aを起すことがあった。
By the way, in this method, after the wiring layer pattern 203 is formed as described above, a heat treatment step, that is, a sintering step, is usually performed to improve the electrical characteristics of the wiring layer. In addition, other heat processes are often performed, but during the heat treatment process, the surface of the wiring layer melts and protrusions 204 are generated as shown in FIG. etc., which could cause an electrical short circuit A.

このことは集積回路の信頼性の低下あるいは歩留りの低
下を招くことが多く、各配線層パターンは近隣の導体層
あるいは上層配線との距離が充分に大きくなるように形
成しなければならず、高集積化をはばむ原因となってい
た。
This often leads to a decrease in reliability or yield of integrated circuits, and each wiring layer pattern must be formed with a sufficiently large distance from neighboring conductor layers or upper layer wiring. This was a factor that hindered agglomeration.

[発明の目的] 本発明は、前記実情に鑑みてなされたもので、配線層表
面に突起が発生するのを抑制し、半導体装置の信頼性の
向上および歩留りの向上をはかることを目的とする。
[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to suppress the occurrence of protrusions on the surface of the wiring layer, and to improve the reliability and yield of semiconductor devices. .

[発明の概要] そこで、本発明では、集積回路等の配線層の形成にあた
り、第1の金属からなる配線層パターンを形成した後、
この配線層パターンの上面および側面に被覆層を形成し
、配線層パターンの表面に突起が発生するのを防止しよ
うとするもので、配線層パターンの形成後、全面に第、
2の金属層を形成し更に、配線層パターンとこの第2の
金属層との接する部分でこれらを合金化することによっ
て被覆層の形成を行ない、一方路縁膜上の第2の金属層
は酸化によって絶縁化するようにしている。
[Summary of the Invention] Therefore, in the present invention, in forming a wiring layer of an integrated circuit, etc., after forming a wiring layer pattern made of a first metal,
A coating layer is formed on the top and side surfaces of the wiring layer pattern to prevent protrusions from forming on the surface of the wiring layer pattern.
A coating layer is formed by forming a second metal layer and then alloying the second metal layer at the contact portion between the wiring layer pattern and the second metal layer, while the second metal layer on the edge film is It is insulated by oxidation.

[発明の効果] 本発明によれば、配線層パターン形成後基板表面全体に
被膜を形成し、配線層パターンの表面ではこの被膜との
間で合金化を行なうと共に、絶縁膜上の被膜は酸化によ
って絶縁化するようにし配線層パターンを被覆保護する
ようにしているため配線層表面に突起が発生するのを防
ぐことができ、集積回路における信頼性および歩留りの
向上をはかることができる。
[Effects of the Invention] According to the present invention, a film is formed on the entire surface of the substrate after the wiring layer pattern is formed, and alloying is performed with this film on the surface of the wiring layer pattern, and the film on the insulating film is oxidized. Since the wiring layer pattern is insulated and protected by covering, it is possible to prevent the formation of protrusions on the surface of the wiring layer, and it is possible to improve the reliability and yield of integrated circuits.

また、各配線層パターン間の距離を短く設定しても信頼
性を充分に維持することができ、高集積化が容易に実現
可能となる。
Further, even if the distance between each wiring layer pattern is set short, reliability can be sufficiently maintained, and high integration can be easily realized.

更に、この配線層パターンは表面が合金層で被覆されて
いるため、高温に耐え得、大電力用のデバイスにも使用
可能である。
Furthermore, since the surface of this wiring layer pattern is coated with an alloy layer, it can withstand high temperatures and can also be used in high-power devices.

[発明の実施例] 以下、本発明の実施例について図面を参照しつつ詳細に
説明する。
[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第1図(a)乃至(C)は、所定の素子領域の形成され
たシリコン基板101上に配線層パターンを形成する工
程を示す図である。
FIGS. 1A to 1C are diagrams showing steps of forming a wiring layer pattern on a silicon substrate 101 on which a predetermined element region is formed.

まず、第1図(a)に示す如く、所定の素子領域の形成
されたシリコン基板101の表面に絶縁膜として膜厚8
000人の二酸化硅素WA102を形成した後、(必要
に応じてスルーホール(図示せず)を穿孔し、)アルミ
ニウムー硅素合金103をスパッタ法により8000人
堆積し、これを写真食刻法により所望の形状にパターニ
ングすることによりアルミニウムー硅素合金パターン1
03′を形成する。
First, as shown in FIG. 1(a), an insulating film is formed on the surface of a silicon substrate 101 with a thickness of 8.
After forming the silicon dioxide WA 102 of 8,000 layers, 8,000 layers of aluminum-silicon alloy 103 are deposited by sputtering (by drilling through holes (not shown) as necessary), and this is deposited as desired by photolithography. Aluminum-silicon alloy pattern 1 is formed by patterning into the shape of
03' is formed.

次いで、第1図(b)示す如く、スパッタ法により、膜
厚200人のタンタル薄膜104を表面全体に形成する
Next, as shown in FIG. 1(b), a tantalum thin film 104 having a thickness of 200 mm is formed over the entire surface by sputtering.

この後、希釈された酸素雰囲気中で450°C130分
の熱処理を施すことにより、第1図(C)に示す如く、
アルミニウムー硅素合金パターン103′上のタンタル
薄膜は、アルミニウムー硅素合金と反応してアルミニウ
ムー硅素−タンタル合金膜105と化し、一方、二酸化
硅素膜102上のタンタル薄膜は完全に酸化され酸化タ
ンタル膜106となり絶縁膜化され、配線層パターンが
完成する。
After that, heat treatment was performed at 450°C for 130 minutes in a diluted oxygen atmosphere, as shown in Figure 1(C).
The tantalum thin film on the aluminum-silicon alloy pattern 103' reacts with the aluminum-silicon alloy and becomes an aluminum-silicon-tantalum alloy film 105, while the tantalum thin film on the silicon dioxide film 102 is completely oxidized and becomes a tantalum oxide film. 106 is formed into an insulating film, and a wiring layer pattern is completed.

このようにして形成された配線層パターンは表面がアル
ミラム−タンタル−硅素合金で被覆されているため、そ
の後に熱処理工程を経た場合にも突起が発生することは
ほとんどなかった。
Since the surface of the wiring layer pattern thus formed was coated with an aluminum-tantalum-silicon alloy, almost no protrusions were generated even when the pattern was subjected to a subsequent heat treatment process.

その結果、配線の信頼性が大幅に向上し、配線のパター
ン設計を行なう際の自由度も大きくなる。
As a result, the reliability of the wiring is greatly improved, and the degree of freedom in designing the wiring pattern is also increased.

また、この方法では、不要部(配線層パターン表面以外
)のタンタル薄膜は選択的に除去される必要はなく、酸
化すればよいため、工程が簡略化できる。
Furthermore, in this method, the tantalum thin film in unnecessary parts (other than the surface of the wiring layer pattern) does not need to be selectively removed, but only needs to be oxidized, thereby simplifying the process.

なあ、実施例においては、配線層パターン形成用の第1
の金属として、アルミニウムー硅素合金を使用したが、
本発明はアルミニウムあるいは他のアルミニウム合金、
鉛等、低融点金属を用いる場合に有効な方法である。
By the way, in the example, the first
An aluminum-silicon alloy was used as the metal, but
The present invention uses aluminum or other aluminum alloys,
This method is effective when using low melting point metals such as lead.

また、被覆層(第2の金属膜)としてタンタル薄膜を用
いたが、この他モリブデン、タングステン等地の金属で
もよい。
Further, although a tantalum thin film is used as the covering layer (second metal film), other metals such as molybdenum and tungsten may be used.

更に、実施例では、希釈された酸素ガス雰囲気中で45
0℃、30分間の熱処理を行なうことにより、アルミニ
ウムー硅素合金パターン103′上のタンタル薄膜10
4の合金化と、二酸化硅素102上のタンタル薄膜10
4の酸化を同時に行なうようにしたが、加熱による合金
化を行なった後、酸素を導入しつつ加熱することにより
酸化を行なうというふうに別工程としてもよい。また、
加熱温度、加熱時間等の処理条件についても何ら実施例
に限定されるものではなく、使用する金属あるいは合金
の種類に応じて適宜選択可能である。
Furthermore, in the example, 45
By performing heat treatment at 0°C for 30 minutes, the tantalum thin film 10 on the aluminum-silicon alloy pattern 103' is
Alloying of 4 and tantalum thin film 10 on silicon dioxide 102
Although the oxidation of step 4 is carried out at the same time, it is also possible to conduct the oxidation in separate steps, such as alloying by heating and then oxidizing by heating while introducing oxygen. Also,
Processing conditions such as heating temperature and heating time are not limited to those in the examples at all, and can be appropriately selected depending on the type of metal or alloy used.

加えて、この方法は、多層配線を行なう場合にも適用可
能であり、層間絶縁膜の形成等が高温工程を伴う場合に
も既に形成される配線層パターンの劣化を生じることな
く、信頼性を維持することがて゛きる。また、絶縁膜上
のタンタル薄膜(第2の金属膜)は選択的に除去される
のではなく、酸化によって絶縁化されてそのまま残留す
る構造であるため表面の段差が増大することがないため
、多層配線の場合に特に優れた効果を奏効するものであ
る。
In addition, this method can be applied to multi-layer wiring, and even if the formation of an interlayer insulating film involves high-temperature processes, it can improve reliability without causing deterioration of the wiring layer pattern that has already been formed. It is possible to maintain it. In addition, the tantalum thin film (second metal film) on the insulating film is not selectively removed, but is insulated by oxidation and remains as it is, so the surface level difference does not increase. This is particularly effective in the case of multilayer wiring.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)乃至(b)は、本発明実施例の配線層パタ
ーンの形成工程図、第2図(a>は従来の配線層パター
ンを示す図、第2図(b)は熱処理後の従来の配線層パ
ターンを示す図である。 201・・・基板、202・・・二酸化硅素膜、203
・・・配線層パターン、204・・・突起、101・・
・シリコン基板、102・・・二酸化硅素膜、103・
・・アルミニウムー硅素合金、103′・・・アルミニ
ウムー硅素合金パターン、104・・・タンタル薄膜、
105・・・アルミニウムー硅素−タンタル合金膜、’
106・・・酸化タンタル膜。 第1図(a) 第1図(b) 第1図(C) 手続ネ甫正書(方式) 昭和61年11月27日
Figures 1 (a) and (b) are process diagrams for forming a wiring layer pattern according to an embodiment of the present invention, Figure 2 (a) is a diagram showing a conventional wiring layer pattern, and Figure 2 (b) is after heat treatment It is a diagram showing a conventional wiring layer pattern. 201...Substrate, 202...Silicon dioxide film, 203
...Wiring layer pattern, 204...Protrusion, 101...
・Silicon substrate, 102...Silicon dioxide film, 103・
...Aluminum-silicon alloy, 103'...Aluminum-silicon alloy pattern, 104...Tantalum thin film,
105...Aluminum-silicon-tantalum alloy film,'
106...Tantalum oxide film. Figure 1 (a) Figure 1 (b) Figure 1 (C) Procedural Nefusho (Method) November 27, 1985

Claims (4)

【特許請求の範囲】[Claims] (1)所定の素子領域が形成されると共に、少なくとも
表面の1部が絶縁性物質から構成されている基板の一主
面に配線層を形成するに際し、第1の金属膜を形成しこ
れをパターニングすることにより配線パターンを形成す
る工程と、全面に第2の金属膜を形成する工程と、 前記配線パターンとこれをとり囲む前記第2の金属膜と
を合金化すべく基板を加熱する熱処理工程と、 前記絶縁性物質上の前記第2の金属膜を酸化する酸化処
理工程とを含むことを特徴とする半導体装置の製造方法
(1) When forming a wiring layer on one main surface of a substrate in which a predetermined element region is formed and at least a portion of the surface is made of an insulating material, a first metal film is formed and A step of forming a wiring pattern by patterning, a step of forming a second metal film on the entire surface, and a heat treatment step of heating the substrate to alloy the wiring pattern and the second metal film surrounding it. A method for manufacturing a semiconductor device, comprising the steps of: oxidizing the second metal film on the insulating material.
(2)前記熱処理工程と前記酸化処理工程は、酸化雰囲
気中において基板を加熱することによって同時に進行せ
しめられる工程であることを特徴とする特許請求の範囲
第(1)項記載の半導体装置の製造方法。
(2) Manufacturing the semiconductor device according to claim (1), wherein the heat treatment step and the oxidation treatment step are performed simultaneously by heating the substrate in an oxidizing atmosphere. Method.
(3)前記第1の金属膜はアルミニウム又はアルミニウ
ム合金からなることを特徴とする特許請求の範囲第(1
)項記載の半導体装置の製造方法。
(3) The first metal film is made of aluminum or an aluminum alloy.
) The method for manufacturing a semiconductor device according to item 2.
(4)前記第2の金属膜は高融点金属膜からなることを
特徴とする特許請求の範囲第(1)項又は第(2)項記
載の半導体装置の製造方法。
(4) The method for manufacturing a semiconductor device according to claim (1) or (2), wherein the second metal film is made of a high melting point metal film.
JP14702385A 1985-07-04 1985-07-04 Manufacture of semiconductor device Pending JPS6297348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14702385A JPS6297348A (en) 1985-07-04 1985-07-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14702385A JPS6297348A (en) 1985-07-04 1985-07-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6297348A true JPS6297348A (en) 1987-05-06

Family

ID=15420794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14702385A Pending JPS6297348A (en) 1985-07-04 1985-07-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6297348A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482547A (en) * 1987-09-24 1989-03-28 Tadahiro Omi Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482547A (en) * 1987-09-24 1989-03-28 Tadahiro Omi Semiconductor device

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