JPS61142739A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61142739A JPS61142739A JP26441984A JP26441984A JPS61142739A JP S61142739 A JPS61142739 A JP S61142739A JP 26441984 A JP26441984 A JP 26441984A JP 26441984 A JP26441984 A JP 26441984A JP S61142739 A JPS61142739 A JP S61142739A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- layer
- substrate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- 238000002844 melting Methods 0.000 claims abstract description 10
- 230000008018 melting Effects 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 10
- -1 nitride compound Chemical class 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 239000010936 titanium Substances 0.000 abstract description 20
- 239000000758 substrate Substances 0.000 abstract description 17
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 10
- 150000004767 nitrides Chemical class 0.000 abstract description 5
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 14
- 229910052719 titanium Inorganic materials 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- LKTZODAHLMBGLG-UHFFFAOYSA-N alumanylidynesilicon;$l^{2}-alumanylidenesilylidenealuminum Chemical compound [Si]#[Al].[Si]#[Al].[Al]=[Si]=[Al] LKTZODAHLMBGLG-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に関し、特に基体と配
線金属の間に珪化金属、高融点金属、窒化金属の層を介
在させた信頼性の高い電極の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, in particular a method for improving reliability by interposing a layer of a metal silicide, a high melting point metal, or a metal nitride between a substrate and a wiring metal. This invention relates to a method for manufacturing high-quality electrodes.
一般に、半導体基体上に形成される配線金属としては、
アルミニウム又はアルミニウムーシリコン合金が用いら
れている。しかし、アルミニウムを配線金属として用い
九場合、通常の素子製造工程における熱処理にともなう
温度上昇により、浅い不純物拡散層を有するトランジス
タま九はＩＣにおいては、アルミニウムと基板シリコン
との反応によるアルミニウムの基板シリコンへの侵入が
この浅い拡散層による接合を破壊する恐れがある。In general, wiring metals formed on semiconductor substrates include:
Aluminum or aluminum-silicon alloys are used. However, when aluminum is used as a wiring metal, transistors with shallow impurity diffusion layers due to the temperature rise associated with heat treatment in the normal device manufacturing process are difficult to manufacture. There is a risk that the intrusion into the shallow diffusion layer may destroy the junction formed by this shallow diffusion layer.
上記の如きアルミニウムとシリコンとの反応を防止する
手段として、従来アルミニウム配線層と基板シリコンと
の間に、チタン、モリブデン、タングステン等の高融点
金属層を設けることが行なわれている。As a means for preventing the reaction between aluminum and silicon as described above, conventionally, a high melting point metal layer such as titanium, molybdenum, tungsten, etc. is provided between the aluminum wiring layer and the silicon substrate.
しかし、この方法においては高融点金属と配線材料であ
るアルミニウム、および基板を構成するシリコンとが低
温で反応しｔす、高融点金属表面が酸化されｆｃｌｐし
て電極特性の安定性に対して問題があう九〇
〔発明の目的〕
本発明は上記の様な従来技術の欠点を改良したもので、
安定で低抵抗のコンタクト電極を有する半導体装置を提
供することを目的とする。However, in this method, the high melting point metal, aluminum that is the wiring material, and silicon that makes up the substrate react at low temperatures, and the surface of the high melting point metal is oxidized and fclp, which causes problems with the stability of the electrode characteristics. 90 [Object of the Invention] The present invention improves the drawbacks of the prior art as described above.
An object of the present invention is to provide a semiconductor device having a stable and low-resistance contact electrode.
上記目的を達成せしめる九め、本発明の半導体装置の製
造方法によれば、絶縁膜上およびコンタクト開孔部表面
上に高融点金属層を形成後、窒素雰囲気中で熱処理（例
えば４００〜８００℃）して金属表面を窒化金属にする
と共に金属と半導体界面をシリサイド化し、次に上記窒
化金属上に配線金属を形成して配線路を形成する。Ninth to achieve the above object, according to the method of manufacturing a semiconductor device of the present invention, after forming a high melting point metal layer on the insulating film and the surface of the contact opening, heat treatment (for example, 400 to 800 ° C. ) to make the metal surface a metal nitride and silicide the interface between the metal and the semiconductor, and then form a wiring metal on the metal nitride to form a wiring path.
本発明により、電極配線の低抵抗化が達成され、アルミ
ニウムと高融点金属との反応が抑えられ高温熱処理にお
いても安定した電極特性を維持できる信頼性の高い電極
を実現できる。According to the present invention, it is possible to achieve a low resistance of electrode wiring, to suppress the reaction between aluminum and a high-melting point metal, and to realize a highly reliable electrode that can maintain stable electrode characteristics even during high-temperature heat treatment.
以下、本発明の詳細を一実施例に従って説明する。第１
図（ａ）〜（ｄ）は、本発明てよる半導体装置の製造方
法の一実施例を示す工程断面図である。先ず通常の方法
によυシリコン基体１に所定不純物を拡散して拡散層２
を形成してＰＮ接合を形成する。次にシリコン基板１０
表面にシリコン酸化膜３を設け、更にフォトレジスト法
により拡散層２上のシリコン酸化膜３を選択的に除去し
てシリコン酸化膜３にコンタクトホールを設ける。Hereinafter, details of the present invention will be explained according to one embodiment. 1st
Figures (a) to (d) are process cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device according to the present invention. First, a predetermined impurity is diffused into the υ silicon substrate 1 using a normal method to form a diffusion layer 2.
is formed to form a PN junction. Next, the silicon substrate 10
A silicon oxide film 3 is provided on the surface, and the silicon oxide film 3 on the diffusion layer 2 is selectively removed using a photoresist method to form a contact hole in the silicon oxide film 3.
次に、通常のスパッタリング装置で全面にチタン（Ｔｉ
）をスパッタリングによシ被着し、５００〜ｚｏｏｏｉ
のチタン膜４を形成する。Next, the entire surface is coated with titanium (Ti) using a normal sputtering device.
) by sputtering, and
A titanium film 4 is formed.
次に、この基板ｌを４００〜８００℃で約３０分糧度窒
素雰囲気中で加熱処理してチタン膜４の表面にチタンナ
イトライド膜６を形成せしめると同時にチタン膜４と基
板シリフンの界面にチタンシリサイド層５を形成せしめ
る。Next, this substrate 1 is heat-treated at 400 to 800°C for about 30 minutes in a nitrogen atmosphere to form a titanium nitride film 6 on the surface of the titanium film 4, and at the same time to form a titanium nitride film 6 at the interface between the titanium film 4 and the substrate silicon. A titanium silicide layer 5 is formed.
次にこのチタンナイトライド膜６上全面に、通常のスパ
ッタリング法により、厚さ８０００にのアルミニウム配
線金属膜７を形成する。Next, an aluminum wiring metal film 7 having a thickness of 8000 mm is formed on the entire surface of the titanium nitride film 6 by a normal sputtering method.
ソノ後エツチングによりアルミニウム配線金属膜７とそ
の下のチタン膜４を連続的にエツチングし配線パター／
を形成する。After etching, the aluminum wiring metal film 7 and the titanium film 4 underneath are continuously etched to form a wiring pattern/
form.
このようにシリコン基板上にチタンシリサイド層５、チ
タン層４、チタンナイトライド層６、アルミニウム配線
金属層７の多層構造にすることにより、チタン、アルミ
ニウム配線金属層の二層構造よシ低抵抗にな夛、またチ
タン層４とアルミニウム配線金属層７がチタンナイトラ
イド層６により分離されているためチタン層４とアルミ
ニウム配線金属層７の反応がおさえられる。さらにチタ
ンナイトライド層６を形成したことにより、チタン層４
０表面酸化がおさえられ、表面酸化膜によるアルミニウ
ム配線金属層７との高接触抵抗化が防止できる。By creating a multilayer structure of the titanium silicide layer 5, titanium layer 4, titanium nitride layer 6, and aluminum wiring metal layer 7 on the silicon substrate in this way, the resistance is lower than that of the two-layer structure of titanium and aluminum wiring metal layers. Moreover, since the titanium layer 4 and the aluminum wiring metal layer 7 are separated by the titanium nitride layer 6, the reaction between the titanium layer 4 and the aluminum wiring metal layer 7 is suppressed. Furthermore, by forming the titanium nitride layer 6, the titanium layer 4
0 surface oxidation is suppressed, and high contact resistance with the aluminum wiring metal layer 7 due to the surface oxide film can be prevented.
なお、シリコン基板１上に形成する高融点金属層４は、
チタンに限る必要がなく、モリブデン、タングステン、
タンタルを用いても同様の効果が期待できる。またチタ
ン層の厚さは数百え程度あれば良〈実施例に示し北範囲
が適当である。アルミニウム配線金属膜７は、実施例の
如（８０００Ａの厚さにする必要はなく、配線の電流容
量などによシ適宜変えてかまわない。ま几配線材料とし
てアルミニウム以外の例えばアルミニウムシリサイド等
のものを用いてもよい。基板１はシリコｙ＆ｃ限らずＧ
ａＡｓで構成してもよいし、 ８ｏ８構造であってもよ
い。Note that the high melting point metal layer 4 formed on the silicon substrate 1 is
There is no need to limit it to titanium, but molybdenum, tungsten,
A similar effect can be expected by using tantalum. Further, the thickness of the titanium layer should be about several hundred digits (the northern range shown in the example is suitable). The aluminum wiring metal film 7 does not need to have a thickness of 8000 A as in the embodiment, and may be changed as appropriate depending on the current capacity of the wiring, etc. The wiring material may be made of a material other than aluminum, such as aluminum silicide, etc. The substrate 1 may be made of not only silico Y&C but also G
It may be composed of aAs or may have an 8o8 structure.
以上説明した如く、本発明は半導体装置の電極部分に低
抵抗のコンタクトを形成することができ、ｔｘ高融点金
属と配線金属の反応がかさえられ、この構造にするとと
くより信頼性を向上させることができる。As explained above, the present invention makes it possible to form a low-resistance contact in the electrode portion of a semiconductor device, suppresses the reaction between the tx high melting point metal and the wiring metal, and particularly improves reliability with this structure. be able to.
第１図（ａ）〜（ｄ）は本発明の一実施例を示す製造工
程断面図である。
１・・・シリコン半導体基板、２・・・不純物拡散層、
３・・・二酸化シリコン膜、４・・・チタン層、５・・
・チタンシリサイド膜、６・・・チタンナイトライド０
膜、７・・・アルミニウム配線金属膜。FIGS. 1(a) to 1(d) are sectional views showing manufacturing steps of an embodiment of the present invention. 1... Silicon semiconductor substrate, 2... Impurity diffusion layer,
3... Silicon dioxide film, 4... Titanium layer, 5...
・Titanium silicide film, 6...Titanium nitride 0
Film, 7... Aluminum wiring metal film.
Claims (1)
達する所要コンタクトホールを上記絶縁膜に形成する工
程と、上記絶縁膜上および上記コンタクトホールに露出
する上記半導体表面上に高融点金属膜を形成する工程と
、窒素雰囲気中で熱処理することにより上記金属表面を
窒化化合物に変換するとともに、上記金属と上記半導体
界面に金属シリサイド膜を形成する工程と、上記窒化化
合物上に配線層を形成する工程とを有することを特徴と
する半導体装置の製造方法。forming an insulating film on the semiconductor surface of the base body and forming a required contact hole in the insulating film reaching the semiconductor surface; and forming a high melting point metal film on the insulating film and on the semiconductor surface exposed to the contact hole. a step of converting the metal surface into a nitride compound by heat treatment in a nitrogen atmosphere and forming a metal silicide film at the interface between the metal and the semiconductor; and a step of forming a wiring layer on the nitride compound. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26441984A JPS61142739A (en) | 1984-12-17 | 1984-12-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26441984A JPS61142739A (en) | 1984-12-17 | 1984-12-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61142739A true JPS61142739A (en) | 1986-06-30 |
Family
ID=17402908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26441984A Pending JPS61142739A (en) | 1984-12-17 | 1984-12-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61142739A (en) |
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61183942A (en) * | 1985-02-08 | 1986-08-16 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS61212041A (en) * | 1985-03-18 | 1986-09-20 | Hitachi Ltd | Formation of metal silicide electrode and wiring |
| JPS6232610A (en) * | 1985-08-05 | 1987-02-12 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6384024A (en) * | 1986-09-26 | 1988-04-14 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPS63175420A (en) * | 1987-01-14 | 1988-07-19 | Nec Corp | Manufacture of semiconductor device |
| JPS63193522A (en) * | 1987-02-05 | 1988-08-10 | Nec Corp | Manufacture of semiconductor device |
| EP0279588A2 (en) * | 1987-02-19 | 1988-08-24 | Advanced Micro Devices, Inc. | Contact in a contact hole in a semiconductor and method of producing same |
| US4811078A (en) * | 1985-05-01 | 1989-03-07 | Texas Instruments Incorporated | Integrated circuit device and process with tin capacitors |
| US4811076A (en) * | 1985-05-01 | 1989-03-07 | Texas Instruments Incorporated | Device and process with doubled capacitors |
| JPH01298765A (en) * | 1988-05-27 | 1989-12-01 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| US4890141A (en) * | 1985-05-01 | 1989-12-26 | Texas Instruments Incorporated | CMOS device with both p+ and n+ gates |
| US4894693A (en) * | 1985-05-01 | 1990-01-16 | Tigelaar Howard L | Single-polysilicon dram device and process |
| JPH02238246A (en) * | 1989-03-09 | 1990-09-20 | Tokyo Gas Co Ltd | Hot-water/water supply device |
| US4960732A (en) * | 1987-02-19 | 1990-10-02 | Advanced Micro Devices, Inc. | Contact plug and interconnect employing a barrier lining and a backfilled conductor material |
| JPH04296020A (en) * | 1991-03-25 | 1992-10-20 | Nec Corp | Semiconductor device and manufactuer thereof |
| JPH0582772A (en) * | 1991-09-20 | 1993-04-02 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| US5371041A (en) * | 1988-02-11 | 1994-12-06 | Sgs-Thomson Microelectronics, Inc. | Method for forming a contact/VIA |
| US5374592A (en) * | 1992-09-22 | 1994-12-20 | Sgs-Thomson Microelectronics, Inc. | Method for forming an aluminum metal contact |
| US5395795A (en) * | 1991-04-09 | 1995-03-07 | Samsung Electronics Co., Ltd. | Method for fabricating a semiconductor device |
| US5472912A (en) * | 1989-11-30 | 1995-12-05 | Sgs-Thomson Microelectronics, Inc. | Method of making an integrated circuit structure by using a non-conductive plug |
| US5658828A (en) * | 1989-11-30 | 1997-08-19 | Sgs-Thomson Microelectronics, Inc. | Method for forming an aluminum contact through an insulating layer |
| US5930673A (en) * | 1990-11-05 | 1999-07-27 | Stmicroelectronics, Inc. | Method for forming a metal contact |
| US6242811B1 (en) | 1989-11-30 | 2001-06-05 | Stmicroelectronics, Inc. | Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature |
| US6271137B1 (en) | 1989-11-30 | 2001-08-07 | Stmicroelectronics, Inc. | Method of producing an aluminum stacked contact/via for multilayer |
| US6278150B1 (en) | 1996-09-05 | 2001-08-21 | Mitsubishi Denki Kabushiki Kaisha | Conductive layer connecting structure and method of manufacturing the same |
| US6287963B1 (en) | 1990-11-05 | 2001-09-11 | Stmicroelectronics, Inc. | Method for forming a metal contact |
| US6617242B1 (en) * | 1989-11-30 | 2003-09-09 | Stmicroelectronics, Inc. | Method for fabricating interlevel contacts of aluminum/refractory metal alloys |
-
1984
- 1984-12-17 JP JP26441984A patent/JPS61142739A/en active Pending
Cited By (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61183942A (en) * | 1985-02-08 | 1986-08-16 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS61212041A (en) * | 1985-03-18 | 1986-09-20 | Hitachi Ltd | Formation of metal silicide electrode and wiring |
| US4811078A (en) * | 1985-05-01 | 1989-03-07 | Texas Instruments Incorporated | Integrated circuit device and process with tin capacitors |
| US4894693A (en) * | 1985-05-01 | 1990-01-16 | Tigelaar Howard L | Single-polysilicon dram device and process |
| US4890141A (en) * | 1985-05-01 | 1989-12-26 | Texas Instruments Incorporated | CMOS device with both p+ and n+ gates |
| US4811076A (en) * | 1985-05-01 | 1989-03-07 | Texas Instruments Incorporated | Device and process with doubled capacitors |
| JPS6232610A (en) * | 1985-08-05 | 1987-02-12 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS6384024A (en) * | 1986-09-26 | 1988-04-14 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPS63175420A (en) * | 1987-01-14 | 1988-07-19 | Nec Corp | Manufacture of semiconductor device |
| JPS63193522A (en) * | 1987-02-05 | 1988-08-10 | Nec Corp | Manufacture of semiconductor device |
| EP0279588A2 (en) * | 1987-02-19 | 1988-08-24 | Advanced Micro Devices, Inc. | Contact in a contact hole in a semiconductor and method of producing same |
| US4960732A (en) * | 1987-02-19 | 1990-10-02 | Advanced Micro Devices, Inc. | Contact plug and interconnect employing a barrier lining and a backfilled conductor material |
| US5371041A (en) * | 1988-02-11 | 1994-12-06 | Sgs-Thomson Microelectronics, Inc. | Method for forming a contact/VIA |
| US5512516A (en) * | 1988-05-27 | 1996-04-30 | Fujitsu Limited | Contact structure for connecting an electrode to a semiconductor device and a method of forming the same |
| US5384485A (en) * | 1988-05-27 | 1995-01-24 | Fujitsu Limited | Contact structure for connecting an electrode to a semiconductor |
| JPH01298765A (en) * | 1988-05-27 | 1989-12-01 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
| JPH02238246A (en) * | 1989-03-09 | 1990-09-20 | Tokyo Gas Co Ltd | Hot-water/water supply device |
| US5658828A (en) * | 1989-11-30 | 1997-08-19 | Sgs-Thomson Microelectronics, Inc. | Method for forming an aluminum contact through an insulating layer |
| US5472912A (en) * | 1989-11-30 | 1995-12-05 | Sgs-Thomson Microelectronics, Inc. | Method of making an integrated circuit structure by using a non-conductive plug |
| US6617242B1 (en) * | 1989-11-30 | 2003-09-09 | Stmicroelectronics, Inc. | Method for fabricating interlevel contacts of aluminum/refractory metal alloys |
| US5976969A (en) * | 1989-11-30 | 1999-11-02 | Stmicroelectronics, Inc. | Method for forming an aluminum contact |
| US6242811B1 (en) | 1989-11-30 | 2001-06-05 | Stmicroelectronics, Inc. | Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature |
| US6271137B1 (en) | 1989-11-30 | 2001-08-07 | Stmicroelectronics, Inc. | Method of producing an aluminum stacked contact/via for multilayer |
| US6287963B1 (en) | 1990-11-05 | 2001-09-11 | Stmicroelectronics, Inc. | Method for forming a metal contact |
| US5930673A (en) * | 1990-11-05 | 1999-07-27 | Stmicroelectronics, Inc. | Method for forming a metal contact |
| JPH04296020A (en) * | 1991-03-25 | 1992-10-20 | Nec Corp | Semiconductor device and manufactuer thereof |
| US5395795A (en) * | 1991-04-09 | 1995-03-07 | Samsung Electronics Co., Ltd. | Method for fabricating a semiconductor device |
| JPH0582772A (en) * | 1991-09-20 | 1993-04-02 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| US5374592A (en) * | 1992-09-22 | 1994-12-20 | Sgs-Thomson Microelectronics, Inc. | Method for forming an aluminum metal contact |
| US6433435B2 (en) | 1993-11-30 | 2002-08-13 | Stmicroelectronics, Inc. | Aluminum contact structure for integrated circuits |
| US6278150B1 (en) | 1996-09-05 | 2001-08-21 | Mitsubishi Denki Kabushiki Kaisha | Conductive layer connecting structure and method of manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS61142739A (en) | Manufacture of semiconductor device | |
| US4283439A (en) | Method of manufacturing a semiconductor device by forming a tungsten silicide or molybdenum silicide electrode | |
| US5093710A (en) | Semiconductor device having a layer of titanium nitride on the side walls of contact holes and method of fabricating same | |
| JPS63127551A (en) | Manufacture of semiconductor device | |
| GB2077993A (en) | Low sheet resistivity composite conductor gate MOS device | |
| JPS58500680A (en) | Semiconductor device with low resistance synthetic metal conductor and method for manufacturing the same | |
| JPS62113421A (en) | Manufacture of semiconductor device | |
| JPS6190445A (en) | Semiconductor device | |
| EP0082012B1 (en) | Multilayer electrode of a semiconductor device | |
| JPS609159A (en) | Semiconductor device | |
| JPS5910271A (en) | Semiconductor device | |
| KR960002061B1 (en) | Metalization method of semiconductor device | |
| JPS60182133A (en) | Manufacture of semiconductor device | |
| JPS61174767A (en) | Semiconductor element electrode | |
| JPS5821821B2 (en) | Handout Taisouchinodenkiyokukeiseihouhou | |
| JP2850380B2 (en) | Method for manufacturing semiconductor device | |
| JPS5873136A (en) | Method of producing semiconductor device | |
| JPS641064B2 (en) | ||
| JPH0578181B2 (en) | ||
| JP3372109B2 (en) | Semiconductor device | |
| KR100199526B1 (en) | Semiconductor device and manufacturing method of the same | |
| JPS61156837A (en) | Manufacture of semiconductor device | |
| JPS5898968A (en) | Semiconductor device | |
| KR100222124B1 (en) | Method for forming metalization in semiconductor device | |
| JPS59227119A (en) | Silicon semiconductor device |