JP3372109B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to an input offset voltage,
The present invention relates to a semiconductor device such as a power supply IC capable of adjusting output voltage and the like. In particular, the present invention relates to a semiconductor device such as an analog integrated circuit which achieves high precision by adjusting a resistance value.

[0002]

2. Description of the Related Art An analog integrated circuit, which is required to have high precision, adjusts a load resistance value and the like on a chip after a metallization process. This adjustment is known as resistance trimming, but conventionally, as shown in FIGS. 12 to 15, a Zener diode is connected to the resistor, and the anode and cathode of this Zener diode are short-circuited by an overcurrent. (Zener zap method). 12-15
Shows an example of a connection method used in the Zener Zap method, but there are various connection methods other than this, which are selected according to an integrated circuit (hereinafter referred to as an IC) to be adjusted, its resistance value, and the like, and are widely used. It's being used.

FIG. 9 is a plan view showing a specific example on the semiconductor substrate (chip) of the equivalent circuit shown in FIG. 15, and FIG. 10 is shown in FIG.
3 is a cross-sectional view taken along line AA ′ of FIG. Resistors R ₁ , R ₂ , ...,
R ₅ is formed by the p-type resistor diffusion region 14 formed in the n-type semiconductor substrate 41, and the zener diode Z ₁ ,
Z ₂ , ..., Z ₅ are formed by the p ⁺ anode region 51 and the n ⁺ cathode region 52 formed in the p-type region 53. , 166 are led to the respective bonding pads a, b, ..., F so that a voltage can be applied. Al wiring 16
1, 162, p-type diffusion region 14, p ⁺ anode region 5
1. When the contact hole opened in the insulating film 15 for connecting to the n ⁺ cathode region 52 is about 8 μm ^{□ and} the mask alignment margin in the IC manufacturing process is 4 μm, the breakdown voltage of the Zener diode is taken into consideration. The occupied dimension d of the Zener diode shown in FIGS. 9 and 10 is usually 50 to 60 μm, so that the occupied area of the Zener diode becomes large and the chip size of the semiconductor IC becomes unnecessarily large.

Further, the residual resistance value of the destroyed PN junction of the Zener diode after the Zener zap has a variation of about 20 to 40 Ω in the case of the above size, so that the reproducibility is poor and the productivity is lowered. .

[0005]

In view of the above problems, an object of the present invention is to provide a novel semiconductor device capable of reducing the area of a region required for resistance trimming and reducing the chip area of the entire IC. That is.

Another object of the present invention is to provide a semiconductor device which can perform resistance trimming with high reproducibility without having to consider variations in residual resistance and the like.

[0007]

In order to solve the above problems, the first feature of the present invention is to provide a resistor (14) formed on a part of the surface of a semiconductor substrate as shown in FIG. A thick insulating film (15) formed on the resistor (r), first and second contact holes (81, 82) penetrating the thick insulating film to reach the resistor, and A thin insulating film (29) formed on the exposed surface of the resistor of the first contact hole, and a first metal wiring (which reaches the first thin insulating film through the first contact hole ( 16
9) and a second metal wiring (16) connected to the resistor via the second contact hole, and at least a predetermined number of them are formed between the first and second metal wirings. Voltage V
A trimming circuit formed in the peripheral portion of the semiconductor IC chip for adjusting the resistance value by applying t to destroy the thin insulating film and short-circuit the first metal wiring and the resistor. (The equivalent circuit of FIG. 1 is shown in FIG. 2).

A second feature of the present invention is that, as shown in FIGS. 5 and 6, at least one of the first and second metal wirings has a second resistor different from the resistor (r). (R) is connected. FIG. 6 shows the case of r≈0.

A third feature of the present invention is that the resistor is a second conductivity type semiconductor region (14) formed on the surface of the first conductivity type semiconductor region (13) as shown in FIG. is there. That is, a p-type diffusion region or p in an n-type semiconductor
A resistor is formed by the n-type diffusion region in the type semiconductor.

A fourth feature of the present invention is that the resistor is an insulating film (15) on the surface of the semiconductor substrate (41) as shown in FIG.
5) is formed from the polycrystalline silicon film (144) formed on the upper part of the above (5).

The fifth feature of the present invention is that, as shown in FIG. 8, a high melting point of TiSi ₂ , WSi ₂ , MoSi ₂ , TaSi ₂ or the like is provided between the thin insulating film (29) and the resistor (144). That is, the metal silicide film 299 is formed.

A sixth feature of the present invention is that the thin insulating film is
TiO ₂ , WO ₂ , MoO of the oxide film of the silicide film
₂ , Ta ₂ O ₅ , SiO ₂ , or the like.

A seventh feature of the present invention is that the thin insulating film is
That is, it is an oxide film of porous silicon.

[0014]

In the semiconductor device of the first feature of the present invention, a thin insulating film (hereinafter referred to as a trimming insulating film) is formed by applying a predetermined voltage Vt, not by destroying the pn junction of the Zener diode in the conventional Zener zap method. Destroy the
The resistor and the first metal wiring are short-circuited to change the connection of the trimming circuit. Therefore, the area for forming the Zener diode, which has been required to have a relatively large area of about 50 to 60 μm square for each conventional circuit changing element, is unnecessary, and the semiconductor IC can be miniaturized. In the semiconductor device of the first feature of the present invention, it can be said that the resistor and the circuit connection changing element are integrated. Also, because it is a dielectric breakdown of the insulator,
There is no problem of residual resistance after destruction of the Zener diode.

The semiconductor device of the second feature of the present invention can be applied to various circuits conventionally used in the Zener zap method. At that time, however, the area for the contact hole for forming the trimming insulating film, for example, about 8 μm □. I'm fine
Since the occupied area is much smaller than that of the Zener diode, the IC can be downsized.

According to the third aspect of the present invention, the resistor is formed in the diffusion region, and according to the fourth aspect of the present invention, the resistor is formed of polycrystalline silicon. That is, since the trimming resistor can be selected and formed according to the size of the resistance value of the trimming circuit and the characteristics of the IC that is the main body, the resistance value can be easily adjusted.

According to the fifth aspect of the present invention, since the silicide film is formed under the trimming insulating film, an ohmic contact with a good resistance between the first metal wiring and the resistor is formed after the destruction of the trimming insulating film. Therefore, the problem of residual resistance and the problem of deterioration of reproducibility due to variations in contact resistance after dielectric breakdown do not occur.

A sixth feature of the present invention is that the trimming insulating film is the oxide film of the silicide film described in the fifth feature,
It is easy to form an oxide film. Further, in the oxidation of the silicide film, SiO ₂ is formed on the high temperature side and TiO ₂ and MoO ₂ are formed on the low temperature side due to the oxidation temperature. Therefore, depending on the trimming voltage Vt, the film quality such as the withstand voltage of the trimming insulating film is changed. You can choose. That is, in the case of an ordinary thermal oxide film, the thickness t _tox of the trimming insulating film must be _set to 3 to 5 nm in order to destroy the insulating film at a low Vt, but such a thin oxide film causes a tunnel current and leaks. There is a current problem. In the case of an oxide film of a silicide film, dielectric breakdown can occur at a relatively low Vt, even if the film thickness is large so that tunnel current does not flow.

According to the seventh feature of the present invention, like the sixth feature, it is possible to form a trimming insulating film in which a tunnel current does not flow and which has a low dielectric breakdown voltage.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. The same parts as those in FIGS. 9 and 10 used in the description of the conventional technique are designated by the same reference numerals.

FIG. 1 is a sectional view of a semiconductor device according to the first embodiment of the present invention, and FIG. 2 is its equivalent circuit. FIG. 2 corresponds to FIG. 13 used in the description of the conventional technique.
The trimming insulating film 29 having the same function as that of the Zener diode Z connected in series with the resistor r is used. Figure 1
As is clear from the above, the trimming insulating film 29 is formed thinner than the other insulating films 15. Trimming insulation film 2
The thickness t _tox of 9 should be about 1 to ₁₀₀ nm,
Preferably, direct tunnel conduction does not become dominant t
_{It is preferable that tox} > 6 nm or more. The value of t _tox may be selected according to the characteristics such as the operating voltage of the IC. Therefore, in the case of a power IC, t _tox > 50 nm. When the trimming insulating film 29 is a thermal oxide film, if the trimming voltage V _t = 30 V, t _tox = about 20 nm and V _t = 1.
If 5V, t _tox = 10 nm may be set.

FIG. 1 shows an embodiment of a trimming circuit formed in the peripheral portion of a bipolar IC, in which an n-type epitaxial growth layer 13 is formed on an n ⁺ buried region 12 formed on a p-type substrate 11. Although the example in which the p-type resistor diffusion region 14 is formed above is shown, the n ⁺ buried region 12 is not essential and may be omitted.
Further, similarly to FIG. 10, the p-type resistor diffusion region 14 may be formed on the n-type semiconductor substrate 41. The thickness of the insulating film 15 is 3
The thickness is about 50 to 1000 nm, and the metal wiring 16 such as Al or Al—Si is connected to the p-type resistor region 14 through the contact hole in the insulating film 15. The metal wiring 169 is connected to the trimming insulating film 29 and is insulated from the resistor diffusion region 14. SiO _2, PSG or passivation such as polyimide, (surface protective) film 1
The metal wiring 169 is connected to the voltage terminal (a) through the hole of No. 7.
And the metal wiring 16 is connected to the voltage terminal (b).
A predetermined trimming voltage Vt is applied between the voltage terminals (a) and (b).
If the trimming insulating film 29 is destroyed by applying the voltage (a)-
Between (b), the resistance r determined by the p-type resistor diffusion region 14
And if the voltage is Vt or less, the resistance becomes infinite between (a) and (b).

First and second manufacturing methods of the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. First, in the first manufacturing method, as shown in FIG. 3, (a) an n ⁺ buried region 12 is formed on a p-type semiconductor substrate 11.
Is further formed, and then an n-type epitaxial growth layer 13 is formed thereon, and vapor phase diffusion using an oxide film as a mask or ¹¹ B ⁺ or ⁴⁹ using a photoresist or the like as a mask is performed on the n-type epitaxial growth layer 13. BF ₂ ⁺
Forming a p-type resistor diffusion region 14 by ion implantation of
On top of that, as shown in FIG. 3A, a thick insulating film 1 is formed.
5, an oxide film 15 of 350-1000 nm, for example, is formed by thermal oxidation or CVD. If the body is a bipolar IC, the p-type resistor diffusion region 14 is formed at the same time as the formation of the p-type base layer of the bipolar transistor, at the same time as the impurity density of the base layer, for example, about 2 × 10 ¹⁷ −3 × 10 ¹⁸ cm ^−3. Good. The length l of the p-type resistance diffusion region 14 is
It may be determined according to the target resistance value, for example, 20
-300 μm. As described with reference to FIG. 1, the formation of the n ⁺ buried region 12 may be omitted.

(B) Next, as shown in FIG. 3B, the oxide film 15 in the portion where the trimming insulating film is to be formed is removed by etching using photolithography, and the contact hole 8 is formed.
1 is opened. Depending on the IC design, for example the dimensions of the contact hole 81 is set to 8 [mu] m ^□ or 14 [mu] m ^□. Next, inside the contact hole 81, a trimming insulating film 29 is formed with a thickness t _{tox of} 1 to ₁₀₀ nm.
The trimming insulating film 29 may be formed by thermal oxidation or CV.
D method or plasma oxidation may be used. Especially contact hole 8
The p-type resistor diffusion region 29 having a depth of 10 to 50 nm from the surface exposed on the surface of No. 1 may be made into porous silicon by using the anodization method and oxidized. When performing the anodization method, the thick insulating film 15 should be a Si ₃ N ₄ film,
A carbon film may be formed on the surface by reverse sputtering of CF ₄ . When porous silicon is oxidized, it has a characteristic that a relatively thick (t _tox > 20 nm) oxide film in which a tunnel current does not easily flow is formed and the dielectric breakdown voltage can be lowered. Further, the oxide film of porous silicon has a characteristic that the dielectric breakdown voltage becomes high due to heat treatment after resistance trimming or a change with time, so that it becomes a stable insulating film. In the case of a low voltage IC, the exposed p-type resistor diffusion region of the contact hole 81 is set to HNO ₃ or H ₂ SO at 60 to 70 ° C.
_By washing in ₄ solution and then exposing to the atmosphere, a natural oxide film of 1 to 2 nm is obtained. Alternatively, the porous silicon is washed with HNO ₃ or H ₂ SO ₄ and then exposed in the air or baked in oxygen at 80 to 100 ° C.
A thin oxide film of 10 nm is obtained.

The trimming insulating film 29 can also be formed by forming a refractory metal silicide in the contact hole 81 and oxidizing the surface thereof. In particular, in this method, since the refractory metal silicide is formed between the trimming insulating film 29 and the p-type resistor diffusion region 14, the metal wiring 169 and the p-type resistor diffusion region 14 are destroyed after the destruction of the trimming insulating film 29. The ohmic contact is improved, and highly reproducible and stable resistance trimming can be realized. For example, Ti is vacuum-deposited while leaving the photoresist used for opening the contact hole 81, and then Ti is formed only inside the contact hole 81 by lift-off to remove the photoresist, and then Ti is formed at 800 ° C. for 45 minutes.
When a Si ₂ film is formed and further oxidized at 700 ° C. in oxygen, T as a trimming insulating film is formed on the surface of the TiSi ₂ film
iO ₂ can be formed. Also, TiSi ₂ is added at 1000 ° C. 60
By partial oxidation, TiO ₂ on the surface disappears, and the surface becomes SiO 2.
₂ and the underlying layer becomes TiSi ₂ . TiO ₂ or SiO ₂ may be used as the trimming insulating film. WSi ₂ , MoSi ₂ and TaSi ₂ may be oxidized to form WO ₂ , MoO ₂ and Ta ₂ O ₅ .

(C) Next, as shown in FIG. 3C, the p-type resistor diffusion region and the metal wiring 1 are formed by photolithography.
A contact hole 82 for connecting with 6 is opened. The oxide film 15 may be etched using the photoresist film 26.

(D) Next, after removing the photoresist film 26, Al, Al-Si, Al-Cu-Si, or the like is formed by vacuum vapor deposition or sputtering, and is shown by photolithography in FIG. 3 (d). Like metal wiring 16
9 and 16 are formed. It should be noted that when a dielectric breakdown of the trimming insulating film occurs, a large current may locally flow to melt and scatter the metal wiring 169 such as Al. Therefore, the thickness of Al is preferably about 1.3 μm or more. More preferably, the metal wirings 169, 16 are made of a high melting point metal such as Ti, W, Mo. Although not shown in the subsequent steps, if the passivation film 17 is formed and the bonding pad portion is opened, the semiconductor device of the first embodiment of the present invention shown in FIG. 1 is completed.

FIG. 4 shows a second manufacturing method for manufacturing the semiconductor device of the first embodiment of the present invention. FIG. 4A shows FIG.
Since it is exactly the same as (a), the description is omitted. Next in FIG.
As shown in (b), the contact hole 81 in the portion where the trimming insulating film is formed and the contact hole 82 portion for the p-type resistor 14 and the metal wiring are simultaneously opened by photolithography. Next, a thin trimming insulating film is formed by CVD, vacuum deposition, sputtering, or thermal oxidation.
Formed as shown in FIG. 4C with a thickness of ˜100 nm,
If only the portion to be left as the final trimming insulating film is covered with the photoresist film 26 and the remaining portion is removed by etching, the result is as shown in FIG. After that, the metallization step may be performed as in the first method.

According to the first embodiment of the present invention, since the trimming insulating film is formed in the portion where the p-type resistor diffusion region 14 is formed, the equivalent circuit is shown in FIGS.
However, in terms of the structure, the area for forming the Zener diode Z is not necessary, and the area can be greatly reduced. An actual structure for realizing FIG. 13 is shown in FIG. 11. The p ⁺ region 51 is the anode region of the Zener diode and the n ⁺ region 52 is the cathode region. It can be seen that FIG. 1 is significantly downsized as compared with the structure of FIG. 11 used for the conventional Zener Zap method.

FIG. 5 shows a second embodiment of the present invention and corresponds to FIG. 13 described in the prior art. This trimming circuit is an equivalent circuit in which a resistor r is connected in series to the trimming insulator 29, and a resistor R is connected in parallel to this series connection. In the trimming circuit of FIG. 5, a current flows between (a) and (b) (resistance R) because of the trimming insulating film. That is, (a) before resistance trimming,
The resistance value between (b) is R.

Next, when a predetermined trimming voltage Vt is applied between the pads (c) and (d) to destroy the trimming insulating film 29 and change the resistance connection in the trimming circuit,
The resistance value is (r · R) / (R + r), and (a),
The current between (b) flows through the resistors R and r.

This trimming circuit is used under the following conditions.
The voltage applied between (a) and (b) (when used only with the resistor R) is the voltage V when the trimming insulating film 29 is destroyed.
It must be used at a voltage lower than t (voltage applied between (a) and (b)). Any circuit satisfying this condition can be freely trimmed. Further, when the trimming insulating film 29 is destroyed, it is different from the junction (PN junction) destruction, and therefore the influence of the residual resistance value after the destruction is small. Especially trimming insulating film is formed by oxidation of TiSi _2, 2-layer structure of TiO ₂ and TiSi _2,
Alternatively, if a refractory metal silicide is formed below the trimming insulating film 29 so as to have a two-layer structure of SiO ₂ and TiSi ₂ , contact failure after destruction does not occur and the residual resistance value is ignored. it can. The refractory metal silicide may be WSi ₂ , MoSi ₂ , Ta ₂ Si or the like. In the case of the metal wirings 169, 16 made of Al, Al-Si, or the like, it is desirable to perform heat treatment at 400 to 450 ° C. for about 10 to 30 minutes after breaking the trimming insulating film 29. When the metal wirings 169 and 16 are made of a high melting point metal such as Ti or W, it is desirable to perform a heat treatment at 700 ° C. to 1000 ° C. for about 30 seconds after the dielectric breakdown.

FIG. 6 is a third embodiment of the present invention and corresponds to FIG. 15 described as the prior art. Resistance R ₁
And a trimming insulating film 291 in parallel, a resistor R ₂ and a trimming insulating film 292 in parallel, ..., A resistor R ₅ and a trimming insulating film 295 in parallel. A plan view of a specific example on the chip of FIG. 6 is shown in FIG. The sectional view taken along the line BB 'in FIG. 7 corresponds to FIG. However, the metal wiring 162 in FIG. 7 corresponds to the metal wiring 169 in FIG. 1, the metal wiring 161 corresponds to the metal wiring 16 in FIG. 1, and the trimming insulating film 291 corresponds to the trimming insulating film 29. Since the trimming circuits of FIGS. 6 and 7 have trimming insulating films 291, 292, ..., 295, the resistance value between (a) and (f) is initially R _T = R.
₁ + R ₂ + ... + R ₅ . For example, if a predetermined voltage V _tab is applied between the pads (a) and (b), the pads (a) and (b) are short-circuited, and the total resistance R _T is R _2.
+ R ₃ + ... + R ₅ . If the pads (e) and (f) are further short-circuited, the total resistance R _T = R ₂ +3 ₃ + R ₄ is obtained. A desired resistance R _T can be obtained by repeating such an operation. In addition, referring to FIG. 9, which is a plan view showing the corresponding specific example of FIG. 15, in the third embodiment of the present invention, the area occupied by the Zener diode in the related art is not necessary, and the chip area is significantly reduced. It can be seen that various reductions are possible. In the present invention, the trimming insulating films 291, 2
92, ..., there be good if there is space for a contact hole to form a 295, p ⁺ diffusion, n ⁺ diffusion region formed in the space, as in this space Zener diode, a mask alignment margin for these ,
Alternatively, it is not necessary to consider the radius of curvature of the p ⁺ diffusion region and the n ⁺ diffusion region, which are necessary for the breakdown voltage design.

FIG. 8 shows a case where the polycrystalline silicon 144 formed on the oxide film 155 on the n-type semiconductor substrate is used as the resistor in the fourth embodiment of the present invention. Others are the same as those in FIG. 1, but TiSi ₂ , W is formed under the trimming insulating film 29.
Silicide film 29 of Si ₂ , MoSi ₂ , TaSi ₂ or the like
9 is formed. When the resistance value of the trimming resistor is large, the structure of FIG. 8 is effective.

In the above description, the case where the p-type resistor diffusion region is used has been described, but it goes without saying that the conductivity types may be all reversed to form the n-type resistor diffusion region. Further, the semiconductor is not limited to Si, and GaAs, In
A compound semiconductor such as P or SiC may be used.

[0036]

According to the trimming circuit according to the first, third and fourth aspects of the present invention, the area of the Zener diode, which is conventionally required for the Zener zap circuit, is completely unnecessary. Further, according to the semiconductor device having the trimming circuit according to the second, third and fourth aspects of the present invention, only the space for the contact hole for forming the trimming insulating film is required.
In particular, as shown in the comparison between FIG. 1 and FIG. 11 or the comparison between FIG. 7 and FIG. 9, a desired resistance value or the like is adjusted. It is not necessary and the IC size can be greatly reduced.

Further, since the PN junction between the anode and cathode of the Zener diode is conventionally destroyed and short-circuited, the trimming circuit must be designed in consideration of the variation in the residual resistance value of the PN junction at this time. However, in the present invention, since the insulating film is destroyed, the residual resistance (P
The variation of (N-junction only) is suppressed.

Particularly, according to the trimming circuit of the fifth and sixth aspects of the present invention, since the refractory metal silicide is formed under the trimming insulating film, the metal wiring and the resistor diffusion after the insulating film is destroyed. The ohmic contact with the region is extremely good, there is no variation, and reproducibility is high.

According to the semiconductor device of claim 7 of the present invention, the withstand voltage of the porous silicon is low before the resistance trimming and is high after the resistance trimming due to the heat treatment and the aging after the resistance trimming. Because you can
This has the advantage that dielectric breakdown occurs at a low trimming voltage V _t and thereafter a stable high breakdown voltage is obtained.

Therefore, according to the present invention, a highly accurate semiconductor device, particularly an analog IC, can be easily manufactured with high productivity.

[Brief description of drawings]

FIG. 1 is a sectional view of a trimming circuit according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit of FIG.

FIG. 3 is a sectional view illustrating a first manufacturing method for manufacturing the structure of FIG.

4 is a cross-sectional view illustrating a second manufacturing method for manufacturing the structure of FIG.

FIG. 5 is an equivalent circuit of a trimming circuit according to a second embodiment of the present invention.

FIG. 6 is an equivalent circuit of a trimming circuit according to a third embodiment of the present invention.

FIG. 7 is a plan view of the semiconductor chip of FIG.

FIG. 8 is a sectional view of a trimming circuit according to a fourth embodiment of the present invention.

FIG. 9 is a plan view on a semiconductor chip of a trimming circuit in the Zener zap method of the related art.

10 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 11 is a cross-sectional view of a trimming circuit in the Zener Zap method of the related art.

FIG. 12 is an example of a trimming circuit in the Zener Zap method of the related art.

FIG. 13 is an example of a trimming circuit in a Zener Zap method according to the related art.

FIG. 14 shows an example of a trimming circuit in the Zener Zap method of the related art.

FIG. 15 shows an example of a trimming circuit in the Zener Zap method of the related art.

[Explanation of symbols]

11 p-type semiconductor substrate 12 n ⁺ buried region 13 n-type epitaxial growth layer 14 p-type resistor diffusion region 15 insulating films 29, 291, 292, ..., 295 trimming insulating films 161, 162, ... 165, 168, 169 metal wiring 17 Passivation (surface protection) films 81, 82 Contact hole 26 Photoresist film 41 n-type semiconductor substrate 144 Polycrystalline silicon resistor 299 Silicide film

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 21/82 H01L 27/04

Claims (5)

(57) [Claims] And 1. A resistor formed on a part of the semiconductor substrate surface, a thick insulating film formed on top of the resistive element antibodies through the said thick insulating film, first reaching the resistor In the contact hole , a refractory metal silicide film formed on the surface of the resistor and in the first contact hole , the silicidation film is formed.
From the oxide film of the silicide film formed on the surface of the oxide film
A thin insulating film made of the first metal interconnection reaching the first contact said thin insulating film through the hole, through the thick insulating film, through a second contactee hole reaching the resistor wherein a second metal wiring connected to the resistor, by applying a predetermined voltage between the first and second metal wires, to destroy the thin insulating film,
By short-circuiting the said resistor and said first metal wiring, a semiconductor device which is characterized in that the resistance value adjustment. 2. The semiconductor device according to claim 1 , wherein a second resistor different from the resistor is connected to at least one of the first and second metal wirings. 3. The semiconductor device according to claim 1, wherein the resistor is a second conductivity type semiconductor region formed on the surface of the first conductivity type semiconductor region. 4. The semiconductor device according to claim 1, wherein the resistor is formed of a polycrystalline silicon film formed on the insulating film on the surface of the semiconductor substrate. 5. A resistor formed on a part of the surface of a semiconductor substrate.
A body, a thick insulating film formed on the resistor, and a first insulating film penetrating the thick insulating film to reach the resistor.
Formed on the surface of the resistor in the contact hole.
A thin insulating film made of a porous silicon oxide film and formed on the thin insulating film through the first contact hole.
A second metal wire that reaches the resistor by penetrating the first metal wiring and the thick insulating film.
A second resistor connected to the resistor via a contact hole
A metal wiring and the first and second metal wiring
Applying a predetermined voltage between them to destroy the thin insulating film,
By short-circuiting the first metal wiring and the resistor
A semiconductor device characterized in that the resistance value is adjusted.