JPS60227469A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60227469A JPS60227469A JP8457084A JP8457084A JPS60227469A JP S60227469 A JPS60227469 A JP S60227469A JP 8457084 A JP8457084 A JP 8457084A JP 8457084 A JP8457084 A JP 8457084A JP S60227469 A JPS60227469 A JP S60227469A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- wirings
- elements
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000010936 titanium Substances 0.000 claims description 13
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 229910001080 W alloy Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021340 platinum monosilicide Inorganic materials 0.000 abstract description 2
- 230000004888 barrier function Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、半導体装置に係シ、特に回路素子のコンタク
ト部やシ冒ットキーバリャダイオード（以下’ ＳＢＤ
“と記す）形成領域に白金シリサイド（以下’ ｐｔＳ
ｉ“と記す）ｔ−有する半導体装置に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor devices, and in particular to contact portions of circuit elements and shield barrier diodes (hereinafter referred to as 'SBD').
Platinum silicide (hereinafter referred to as 'ptS) is formed in the formation region
The present invention relates to a semiconductor device having t- (denoted as "i").
従来、バイポーラ集積回路では１回路素子のコンタクト
やＳＢＤ形成１ｃ Ｐ ｔ Ｓ ｉ が用いられること
が多いが、前記ｐｔＢｔ を用いる場合、ｐｔＳｉ上に
直接アルミ（Ａｔ、）膜を付けるとｐｔＳｔ とＡｔが
反応し、ｐｔＳｉ上の基板シリコン（Ｓｉ）がすい上げ
られ、ｐｔＳｉ コンタクト下のＰＮ接合が破壊された
シ、又ＰｔＡｔ２の形成により。Conventionally, in bipolar integrated circuits, single-circuit element contacts or SBD formation 1c P t Si are often used, but when using the ptBt described above, if an aluminum (At) film is directly attached on the ptSi, the ptSt and At As a result of the reaction, the substrate silicon (Si) on the ptSi was scooped up and the PN junction under the ptSi contact was destroyed, also due to the formation of PtAt2.
ＳＢＤの電位障壁が変わったシするので通常はｐｔ３ｉ
とｋｌの間にはバリヤ膜を入れている。Since the potential barrier of SBD has changed, it is usually pt3i.
A barrier film is inserted between and kl.
このバリヤ膜としては、ＴｉとＷとの合金（以下’Ｔｔ
−ｗ“と記す）膜がそのバリヤ性の強さ力ら最もよく用
いられている。しかしながら前記Ｔｉ−Ｗとその上に付
層されるＡｔからなる二層金践を素子間の配線として用
いると、Ｔｉ−ｗと該Ｔｉ−Ｗ下のシリコン酸化膜（Ｓ
ｉ０２）との密着性が悪＜Ｔｉ−Ｗ／Ａｔ配線が剥れる
という問題があシＴｉ−Ｗは、ｐｔＳｉ形成領域のみに
選択的に残して配線はＡｔのみで行なうことで対処する
場合が多かった。しかしこの方法では、製造プロセスが
長くなったシ、又Ｔ ｉ−ＷとｐｔＳｉ間、Ｔｉ−Ｗと
Ａｔ間の設計マージンをとる必要から素子の微細化が難
しいと った様な１問題が生じていた。As this barrier film, an alloy of Ti and W (hereinafter 'Tt
-w'' is the most commonly used film due to its strong barrier properties.However, a two-layer metal layer consisting of Ti-W and At layered thereon is used as wiring between elements. , Ti-w and the silicon oxide film (S) under the Ti-W.
Poor adhesion with i02) <There is a problem of peeling of Ti-W/At wiring.Ti-W may be solved by leaving it selectively only in the ptSi formation area and wiring only with At. There were many. However, this method has problems such as a longer manufacturing process and the need to take design margins between Ti-W and ptSi and between Ti-W and At, making it difficult to miniaturize the device. was.
本発明の目的は、従来技術の欠点を除き、高信頼の配線
を実現し高速で高集積密度化の期待できる半導体装置を
提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and provide a semiconductor device that realizes highly reliable wiring and can be expected to achieve high speed and high integration density.
本発明の半導体装置は、充分に薄いＴｉ膜上にＴｉ−Ｗ
合金膜を有し、更に該Ｔｉ−Ｗ膜上にＡｔ膜を有する三
層金属膜を素子間の配線として用いることを特徴とする
。The semiconductor device of the present invention has Ti-W on a sufficiently thin Ti film.
It is characterized in that a three-layer metal film having an alloy film and further having an At film on the Ti--W film is used as wiring between elements.
本発明によればＴｉ−Ｗ膜とＳｉＯ□との間にはＴｉ膜
が入れられており、又、Ｔｉ膜はＴｉ−Ｗ膜に比較する
と、５ｔＯ２との密着性が良く。According to the present invention, a Ti film is inserted between the Ti--W film and the SiO□, and the Ti film has better adhesion to 5tO2 than the Ti--W film.
しかもＴｉ膜とＴ ｉ−Ｗ膜間の密着性も良い為に従来
のＴ ｉ −Ｗ／ Ａ Ｌ構造の配線でのＳｔＯ，との
密着不良というような整置はなく、かつ製造プロセスを
複雑にすることなしに微細配線を実現でき、このＴｉ／
Ｔｉ−Ｗ／Ａｔ構造の配線を集積回路上組込むことによ
り高速で高集積密度の半導体装置が得られる。Moreover, because the adhesion between the Ti film and the Ti-W film is good, there is no alignment problem such as poor adhesion with StO in the wiring of the conventional Ti-W/AL structure, and the manufacturing process is not complicated. This Ti/
By incorporating wiring having a Ti-W/At structure on an integrated circuit, a semiconductor device with high speed and high integration density can be obtained.
従来構造と比較しながら本発明の一実施例について説明
する。第１図及び第２図は、従来構造を示す断面図であ
り、第３図は、本発明の一実施例金示す断面図である。An embodiment of the present invention will be described while comparing it with a conventional structure. 1 and 2 are sectional views showing a conventional structure, and FIG. 3 is a sectional view showing an embodiment of the present invention.
第１図に示す従来構造の一実施例Ｉは素子のコンタクト
部分にＰｔＳｉ を形成後、Ｔｉ−Ｗ膜１０４とＡｌ１
１０５’に付宥し、フォトレジストマスクとして選択的
にＴｉ−ＷとＡｔｋエツチングし。Embodiment I of the conventional structure shown in FIG.
105' and selectively etched Ti-W and Atk as a photoresist mask.
素子の電極形成と素子間の配線を形成している。Forms electrodes of elements and wiring between elements.
しかしこの構造ではＴ ｉ−Ｗ膜（１０４）と５ｉ０２
１０２との間で（第１図円内）剥れが生じ易いため、第
２図に示す様な従来構造がよく用いられる。However, in this structure, the Ti-W film (104) and 5i02
102 (inside the circle in FIG. 1), a conventional structure as shown in FIG. 2 is often used.
この構造は、ｐｔＳｉ 形成後、Ｔｉ−Ｗ膜２０４を付
着し、フォトレジストをマスクとして選択的にＴｉ−Ｗ
をエツチングし、ｐｔｓｉ部分のみ’ｌ’ｉ−Ｗ膜２０
４を残す。次にＡｔ膜１０５を付着し。In this structure, after forming ptSi, a Ti-W film 204 is attached, and the Ti-W film 204 is selectively deposited using a photoresist as a mask.
and etched the 'l'i-W film 20 only on the ptsi part.
Leave 4. Next, an At film 105 is attached.
フォトレジストをマスクとして選択的にＡｔを除去し、
配線を形成する。この構造では、配線の剥れる事はない
が、製造プロセスが複雑になシ、Ｔｉ−Ｗ２Ｏ４とＰｔ
５ｉ１０３との設計マージンとＴｉ−Ｗ２Ｏ４とＡｔ１
０５との設計マージをある程度とらなければならないの
で素子の微細化が困離である。selectively removing At using a photoresist as a mask;
Form wiring. With this structure, the wiring will not peel off, but the manufacturing process will be complicated, and Ti-W2O4 and Pt
Design margin with 5i103 and Ti-W2O4 and At1
Since the design must be merged to some extent with 05, it is difficult to miniaturize the device.
それに対し１本発明の第３図に示す実施例では。In contrast, in the embodiment shown in FIG. 3 of the present invention.
ｐｔ３ｉ 形成後Ｔｉ膜３０６とＴｉ−Ｗ膜３０４及び
Ａｔ膜１０５’ｅ連続して付着し、フォトレジストをマ
スクとして選択的ＫＴ ｔ ３０６とＴｉ−Ｗ３Ｏ４及
びＡｔ１０５を除去し素子間の配線を形成する。After forming pt3i, Ti film 306, Ti-W film 304, and At film 105'e are successively deposited, and using photoresist as a mask, selectively remove KT t 306, Ti-W3O4, and At105 to form wiring between elements. .
以上の方法で形成された本発明の一実施例では’ｌ’１
−Ｗ３０４と５ｉＯ２１０２の間には両者に対し粘着性
を持つＴｉ３０６が入れられている為。In one embodiment of the present invention formed by the above method, 'l'1
- Because Ti306 is placed between W304 and 5iO2102, which has adhesive properties to both.
ＳｉＯ２と配線との間の剥れを防ぐことができる。Peeling between SiO2 and wiring can be prevented.
本発明の構造では、’ｒｔ−ｗ膜下には、５ｔＯ２と密
着性のよい、Ｔｉ膜が入れられている為、配線が下地５
ｉｏ２から剥れることがなくなシ、信頼件の高い微細配
線が実現できる。従って本発明を集積回路に粗み込むこ
とにより、冒速で高集積の半導体装置を得ることができ
る。In the structure of the present invention, a Ti film with good adhesion to 5tO2 is placed under the 'rt-w film, so that the wiring can be connected to the underlying 5tO2.
There is no peeling from the io2, and highly reliable fine wiring can be realized. Therefore, by applying the present invention to an integrated circuit, a highly integrated semiconductor device can be obtained at an early stage.
第１図及び第２図は従来構造の２つの実施例を示す断面
図で、第３図は本発明の一実施例を示す断面図である。
尚１図中に於いて、１０１・・・・・・シリコン基板。
１０２・・・・・・シリコン酸化膜（ＳｉＯ□）、１０
３・・・・・・口金シリサイド膜（ＰｔＳｉ）、１０４
，２０４，３０４・・・・・・チタン−タングステン合
金膜（Ｔｉ−Ｗ）。
１０５・・・・・・アルミ膜（Ａｔ）、３０６・・・・
・・チタン膜（Ｔｉ）。1 and 2 are sectional views showing two embodiments of conventional structures, and FIG. 3 is a sectional view showing one embodiment of the present invention. In Figure 1, 101...silicon substrate. 102...Silicon oxide film (SiO□), 10
3... Cap silicide film (PtSi), 104
, 204, 304...Titanium-tungsten alloy film (Ti-W). 105... Aluminum film (At), 306...
...Titanium film (Ti).
Claims (1)
ｉ）膜上にチタン（Ｔｉ）とタングステン局の合金膜を
有し、更に該合金膜上にアルミｃｋｔ）膜を有する三層
金属膜を前記回路素子間を接続する配線として用いるこ
とを特徴とする半導体装置。Titanium (T) is used in semiconductor devices including multiple circuit elements.
i) A three-layer metal film having an alloy film of titanium (Ti) and tungsten alloy on the film and further having an aluminum ckt) film on the alloy film is used as a wiring for connecting the circuit elements. semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8457084A JPS60227469A (en) | 1984-04-26 | 1984-04-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8457084A JPS60227469A (en) | 1984-04-26 | 1984-04-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60227469A true JPS60227469A (en) | 1985-11-12 |
Family
ID=13834323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8457084A Pending JPS60227469A (en) | 1984-04-26 | 1984-04-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60227469A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4926237A (en) * | 1988-04-04 | 1990-05-15 | Motorola, Inc. | Device metallization, device and method |
| US5124781A (en) * | 1988-05-06 | 1992-06-23 | Nec Corporation | Semiconductor device having organic film as interlayer insulating film for multilayer wirings |
| US5236852A (en) * | 1992-09-24 | 1993-08-17 | Motorola, Inc. | Method for contacting a semiconductor device |
| JPH06140357A (en) * | 1990-12-11 | 1994-05-20 | Samsung Semiconductor Inc | Method for formation of metal barrier |
| US5719416A (en) * | 1991-12-13 | 1998-02-17 | Symetrix Corporation | Integrated circuit with layered superlattice material compound |
-
1984
- 1984-04-26 JP JP8457084A patent/JPS60227469A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4926237A (en) * | 1988-04-04 | 1990-05-15 | Motorola, Inc. | Device metallization, device and method |
| US5124781A (en) * | 1988-05-06 | 1992-06-23 | Nec Corporation | Semiconductor device having organic film as interlayer insulating film for multilayer wirings |
| JPH06140357A (en) * | 1990-12-11 | 1994-05-20 | Samsung Semiconductor Inc | Method for formation of metal barrier |
| US5719416A (en) * | 1991-12-13 | 1998-02-17 | Symetrix Corporation | Integrated circuit with layered superlattice material compound |
| US5236852A (en) * | 1992-09-24 | 1993-08-17 | Motorola, Inc. | Method for contacting a semiconductor device |
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