JPH03191525A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH03191525A JPH03191525A JP33205389A JP33205389A JPH03191525A JP H03191525 A JPH03191525 A JP H03191525A JP 33205389 A JP33205389 A JP 33205389A JP 33205389 A JP33205389 A JP 33205389A JP H03191525 A JPH03191525 A JP H03191525A
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- high melting
- interlayer insulating
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000010410 layer Substances 0.000 claims abstract description 29
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 26
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000002844 melting Methods 0.000 claims abstract description 24
- 230000008018 melting Effects 0.000 claims abstract description 24
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 21
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000002955 isolation Methods 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野）
本発明は半導体装置及びその製造方法に関し、特に多層
配線を有する半導体装置及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having multilayer wiring and a method for manufacturing the same.
半導体装置の高集積化に伴い電極配線パターンの微細化
が重要となる。従来より配線材料は主にアルミニウムが
用いられており、近年電極配線の微細化が進むにつれア
ルミニウム電極配線に加わる機械的・電気的ストレスに
よるアルミニウムのマイグレーションが装置の信頼性低
下の要因として重要視されてきている。そこでこれらの
現象を抑制する為モリブデンやタングステン等の高融点
金属の硅化物膜とアルミニウム膜の多層膜を配線として
用いる方法がとられている。As semiconductor devices become more highly integrated, miniaturization of electrode wiring patterns becomes important. Conventionally, aluminum has been mainly used as the wiring material, and as electrode wiring has become finer in recent years, aluminum migration due to mechanical and electrical stress applied to aluminum electrode wiring has become important as a factor in reducing device reliability. It's coming. Therefore, in order to suppress these phenomena, a method has been adopted in which a multilayer film of a silicide film of a high melting point metal such as molybdenum or tungsten and an aluminum film is used as the wiring.
第３図（ａ）、（ｂ）は従来の半導体装置の製造方法を
示す工程順に示す配置した半導体チップの縦断面図であ
る。FIGS. 3(a) and 3(b) are vertical cross-sectional views of semiconductor chips arranged in the order of steps showing a conventional method of manufacturing a semiconductor device.
まず第３図（ａ）に示す様に半導体基板１の表面に素子
分離領域としてフィールド絶縁膜２と高濃度不純物拡散
層３及び第１の配線層としてポリシリコン配線層４を形
成し層間絶縁膜５を被着し、第２の配線層と接続するた
めのコンタクト孔を選択的に開孔し、次いでタングステ
ン等の高融点金属シリサイド膜６ａを厚さ１１００ｎ程
度被着する。続いて第３図（ｂ）に示す様にアルミニウ
ム膜７を１μｍ程度被着し、フォトリソグラフィ法を用
いてアルミニウム膜電極及び高融点金属シリサイド膜を
同時にバターニングする。さらに図は省略するがこの素
子表面にパッシベーション膜を被着して装置を完成させ
る。First, as shown in FIG. 3(a), a field insulating film 2 and a high concentration impurity diffusion layer 3 as an element isolation region and a polysilicon wiring layer 4 as a first wiring layer are formed on the surface of a semiconductor substrate 1, and an interlayer insulating film is formed. A contact hole for connecting to the second wiring layer is selectively formed, and then a high melting point metal silicide film 6a such as tungsten is deposited to a thickness of about 1100 nm. Subsequently, as shown in FIG. 3(b), an aluminum film 7 of about 1 μm is deposited, and the aluminum film electrode and the refractory metal silicide film are simultaneously patterned using photolithography. Further, although not shown in the drawings, a passivation film is coated on the surface of this element to complete the device.
」二連した従来の半導体装置は、下層配線層であるポリ
シリコン配線層や高濃度不純物拡散層のアルミニウム膜
とのコンタクト部に高融点金属シリサイド膜が存在する
ためコンタクトの接触抵抗が高くなり、素子の高速性を
そこなうという欠点がある。In the conventional double-connected semiconductor device, the contact resistance of the contact is high because a high melting point metal silicide film is present in the contact area with the polysilicon wiring layer, which is the lower wiring layer, and the aluminum film of the high concentration impurity diffusion layer. This has the disadvantage of impairing the high speed performance of the device.
本発明の半導体装置は、半導体素子領域を有する半導体
基板の前記半導体素子領域を含む表面に設けた層間絶縁
膜と、前記半導体素子領域及び配線層上の前記層間絶縁
膜に設けた開口部と、前記開口部を除いて前記層間絶縁
膜上に形成した高融点金属シリサイド膜及び前記開口部
の前記半導体素子領域及び配線層に接続して前記高融点
金属シリサイド膜上に形成したアルミニウムを含む金属
膜からなる２層構造の電極配線とを有している。The semiconductor device of the present invention includes: an interlayer insulating film provided on a surface including the semiconductor element region of a semiconductor substrate having a semiconductor element region; an opening provided in the interlayer insulating film over the semiconductor element region and the wiring layer; A high melting point metal silicide film formed on the interlayer insulating film except for the opening, and a metal film containing aluminum formed on the high melting point metal silicide film connected to the semiconductor element region and wiring layer in the opening. It has a two-layer structure of electrode wiring.
又、本発明の半導体装置の製造方法は、半導体素子領域
を有する半導体基板の前記半導体素子領域を含む表面に
層間絶縁膜を被着する工程と、前記層間絶縁膜上に高融
点金属シリサイド膜を被着する工程と、前記高融点金属
シリサイド膜及び前記層間絶縁膜を順次選択的に除去し
前記半導体素子領域上に開孔部を設ける工程と、アルミ
ニウムを含む金属膜を被着する工程とを含むというもの
である。The method for manufacturing a semiconductor device of the present invention also includes the steps of: depositing an interlayer insulating film on a surface including the semiconductor element region of a semiconductor substrate having a semiconductor element region; and depositing a high melting point metal silicide film on the interlayer insulating film. a step of depositing a metal film containing aluminum, a step of sequentially selectively removing the high melting point metal silicide film and the interlayer insulating film to provide an opening over the semiconductor element region, and a step of depositing a metal film containing aluminum. Including.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明半導体装置の一実施例を示す半導体チッ
プの断面図である。FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the semiconductor device of the present invention.
この実施例はフィールド絶縁膜２で区画された半導体素
子領域を有する半導体基板（シリコン）の前述の素子領
域を含む表面に設けた層間絶縁膜５と、前述の半導体素
子領域上の層間絶縁Ｍ５に設けた開口部９と、開口部９
を除いて層間絶縁膜５上に形成した高融点金属シリサイ
ド膜及び開口部９の前述の半導体素子領域に接続して高
融点金属シリサイドＭ６ｂ上に形成したアルミニウム膜
７からなる２層構造の電極配線とを有するというもので
ある。This embodiment includes an interlayer insulating film 5 provided on the surface including the aforementioned element region of a semiconductor substrate (silicon) having a semiconductor element region partitioned by a field insulating film 2, and an interlayer insulating film M5 on the aforementioned semiconductor element region. The opening 9 provided and the opening 9
The electrode wiring has a two-layer structure consisting of a high melting point metal silicide film formed on the interlayer insulating film 5 except for , and an aluminum film 7 formed on the high melting point metal silicide M6b connected to the above-mentioned semiconductor element region of the opening 9. It is said that it has.
第２図（ａ）、（ｂ）は本発明半導体装置の製造方法の
一実施例を説明するため工程順に示す半導体チップの縦
断面図である。FIGS. 2(a) and 2(b) are longitudinal cross-sectional views of a semiconductor chip shown in order of steps to explain an embodiment of the method for manufacturing a semiconductor device of the present invention.
Ｊず第２図（ａ）に示す様に半導体基板ｌの表面に素子
分離のためにフィールド絶縁膜２を形成し次いで第１の
配線層としてポリシリコン配線層４を形成し、高濃度不
純物拡散層領域３をイオン注入法等を用いて形成する。As shown in FIG. 2(a), a field insulating film 2 is formed on the surface of a semiconductor substrate 1 for element isolation, and then a polysilicon wiring layer 4 is formed as a first wiring layer, and a high concentration impurity is diffused. Layer region 3 is formed using an ion implantation method or the like.
次に半導体基板表面に二酸化シリコン膜やリンガラス膜
（ＰＳＧ膜）等を層間絶縁膜５として被着し、続いてタ
ングステンシリサイド等を１１００ｎ程度被着し、高融
点金属シリサイド膜６ｂを形成する。Next, a silicon dioxide film, a phosphorus glass film (PSG film), or the like is deposited on the surface of the semiconductor substrate as an interlayer insulating film 5, and then about 1100 nm of tungsten silicide or the like is deposited to form a high melting point metal silicide film 6b.
次に第２図（ｂ）に示す様にフォトリングラフィにより
上部配線層と接続するためのコンタクト開口をまず高融
点金属シリサイド膜６ｂを選択的に除去し、次いで層間
絶縁膜５を除去して開口を設ける。次に、第１図に示す
ように、上部配線層としてアルミニウム膜７を１μｍ程
度被着し、選択的にアルミニウム膜、高融点金属シリサ
イド膜を順次エツチングして電極配線を形成する。Next, as shown in FIG. 2(b), a contact opening for connecting to the upper wiring layer is created by first selectively removing the high melting point metal silicide film 6b, and then removing the interlayer insulating film 5. Provide an opening. Next, as shown in FIG. 1, an aluminum film 7 of about 1 .mu.m thick is deposited as an upper wiring layer, and the aluminum film and high melting point metal silicide film are selectively etched in sequence to form electrode wiring.
このようにして、コンタクト開口部においてのみ高融点
シリサイド膜を除去した２層構造の電極配線を形成でき
、コンタクトの接触抵抗を下げることが可能となる。In this way, it is possible to form a two-layer electrode wiring structure in which the high melting point silicide film is removed only in the contact opening, and it is possible to lower the contact resistance of the contact.
なお、アルミニウム膜の代わりにアルミニウムを主成分
とする金属膜を使用してもよいのはいうまでもない。Note that it goes without saying that a metal film containing aluminum as a main component may be used instead of the aluminum film.
以上説明したように本発明は、高融点シリサイド膜とア
ルミニウムを含む金属膜の２層構造の電極配線を有する
半導体装置において、コンタクト開口部の高融点金属シ
リサイド膜が選択的に除去されているため前述の金属膜
と下層の高濃度不純物拡散層や配線層とのコンタクト抵
抗を従来より下げる事ができかつストレスマイグレーシ
ョンに対し充分な強度を持つ電極配線を有する半導体装
置を提供できる効果がある。As explained above, the present invention provides a semiconductor device having an electrode wiring having a two-layer structure of a high melting point silicide film and a metal film containing aluminum, in which the high melting point metal silicide film in the contact opening is selectively removed. The contact resistance between the aforementioned metal film and the underlying high-concentration impurity diffusion layer or wiring layer can be lowered compared to the conventional one, and there is an effect that it is possible to provide a semiconductor device having an electrode wiring having sufficient strength against stress migration.
第１図は本発明の半導体装置の一実施例を示す半導体チ
ップの縦断面図、第２図（ａ）、（ｂ）は本発明半導体
装置の製造方法の一実施例を示す工程順に配置した半導
体チップの縦断面図、第３図（ａ）、（ｂ）は従来例を
説明するための工程順に示す半導体チップの縦断面図で
ある。
１・・・半導体基板、２・・・フィールド絶縁膜、３・
・・高濃度不純物拡散層、４・・・ポリシリコン配線層
、５・・・層間絶縁膜、６ａ、６ｂ・・・高融点金属シ
リサイド膜、７・・・アルミニウム膜、８・・・フォト
レジスト膜、９・・・コンタクト開口。FIG. 1 is a vertical cross-sectional view of a semiconductor chip showing an embodiment of the semiconductor device of the present invention, and FIGS. 2(a) and 2(b) are arranged in the order of steps showing an embodiment of the method of manufacturing the semiconductor device of the present invention. 3(a) and 3(b) are longitudinal sectional views of a semiconductor chip shown in the order of steps for explaining a conventional example. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Field insulating film, 3...
...High concentration impurity diffusion layer, 4...Polysilicon wiring layer, 5...Interlayer insulating film, 6a, 6b...High melting point metal silicide film, 7...Aluminum film, 8...Photoresist Membrane, 9... contact opening.
Claims (1)
子領域を含む表面に設けた層間絶縁膜と、前記半導体素
子領域上の前記層間絶縁膜に設けた開口部と、前記開口
部を除いて前記層間絶縁膜上に形成した高融点金属シリ
サイド膜及び前記開口部の前記半導体素子領域に接続し
て前記高融点金属シリサイド膜上に形成したアルミニウ
ムを含む金属膜からなる２層構造の電極配線とを有する
ことを特徴とする半導体装置。 ２、半導体素子領域を有する半導体基板の前記半導体素
子領域を含む表面に層間絶縁膜を被着する工程と、前記
層間絶縁膜上に高融点金属シリサイド膜を被着する工程
と、前記高融点金属シリサイド膜及び前記層間絶縁膜を
順次選択的に除去し前記半導体素子領域上に開孔部を設
ける工程と、アルミニウムを含む金属膜を被着する工程
とを含むことを特徴とする半導体装置の製造方法。[Scope of Claims] 1. An interlayer insulating film provided on a surface including the semiconductor element region of a semiconductor substrate having a semiconductor element region, an opening provided in the interlayer insulating film over the semiconductor element region, and the opening A two-layer structure consisting of a high melting point metal silicide film formed on the interlayer insulating film except for a portion thereof, and a metal film containing aluminum connected to the semiconductor element region of the opening and formed on the high melting point metal silicide film. 1. A semiconductor device comprising: electrode wiring. 2. A step of depositing an interlayer insulating film on a surface including the semiconductor element region of a semiconductor substrate having a semiconductor element region; a step of depositing a high melting point metal silicide film on the interlayer insulating film; Manufacturing a semiconductor device comprising the steps of: sequentially and selectively removing a silicide film and the interlayer insulating film to provide an opening over the semiconductor element region; and depositing a metal film containing aluminum. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33205389A JPH03191525A (en) | 1989-12-20 | 1989-12-20 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33205389A JPH03191525A (en) | 1989-12-20 | 1989-12-20 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03191525A true JPH03191525A (en) | 1991-08-21 |
Family
ID=18250616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33205389A Pending JPH03191525A (en) | 1989-12-20 | 1989-12-20 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03191525A (en) |
-
1989
- 1989-12-20 JP JP33205389A patent/JPH03191525A/en active Pending
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