JPS62104138A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce connecting resistance and to reduce electrode or wiring resistance, by selectively removing a metal silicide layer on a lower wiring layer in a polycide structure, and directly connecting an upper polycrystal silicon layer to a lower polycrystalline silicon layer. CONSTITUTION:Only a metal silicide layer 5 on a lower wiring layer 3 is etched by way of a through hole 7 by a selective etching method. A lower polycrystalline silicon layer 4 is exposed in the through hole 7. Then, a polycrystalline silicon layer 9 and a metal silicide layer 10 are sequentially formed. A required pattern is formed by a photoetching method, and an upper wiring layer 8 is formed. At the connecting part of the lower wiring layer 3 and the upper wiring layer 8, the polycrystalline silicon layer 9 beneath the upper wiring layer 8 is directly connected to the polycrystalline silicon layer 4 beneath the lower wiring layer 3. Therefor,e a potential barriers is not yielded between both layers, and the connections having low junction resistance are obtained. The contact area of both wiring layers 3 and 8 can be increased, and the connecting resistance can be also decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which electrodes and interconnections of a polycide structure are formed in multiple layers.

[Conventional technology]

In recent years, with the demand for higher integration and faster operation of semiconductor devices, a so-called polycide structure, in which a polycrystalline silicon layer and a metal silicide layer are laminated, has been adopted for various electrodes and wiring, including gate electrodes. At the same time, multilayer wiring in which wiring is arranged vertically is being promoted. For example, the third
As shown in the figure, a lower wiring layer 13 of a polycide structure consisting of a polycrystalline silicon layer 14 and a metal silicide layer 15 is extended on an insulating film 12 on the surface of a semiconductor substrate 11, and is covered with an interlayer insulating film 16. Then, a through hole 17 is formed here, and an upper wiring layer 1 consisting of a polycrystalline silicon layer 19 and a metal silicide layer 20 extended on the interlayer insulating film 16 is formed.
8 through this through hole 17 to the lower wiring layer 13.
are connected to form a multilayer wiring structure.

[Problem that the invention seeks to solve]

In the semiconductor device having the conventional multilayer wiring structure described above,
When both the lower wiring layer 13 and the upper wiring layer 18 have a polycide structure, the connection between them at the through hole 17 is between the metal silicide layer 15 of the lower wiring layer 13 and the polycrystalline silicon layer of the upper wiring layer 18. It becomes a junction with 19. Therefore, a potential barrier may occur between the metal silicide layer 15 and the polycrystalline silicon layer 19 at this junction, resulting in high junction resistance.

Further, in the above configuration, the lower wiring layer 13 and the upper wiring layer 18
Since the contact area where these are connected is limited to the opening area of the through hole 17, the contact area also decreases as the diameter of the through hole 17 decreases, and there is also the problem that connection resistance increases as semiconductor devices become smaller. be.

[Means for solving problems]

The semiconductor device of the present invention aims to reduce the connection resistance between the lower wiring layer and the upper wiring layer while increasing the degree of integration of the semiconductor device, and has a polycide structure with a polycrystalline silicon layer and a metal silicide layer. A metal silicide layer provided above the lower wiring layer in a multilayer wiring structure that has a formed lower wiring layer and an upper wiring layer comprising at least a polycrystalline silicon layer, and connects both wiring layers in the vertical direction. selectively remove
The exposed lower polycrystalline silicon layer is directly connected to the upper wiring layer polycrystalline silicon layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a cross-sectional view of one embodiment of the present invention, and in particular is a diagram selectively showing a portion of the wiring structure.

As shown in the figure, an insulating film 2 such as a silicon oxide film is formed on the surface of a semiconductor substrate 1 made of silicon or the like, and a lower wiring layer 3 is formed thereon in a desired pattern. This lower wiring layer 3
has a polycide structure, consisting of a lower polycrystalline silicon layer 4 and a lower metal silicide layer 5 laminated thereon. As the metal silicide layer 5,
A high melting point metal silicide layer such as a titanium silicide layer, a tungsten silicide layer or a molybdenum silicide layer is preferred. This lower wiring layer 3 is covered with an interlayer insulating film 6 made of a CVD silicon oxide film, and through holes 7 are formed at predetermined locations in the interlayer insulating film 6. Further, on this interlayer insulating film 6, an upper wiring layer 8 is formed in a desired pattern. This upper wiring layer 8 also has a polycide structure here, and is composed of a lower polycrystalline silicon layer 9 and an upper metal silicide layer IO. The metal silicide N10 is made of high-melting point metal silicide like the metal silicide layer of the lower wiring layer 3.

The lower wiring layer 3 and the upper wiring layer 8 are connected to each other through the through hole 7, and at this connection point, the metal silicide layer 5 provided on the upper layer of the lower wiring layer 3 is selectively connected. to remove the lower polycrystalline silicon layer 4.
is exposed, and the polycrystalline silicon N9 in the lower layer of the upper wiring layer 8 is directly connected thereto.

The manufacturing method for the wiring structure with this configuration is shown in Figs. 2(a) to (c).
Explain using.

First, as shown in FIG.
A polycrystalline silicon layer 4 and metal silicide N5 are sequentially formed thereon, and a desired pattern is formed by photoetching to form the lower wiring layer 3. Then, a CVD silicon oxide film is grown on this to form an interlayer insulating film 6, and through holes 7 are opened at required locations by selective etching.

Next, as shown in FIG. 6B, only the upper metal silicide layer 5 of the lower wiring layer 3 is etched through the through hole 7, and the lower polycrystalline silicon layer 4 is etched through the through hole 7.
Reveal within.

Thereafter, as shown in FIG. 3C, a polycrystalline silicon layer 9 and a metal silicide layer 10 are sequentially formed, and a desired pattern is formed by photo-etching, thereby forming an upper wiring N8. As a result, the semiconductor device shown in FIG. 1 is completed.

Note that when forming the lower wiring layer 3 and the upper wiring layer 8, a method may be used in which a metal layer is formed on the polycrystalline silicon layer 4.9, and this is heat-treated to silicide the metal layer. You can also do it.

According to this configuration, at the connection portion between the lower wiring layer 3 and the upper wiring layer 8, the lower polycrystalline silicon layer 4 of the lower wiring layer 3 directly contacts the lower polycrystalline silicon layer 4 of the upper wiring layer 8. Since they are connected, no potential barrier is generated between them, and a connection with low junction resistance can be obtained. Further, since the upper wiring layer 8 is connected after etching and removing the upper metal silicide layer 5 of the lower wiring layer 3, the rewiring layer 3.8 is at least as thick as the metal silicide layer 5.
The contact area can be increased and the connection resistance can be reduced.

Thereby, the connection resistance between the upper wiring layer 3 and the lower wiring layer 8 can be reduced, the resistance of the electrodes or wiring of the semiconductor device can be lowered, and the operation speed of the semiconductor device can be increased.

Note that in the present invention, if the lower wiring layer has a polycide structure,
The same applies even if the upper wiring layer is simply a polycrystalline silicon layer.

〔Effect of the invention〕

As explained above, the present invention selectively removes the metal silicide layer provided on the lower wiring layer formed in a polycide structure by a polycrystalline silicon layer and a metal silicide layer, and removes the exposed lower layer of polycrystalline silicon. Since the polycrystalline silicon layer of the upper wiring layer is directly connected to the silicon layer, the potential barrier between the upper and lower wiring layers is suppressed, and the contact area is increased to reduce the connection resistance between the two. Therefore, it is possible to construct a multilayer wiring structure with low electrode or wiring resistance.

[Brief explanation of drawings]

FIG. 1 is a sectional view of one embodiment of the semiconductor device of the present invention, and FIG.
Figures (a) to (C) are cross-sectional views showing the manufacturing method in order of steps, and Fig. 3 is a cross-sectional view of a conventional structure. 1.11... Semiconductor substrate, 2.12... Insulating film, 3
゜13...Lower wiring layer, 4.14...Polycrystalline silicon layer, 5.15...Metal silicide layer, 6,16...
・Interlayer insulating film, 7, 17...Through hole, 8.18
... Upper wiring layer, 9, 19... Polycrystalline silicon layer,
10,20...Metal silicide layer.

Claims (1)

[Claims] 1. A lower wiring layer formed in a polycide structure with a lower polycrystalline silicon layer and an upper metal silicide layer, and an upper wiring layer having at least a polycrystalline silicon layer, and both wirings A semiconductor device having a multilayer wiring structure in which layers are vertically connected through through holes provided in an interlayer insulating film, wherein a metal silicide layer provided on an upper layer of a lower wiring layer is selectively removed in the through hole. A semiconductor device characterized in that a polycrystalline silicon layer of an upper wiring layer is directly connected to the exposed polycrystalline silicon layer. 2. Claim 1 in which the upper wiring layer has a polycide structure consisting of a polycrystalline silicon layer and a metal silicide layer.
1. Semiconductor device described in Section 1.