JPS59155148A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce fraction defective by forming a conductor layer pattern, size thereof is larger than a contact hole and which has selective etching capability to first and second wiring layers, to the contact hole section for connecting said wiring layers. CONSTITUTION:A field oxide film 12 is formed on the surface of a semiconductor substrate 11, an element is formed in an element region surrounded by the oxide film 12, and an Al film is evaporated on the whole surface and patterned to form a first wiring layer 13. A CVD oxide film 14 is deposited on the whole surface. A contact hole 15 is bored to the oxide film 14, and an impurity doped polycrystalline silicon film is deposited on the whole surface and patterned to form a polycrystalline silicon film pattern 16 connected to the first wiring layer 13 through the contact hole 15. Al is evaporated, and a second wiring layer 17 connnected to the pattern 16 is formed. The size of the pattern 16 is larger than that of the contact hole 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for connecting wiring in a semiconductor device having a multilayer wiring structure.

[Technical background of the invention and its problems]

A conventional method for manufacturing a semiconductor device with a multilayer wiring structure is shown in Figure 1 (
This will be explained with reference to a) and (b).

First, a field oxide film 2 is formed on the surface of a semiconductor substrate 1, and an element is formed in an element region (not shown) surrounded by this field oxide film 2. After that, a film K, for example, a U film, is deposited on the entire surface and patterned to form a first film. A wiring layer 3 is formed. next,
After depositing, for example, a CVD oxide film 4 over the entire surface, a contact hole 5 is opened. Subsequently, after depositing, for example, Atm on the entire surface, patterning is performed to form the contact hole 5.
a second wiring layer 6 connected to the first wiring layer 3 via
form.

Note that when attempting to manufacture a semiconductor device with a multilayer wiring structure using the above-described method, after the contact hole 5 is opened and before the second wiring layer 6 is formed, the first layer made of At is removed due to the influence of an etchant or the like. At20. which is formed by oxidizing the surface of the wiring layer 3. There is a risk that other unexpected compounds may remain and the contact resistance between the first wiring layer 3 and the second wiring layer 6 may increase.
) to (c) have also been adopted.

First, a first wiring layer 3 made of At, for example, is formed on the field oxide film 2 on the surface of the semiconductor substrate 1, and then, for example, a single crystal or polycrystalline silicon film or a metal silicide film is deposited on the entire surface, and then patterned and oxidized. A protective film pattern 7 is then formed. Next, a CVD oxide film 4, for example, is deposited on the entire surface (as shown in FIG. 2(a)).

Next, a contact hole 5 is formed by selectively etching a portion of the CVD oxide film 4 and a portion of the film-retaining film pattern 7 (as shown in FIG. 2B). At this time, since the surface ν of the contact portion of the first wiring layer 3 was covered with the protective film pattern 7, if the protective film pattern 7 was etched, unexpected compounds would remain on the first wiring layer 3. 0 Subsequently, after depositing, for example, an At film on the entire surface, it is patterned to form a second wiring layer 6 that connects to the wiring layer 3 of the ls1 (as shown in FIG. 3(C)). The protective film pattern 7 may be made of an insulating film.

By the way, in both of the above-mentioned two manufacturing methods, defects may occur during the formation of the first wiring layer 3, such as defects in the covering condition (step cottage) during M vapor deposition or cutting of the wiring layer during patterning. If contact between adjacent wiring layers (hereinafter referred to as an open defect) or contact between adjacent wiring layers (hereinafter referred to as a short defect) occurs, the first wiring layer 13 is dissolved in a mixture of hydrochloric acid, hydrogen peroxide, and water. After that, the M film is often deposited and patterned again.

However, when various defects as described above occur in the second wiring layer 6, when trying to dissolve the second wiring layer 6 in order to re-form the second wiring layer 6, the problem shown in FIG. As such, the underlying first wiring layer 3 is also dissolved at the same time, making it impossible to reproduce the pattern of the first wiring layer 3. Therefore, such re-formation of the second wiring layer 6 cannot be performed, which causes a high defect rate.

Therefore, in order to prevent oven defects and short-circuit defects in the second wiring layer 6 and to reduce the defective rate, the width of the second wiring layer 60 shown in FIG. width,
Countermeasures have been taken to increase the area and also increase the distance between adjacent second wiring layers 6, but this is not effective in reducing the defective rate in the current situation where device miniaturization is progressing. do not have.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is possible to re-form the second wiring layer when a defect occurs in the second wiring layer, thereby reducing the defective rate and increasing the yield. The present invention aims to provide a method for manufacturing a semiconductor device that can improve the performance of semiconductor devices.

[Summary of the invention]

In the method for manufacturing a semiconductor device according to the present invention, a contact hole portion for connecting a first wiring layer and a second wiring layer is larger in size than the contact hole, and is connected to the first wiring layer and the second wiring layer. The main idea is to form a conductor layer pattern that has selective etching properties.

By forming a conductor layer pattern that is larger in size than the contact hole and has selective etching properties for the first and second wiring layers, it is possible to re-form even if a defect occurs in the second wiring layer. can reduce the defective rate.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described with reference to FIGS. 4(a) and 4(b), FIGS. 5 and 6.

First, a field oxide film 12 is formed on the surface of the semiconductor substrate 11, and an element is formed in an element region (not shown) surrounded by this field oxide film 12. After that, an M film is deposited on the entire surface and patterned to form a first wiring. Layer 13 was formed. Next, a CVD oxide film 14 was deposited on the entire surface (as shown in FIG. 4(a)).Continuously, after opening a contact hole 15 in the CVD oxide film 14, an impurity-doped polycrystalline silicon film was deposited on the entire surface. , patterning the contact hole 1
A polycrystalline silicon film pattern 16 was formed to be connected to the first wiring layer 13 via a polycrystalline silicon film pattern 16. As shown in FIG. 5, this polycrystalline silicon film pattern 16 has a length W of each side,
is the length W of each side of the contact hole 15.

, and larger in size than the contact hole 15. Subsequently, after depositing an A/= film on the entire surface, it was patterned to form a second wiring layer 17 connected to the polycrystalline silicon film pattern 16, and a semiconductor device with a multilayer wiring structure was manufactured. Figure (b) shown).

According to the above method, selective etching is performed between the first wiring layer 13 made of M and the second wiring layer 12 made of M in the step shown in FIG. 4(b). Since a polycrystalline silicon film pattern 16 with a larger size than the contact hole 15 is formed, if a defect occurs in the second wiring layer 17, the polycrystalline silicon film pattern 16 is removed as shown in FIG. 16 acts as a barrier against etching, and only the second wiring layer 17 can be dissolved and removed without dissolving the first wiring layer 13. Therefore, by re-forming the second wiring layer 17, edge defects can be eliminated, the defective rate can be significantly reduced, and the yield can be improved.

Note that the method of FIG. 7(&) is not limited to the method of the above embodiment.

As shown in FIG. 4B, after forming the first wiring layer 13 in a step corresponding to the step in FIG. 4A, a polycrystalline silicon film pattern 18 is formed on the first wiring layer 13. Next, a contact hole 15 smaller in size than the polycrystalline silicon film notch 18 is formed, and a second wiring layer 1 is formed.
7 may also be used.

Even with this method, as shown in FIG. 8, even if a defect occurs in the second wiring layer 17, only the second wiring layer 17 is dissolved;
Can be reshaped.

Further, the first and second wiring layers 13.17 are not limited to M used in the first embodiment, but may be an aluminum alloy such as aluminum silicon, and they may be the same or different. The conductive layer pattern formed between the layers is not limited to the polycrystalline silicon used in the above embodiments, but may also be metals other than aluminum such as platinum, molybdenum, and tungsten, or alloys other than aluminum alloys such as molybdenum silicide. It is desirable that it has good adhesion to the first and second wiring layers and has low resistance.

Furthermore, in the above embodiments, the explanation was made regarding the connection between the first and second wiring layers on a semiconductor substrate, but the method of the present invention can be similarly applied to connections between each wiring layer in a semiconductor device having three or more wiring layers. Of course it can be done.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device that can significantly reduce defects in wiring layers and improve yield.

[Brief explanation of drawings]

FIG. 1(a) is a plan view of a conventional semiconductor device with a multilayer wiring structure, and FIG. 1(b) is a cross-sectional view taken along line B-B in FIG. 1(a).
FIGS. 2(a) to (C) are cross-sectional views showing another conventional method for manufacturing a semiconductor device with a multilayer wiring structure, and FIG. 3 is a cross-sectional view showing a state in which the second wiring layer is melted in the conventional semiconductor device. 4(a) and 4(b) are cross-sectional views showing a method for manufacturing a semiconductor device having a multilayer wiring structure in an embodiment of the present invention.
The figure is a plan view of the semiconductor device, FIG. 6 is a cross-sectional view showing the state in which the second wiring layer of the semiconductor device is dissolved, and FIG. 7(a)
8 is a plan view of a semiconductor device manufactured by a method according to another embodiment of the present invention, FIG. 8B is a sectional view taken along line B-B in FIG. FIG. 3 is a cross-sectional view showing a state in which the second wiring layer of FIG. 11... Semiconductor substrate, 12... Field oxide film 1
3... First wiring layer, 14... CVD oxide film, 15
. . . Contact hole, 16. 18 . . . Polycrystalline silicon film pattern, 17 . . . Second wiring layer. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (3)

[Claims] (1) A step of forming a first wiring layer via a first insulating film on a semiconductor substrate on which an element is formed, depositing a second insulating film on the entire surface, opening a contact hole, and The contact hole area has a large contact hole area,
forming a conductor layer pattern having selective etching properties with respect to the first wiring layer and a second wiring layer to be described later; 1. A method for manufacturing a semiconductor device, comprising the step of forming a wiring layer. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the first and second wiring layers are made of the same or different wiring materials. (3) The first and second wiring layers are made of aluminum or an aluminum alloy, and the conductor layer pattern is made of polycrystalline silicon, a metal other than aluminum, or a metal silicide other than aluminum alloy. A method for manufacturing a semiconductor device according to item 1 or 2.