JP2653672B2 - Method of forming scalable fuse link device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates generally to integrated circuit fuse links, and more particularly to improved fuse links and fuses compatible with both wet and dry etching. And a method for forming the same.

Prior Art Fuse links have been used for years in digital integrated circuits, especially in programmable fixed (read-only) storage (PROM) and programmable logic arrays (PAL). The fuse links are used to connect a matrix of circuit elements for custom applications or permanent data storage by selectively cutting undesirable fuse links. Hughes Link
Disconnection is achieved by various techniques, such as by selectively applying a sufficiently large current through the undesirable link.

As with many other semiconductor products, the increase in device integration on a single chip is rapidly obsoleting the process technology used to fabricate fuse link devices. Dry plasma etching
Wet wet to provide increased levels of integration
Increasingly replacing chemical etching. While dry plasma etching allows for smaller device widths and pitches, overetching can adversely affect sensitive components on the surface of the substrate. It is therefore important to minimize the interaction between dry etching and surface features as much as possible.

Scalability is also an important criterion in semiconductor processing. A process that can be easily applied to smaller components is one that has a high degree of scalability. Previously developed methods of forming fuse links are not applicable to highly integrated circuits where the width of the interconnect leads and the spacing between the interconnect leads are substantially reduced.

In addition, prices of semiconductor products have been reduced to remain competitive. Therefore, it is important that semiconductor products be as efficient as possible. The price of a semiconductor device largely depends on the number of masking levels used when manufacturing the device. Therefore, the masking level, and
It is desirable to reduce the associated fine alignment tolerances required during masking. Previously developed techniques for fabricating fuse links have provided difficulties in reducing the number of masking levels and reducing alignment tolerances.

Therefore, what is needed in the fuse link process is to minimize over-etching of sensitive layers on the substrate surface, the number of masking levels and associated fine alignment tolerances required during masking, and The goal is to provide a high degree of scalability using as much of the dry process as possible.

SUMMARY OF THE INVENTION The present invention disclosed herein provides a fuse link between two interconnecting leads and a fuse link that substantially eliminates the problems associated with conventional methods of forming a fuse link. A method for forming a link will be described. In one aspect of the invention, a method of forming a fuse link between two interconnects includes forming an insulating mask over a thin metallization layer. The insulating mask is formed in the form of a fuse link of a preferred size. A thick metallization layer and a thick conductive layer are formed over the thin metallization layer and the isolation mask. A photoresist mask defining the shape of the interconnect is formed on the surface of the conductive layer. Etching of the original place (insitu)
Applied over the conductive layer, the thick metallization layer, and the thin metallization layer to provide an interconnect having a barrier region consisting of the thick metallization layer. Portions of the thin metallization layer that are not covered by the first mask or photoresist mask are removed during the in-situ etching, leaving fuse links connecting the two interconnects.

The technical advantages provided by the present invention are that damage from dry etching and over-etching of sensitive components on the substrate surface are minimized and the number of masking levels required to form a fuse link is reduced. Decreased,
It is an object of the present invention to provide a process adapted to the reduction of the line width of the component.

Embodiment The application of the preferred embodiment of the present invention is best understood by referring to the drawings of FIGS.
In the drawings, the same numbers are used for the same and similar parts in the drawings.

Reference is made to the drawings of FIGS. 1a to 1b, which show a conventionally developed method of forming a fuse link. A doped isolation oxide layer 10 is formed over a substrate 12 having an active device. Isolation oxide layer 10
Patterned and etched to expose the exposed contact pads 14 on the substrate 12 over the active device 15.
To form A barrier layer 16 is formed over the contact pads 14, but by forming a thick metallization layer over the isolation oxide 10 and the contact pads 14, and then patterning and etching the metallization layer. The barrier layer 16 is formed.

A thin metallization layer 18 is formed over barrier layer 16 and isolation oxide 10. A thick conductive layer is formed over the thin metallization layer 18, then patterned and etched to form interconnects 20 and 22. After forming interconnects 20 and 22, a photoresist pattern 24 is applied to the interconnect and thin metallization layer 18. Portions of the thin metallization layer 18 that are not covered by the photoresist pattern 24, neither the interconnects 20 and 22, are etched away, exposing the isolation oxide layer 10. The portion of the thin metallization 18 remaining under the photoresist pattern 24 forms the fuse link 26. The photoresist pattern 24 is removed after etching.

The barrier layer 16 is necessary to provide electrical conductivity between the substrate and the interconnects 20 and 22 while preventing the silicon substrate from reacting to the aluminum used for the interconnects 20 and 22. Is because aluminum can react undesirably with silicon. This barrier layer must be of substantial thickness in the range of 1200 Angstroms to 200 Angstroms to provide sufficient barrier between substrate 12 and interconnects 20 and 22.

There are several disadvantages associated with previously developed processes for forming fuse links. One problem with previously developed manufacturing methods is that they are incompatible with the dry etching technology steps required to fabricate small linewidth interconnects. Due to the large undercut characteristics of wet etching, wet etching should no longer be used once the line width 27a or pitch 27b of interconnects 20 and 22 has been reduced to increase the integration of semiconductor devices. Can not. Wet etching has an undercut characteristic of about 1 micron per side. For interconnects having a relatively large line width, for example, a line width of 7 microns, the interconnect can be oversized, providing a reduction of 1 micron per side. However, when the line width 27a of the interconnects 20 and 22 and the spacing between the interconnects are reduced, the undercut characteristics are not controlled precisely enough to produce consistent results. Therefore, for line widths of 3 microns or less, dry etching must be used.

Therefore, it is preferable to use a dry etching technique for a highly integrated device. However, when dry etching interacts with the substrate 12 and dry etching,
Doping impurities are removed from the surface of the isolation oxide layer 10. After the completion of the etching step, the doping impurities are needed to prevent surface inversion,
10 It is important that a sufficient amount of doping impurities remain. In the previously developed manufacturing method described above,
The isolation oxide layer 10 is etched twice, once in the etching of the barrier layer 16 and again when etching the fuse link 26 from the thin metallization layer 18.

Other issues associated with traditionally developed recipes include:
The complexity of forming the photoresist pattern 24, which is used to cover the fuse link 26 during the etching of the thin metallization layer 18. Interconnects 20 and 22 are made of thin metallized layer 18
Interconnects 20 and
A photoresist pattern 24 must be formed on the steps formed by 22. This problem can be alleviated somewhat by using a "slanting etch" that creates sloping edges on interconnects 20 and 22,
Precisely forming a photoresist pattern on sloping edges is much less reliable than forming a photoresist pattern on a flat surface. Furthermore,
Reducing the width of the valleys between interconnects can reduce photoresist and
Adding within that valley of the pattern 24 becomes increasingly difficult, and thus the scalability of the process is also reduced.

A third problem with previously developed manufacturing methods is the number of masks required to complete the process. Traditionally developed processes include a first mask for the barrier layer, an interconnect 20
2 and a third mask for forming the fuse link 26 are used.
Generally, the complexity of the process is based on the number of masks used, so it is desirable to reduce the masks as much as possible. Furthermore, the elimination of the masking level significantly reduces the degree of misalignment.

Referring now to FIGS. 2a through 2b, which show the first stage of the manufacturing method used in the present invention. In a first process step, a doped isolation oxide layer 28 is formed on a substrate 30. In a preferred embodiment, this isolation oxide layer 28
Is thermally grown and doped with phosphorus doping impurities. Generally, the thickness of the isolation oxide ranges from 2500 Angstroms to 3000 Angstroms, with a preferred value of about 2800 Angstroms. The purpose of the isolation oxide layer 28 is to separate the conductive elements connecting the active devices from the substrate 30
To prevent surface inversion.

In a second process step, isolation oxide layer 28 is patterned and etched to provide contact region 32 over active device 31. The isolation oxide 28 can be etched using a common oxide etch (COE) for wet etching and a fluorinated plasma for dry etching.

In a third stage of the first stage, a thin metallization layer 34 is formed over the isolation oxide layer 28 and the contact region 32.
The thin metallization layer 34 is between 400 Å and 500 Å thick. This thin metallization layer will be used at a later stage to form a fuse link. Preferably, this thin metallization layer 34 is formed of a titanium-tungsten material (hereinafter "Ti: W"). But,
Other materials such as polycrystalline silicon with platinum can be used. Titanium is known to diffuse into silicon and aluminum used for interconnects, so Ti: W
Is generally on another material, which provides increased conductivity and excellent tack. Generally, sputtering techniques are used to deposit a Ti: W material over the isolation oxide layer 28 and the contact region 32.

After forming the thin metallization layer 34, an oxide mask 36 is formed over the metallization layer 34 in the form of a preferred fuse link. This oxide mask 36 is formed by coating the thin metallization layer 34 with an oxide layer and then patterning and etching the oxide layer to form the oxide mask 36. Generally, the oxide mask is between 1000 Angstroms and 2000 Angstroms thick and can be deposited using a chemical vapor deposition (CVD) method.
A fluoridation etch selective about 15: 1 with respect to metallization layer 34 is used to etch this oxide mask 36. The same mask used to form the fuse link 26 in the conventionally developed process of FIG.
Note that it can be used to form oxide mask 36 in the process of the present invention as well.

A second process stage according to the present invention will now be disclosed with reference to FIGS. 3a to 3b. Barrier layer 38 with thin metallization layer
On the oxide mask 36 and the oxide mask 36, a sputtering technique is used. Barrier layer from 1500 Å to 20 Å
It has a thickness of 00 angstroms. Preferably, the barrier layer 38 is also formed of a Ti: W material.

A conductive layer 40 is formed on the barrier layer 38. This conductive layer,
Second, it must be formed of a metal that is used to form the interconnect and is therefore highly conductive. Preferably, the conductive layer 40 is made of aluminum material doped with aluminum or copper. Aluminum material doped with aluminum or copper can be sputtered,
It can be deposited using vapor deposition or CVD techniques.
The thickness of the aluminum conductor is generally in the range of 7000 Angstroms to 8000 Angstroms.

Photoresist masks 42 and 44 are formed over conductive layer 40 to shape the interconnect pattern. Photoresist
Masks 42 and 44 can be created using standard lithographic techniques.

Reference is now made to FIGS. 4a to 4b, which show the last stage of making a fusible link. As described below, the last process stage can be completed using either a dry etching technique or a wet etching technique, and both techniques provide useful results.

The aluminum layer is etched in a chlorinated plasma using a dry etching technique. Chlorinated plasma
During the etch, interconnects 46 and 48 are formed. The chlorinated plasma etch is about 5: 1 selective for Ti: W. After the conductive layer 40 has been etched to the level of the barrier layer 38, a fluorinated plasma etch can be applied over the barrier layer 38 and the thin metallization layer 34. Because the fluorinated plasma etch is oxide selective, the oxide mask 36 does not pass through the etch.
Thus, only the portion of the barrier layer covered by the interconnects 46 and 48 remains, leaving only the remaining barrier layer 38 and the portion of the thin metallization layer 34 covered by the oxide mask 36. The remaining portion of the thin metallization layer 34 below the oxide mask 36 forms the fuse link 50.

The use of dry etching techniques in the disclosed process offers several advantages over previously developed processes. Conventionally developed processes must selectively stop on active semiconductor components. Requires two separate etching steps. Current dry etching techniques are traditionally developed because they do not achieve the selectivity needed to achieve contact with active semiconductor components without harming the thinning of critical constituent oxides The manufacturing method is not suitable for dry etching technology. In the disclosed process (the disclosed process), a fuse link is formed during the first part of the normal barrier etching process, so that only one etching step, which requires a high degree of selectivity for critical layers, Used. Current metal dry etching techniques are well tolerated in one dry etching step, ensuring sufficient selectivity for critical underlying layers.

A major advantage of using the disclosed process with dry metal etching occurs when the conductor pitch (the width of the sum of the spacing between conductors) is 5 microns or less. In this case, dry the conductor and fuse link.
Etching is preferred over wet chemical etching because of greater linewidth control during pattern transfer.
For example, fusible links can be patterned using dry etching techniques to the exact width required to produce a fuse with particular characteristics for predictable results. On the other hand, a wet etch process has poor linewidth control, makes the fuse characteristics somewhat unpredictable, and requires testing of the fuses after they have been formed. However, the anisotropic properties of some dry etching techniques can result in metal filaments remaining at the interconnect stage. These filaments do not normally occur with wet etching.

If a wet etching technique is used in the process disclosed in the present invention, a hydrogen peroxide solution can be used for etching the Ti: W layer, and a solution of phosphoric acid, acetic acid, nitric acid, and an aqueous solution can be used for the aluminum layer. Can be used for etching.

The disclosed process provides several advantages over previously developed processes, whether using wet or dry etching techniques. First, a previously developed process involves a step-by-step photoresist / step formed by interconnects 20 and 22.
It is necessary that the mask form the fuse link. However, in the process of the present invention, the fuse
Link is an oxide mask patterned on a flat surface
36. Therefore, the formation of the fuse link can be more precisely controlled. Second, the number of masks and the number of separate etching steps are reduced by the process of the present invention. Conventionally developed processes require three masks and three separate etching steps: (1) barrier layer formation, (2) interconnect formation, and (3) fuse and fuse formation. Link formation is required. In the process of the present invention, only two masks are needed, one for oxide mask 36 and another for interconnects 46 and 48. No separate step is required to form the barrier layer.

A third advantage of providing both wet and dry etching techniques is the improved alignment tolerance provided by this process. Since the barrier layers and interconnects are formed using a single masking step, they are automatically aligned.

Reference is now made to FIGS. 5-7, which show additional process steps for planarization and via etching. In FIG. 5, a thick oxide layer 52, typically about 18,000 angstroms, is deposited on the fuse link structure of FIG. 4 to completely cover the interconnects 46 and 48.
The oxide layer 52 used as a dielectric can be deposited using a CVD oxide deposition technique. A photoresist layer 54 is formed on the surface of the oxide layer 52 to flatten the steps 56 of the oxide layer 52. The photoresist layer 54 has a thickness of about 4,000 angstroms at its thinnest point and increases to about 15,000 angstroms at its thickest point. The oxide layer 52 and the photoresist layer 54 are etched at the same ratio using a non-selective etch such as fluorinated plasma. Oxide layer 52 is etched to a height that leaves sufficient thickness above interconnects 46 and 48 such that oxide 52 completely covers interconnects 46 and 48, as shown in FIG. I do.

A re-deposited oxide layer 58 is deposited on the surface of the etched oxide layer 52. The redeposited oxide layer 58 allows the interconnect 46
And that the thickness of the conductor between the surface and the surface is at least 7000 angstroms. Similarly, a new layer of oxide can act to fill the pinholes in the oxide layer 52 created during the planarization etch that result in pinholes in the photoresist layer 45.

Referring again to FIG. 6, a patterned photoresist layer 60 is formed on the redeposited oxide layer 58,
A window or "opening" 64 is formed for the first level interconnect. In the described embodiment, openings 64 are formed above interconnect 48. The patterned photoresist layer 60 exposes an opening 64 above the interconnect 48. Patterned photoresist layer 60 can be formed using standard lithographic techniques.

Referring now to FIG. 7, the patterned photoresist layer 60, the redeposited oxide layer 58, and the remaining oxide layer
52 is non-selectively etched so that openings 64 are formed through oxide layer 52 and over interconnect layer 48. A second thin metallization layer 66 is applied to the remaining oxide layers 52 and 58.
(Hereinafter referred to as “derivative” 68). A second thick conductive layer 70 is formed on the surface of the thin metallization layer 66.

The second metallization layer 66 and the second thick conductive layer 70 are patterned and etched using either wet or dry etching techniques to form a second level interconnect. This is shown in FIG. 7 as a second level interconnect 72. Using more than one level of interconnect allows for greater complexity while maintaining the same chip size.

An alternative embodiment of a fuse link having a multilayer interconnect structure is described with reference to FIGS. FIG. 8 illustrates an embodiment of arranging fuse links between second level interconnects. In this embodiment, a doped isolation oxide layer 74 is deposited on a substrate 76. The isolation oxide layer 74 is etched to form a contact region 78 on the substrate 76. Separating oxide layer 74 from thick metallization layer 80
And the contact region 78. The conductive layer 82 is coated on the thick metallization layer 80. The conductive layer 82 is patterned and etched to form a first level interconnect 84. Conductive layer
Both 82 and the thick metallization layer 80 are etched at this stage, whereby the metallization layer 80 serves as a barrier pad between the first interconnect 84 and the contact region 78. Since there is no fuse link at the first level, there is no need to form a thin metallization on the first layer. After the interconnect is etched, the first level is planarized as shown in FIGS. 5 and 6, and the opening is etched as shown in FIGS. 6 and 7.

After the opening has been etched, a thin metallization layer 88 is deposited over the dielectric 90 and the areas 92 where the first level interconnects 84 are exposed. An oxide mask 94 is deposited on the surface of the thin metallization layer 88 and the oxide mask 94 is patterned and etched to form the desired fuse link shape. Next, a barrier layer 96 and a conductive layer 98 are deposited sequentially over the thin metallization layer 88 and oxide mask 94. As shown in FIGS. 2 and 3, conductive layer 98 is patterned and etched to form interconnects 100 and 102 and fuse link 104 therebetween. If necessary, additional layers can be formed using the techniques described above.

FIG. 9 illustrates a two-level interconnect structure having a fuse link at the second level, in which a tungsten plug is used as a pass-through between the first and second levels. Used. In this embodiment,
The first level interconnect is formed as described in connection with FIG. However, rather than etching the openings, use a non-tilted etch to flatten the dielectric layer.
At 90 a passage 108 is created. Non-tilted etching is performed by treating dark ultraviolet (deep UV) resist to maintain the non-tilted angle of the resist, and by reducing the oxide height of the fluorinated plasma etch. Can be. In this preferred embodiment, passage 10
8. Fill one of the two directions with a tungsten material. First, tungsten can be selectively applied to the holes formed in the conductor layer 90, i.e., so that the tungsten fills the passage 108 from the bottom. Alternatively, a non-selective deposition of tungsten may be used, followed by planarization. Although tungsten is used in the preferred embodiment, it can be replaced by any other suitable material that conducts between the first and second level interconnects.

Following formation of the tungsten passage 108, a second level interconnect is formed as described in connection with FIG. The advantage of using the tungsten pass-through 108 as opposed to the opening connections of FIGS. 7 and 8 is that the tungsten pass-through embodiment provides excellent inter-level contacts between interconnects. It is to provide.

Referring now to FIG. 10, the present invention is used in an embodiment using conductive pillars to connect different interconnect levels. In this embodiment, the pillar 110 and the underlying metallization 112 are disposed above the first level leads and connect the first level leads and the second level leads.

In this embodiment, the metallization level layer 34, the oxidation mask
36, barrier layer 38, and conductive layer 40 are formed as described in connection with FIGS. An etching barrier 114 and a pillar layer 116 are formed on the surface of the conductive layer 40. In a preferred embodiment, the etch barrier 114 comprises a Ti: W layer and the pillar layer 116 comprises aluminum or a layer of aluminum and copper.

These layers are masked and etched to form pillars and interconnects. The fuse link is formed in an etching step as described in connection with FIG. The process steps performed to produce the pillar-like connection, embodied herein, are described in US patent application Ser. No. 011,011, filed Jan. 19, 1987.
Issue 355, "Planar Metal Interconnects for VLSI Devices" (198
No. 762,885 filed on Aug. 8, 5 (corresponding to Japanese Patent Application No. 61-184996).

Reference is now made to FIG. 11, which shows another embodiment having two levels of interconnections connected by pillar-like structures. In this embodiment, the fuse link is formed over the second level interconnect. After forming the pillar connections as described in U.S. patent application Ser. No. 011,355, a second level interconnect having fuse links is formed as described in connection with FIGS.

While the preferred embodiment of the invention has been described in detail, various changes, substitutions, and alterations may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that.

 In connection with the above description, the following items are further disclosed.

(1) A method for forming a fuse link between two interconnects, comprising: forming a first conductive layer; and forming a fuse of a preferred size on the first conductive layer.
Forming a first mask in the form of a link; forming a second conductive layer on the mask and on a portion of the first conductive layer that is not covered by the mask; Forming a third conductive layer on the second conductive layer; forming a second mask on the portion of the third conductive layer; covering with the second mask Removing the portions of the second and third conductive layers that are not formed to form an interconnect consisting of the remaining portions of the third conductive layer; and covering the interconnects with the first mask or the second mask. Removing portions of the first conductive layer that are not present, leaving a portion of the first conductive layer under the first mask to form a fuse link. .

(2) The method according to item (1), wherein the first conductive layer is thinner than the second conductive layer and includes a titanium-tungsten material.

(3) The method according to (1), wherein the first conductive layer has a thickness of 400 to 500 Å.

(4) The method according to (1), wherein the second conductive layer includes a titanium-tungsten material.

(5) The method according to (1), wherein the second conductive layer has a thickness of 1500 Å to 200 Å.

(6) The method according to (1), wherein the third conductive layer includes an aluminum material.

(7) The method according to item (6), wherein the third conductive layer includes an alloy of aluminum and copper.

(8) The method according to (1), wherein the first mask includes an insulating material.

(9) The method according to item (8), wherein the insulating material is silicon dioxide.

(10) The method according to item (1), wherein the second mask includes a photoresist material.

(11) The method according to (1), wherein the first, second, and third conductive layers are etched at their original locations.

(12) The method according to (1), further comprising a step of forming a doped oxide layer before forming the conductive layer.

(13) The method according to paragraph (1), further comprising forming a window over the active device through the doped oxide layer, wherein the first conductive layer is formed with the doped oxide layer. , And a portion of the substrate exposed through the window.

(14) A method of forming a fuse link between two interconnects, comprising: forming a first layer of a conductive material that can use the fuse link; and forming a first layer on the first layer. Forming a mask, the mask comprising an electrical isolator; forming a second layer of conductive material over the first layer and the first mask; Forming a third electrically conductive material on the second layer; providing a second mask on the third layer; either the first mask or the second mask; Etching portions of the first, second, and third layers that are not otherwise covered, thereby forming a fuse link below the first mask. Formation method.

(15) The method according to item (14), wherein the etching includes dry etching.

(16) The method according to paragraph (14), wherein the first mask comprises silicon dioxide.

(17) The method according to (14), wherein the first and second layers are made of a titanium-tungsten material, and the third layer contains an aluminum alloy.

(18) The method according to paragraph (14), further comprising: forming an interconnect at a second level, and connecting the second level interconnect to the first level interconnect. Method.

(19) The method of paragraph (18), wherein the second level interconnect is formed over the first level interconnect.

(20) The method of paragraph (18), wherein the first and second level interconnects are connected by tungsten plugs.

(21) The method according to (18), wherein the first and second layers are connected by a conductive pillar structure.

(22) The method according to (21), wherein the pillar-shaped structure comprises an alloy of aluminum and copper.

(23) A method of forming a fuse link between two interconnects, comprising: forming a doped isolation layer on a semiconductor surface having an active device; and forming a window in the isolation layer over the active device. Forming a first layer of electrically conductive material over the doped isolation layer and the active device; forming a first mask over the first layer; A first mask having the shape of a fuse link; forming a second layer of an electrically conductive material over the first layer and the first mask; Forming a third layer; forming a second mask over the third layer; patterning the second mask in an interconnected manner; Etching to form an interconnect; Etching a layer to form a barrier between the interconnect and the semiconductor surface; and etching the first layer to form a barrier between the first layer under the first mask. Fuse between interconnects depending on the part
Forming a fuse link.

(24) The method according to paragraph (23), wherein the doped separation layer comprises a phosphorus-doped silicon dioxide layer.

(25) The method according to (23), further comprising: forming a pillar layer of an electrically conductive material on the third layer; and etching the pillar layer to form a pillar conductive material. Forming the pillars within an interconnect area; coating a layer of dielectric over the pillars and the interconnect; and planarizing a layer of photoresist over the dielectric. Forming an etch ratio of the dielectric and the photoresist to be substantially equal; and etching back the dielectric of the photoresist so that a small portion of the pillar is exposed. Coating the pillars and another layer of conductive material over the dielectric material to form a second level interconnect.

(26) a semiconductor surface having an active device; two spaced apart electrically conductive interconnects on the semiconductor surface; and a fuse layer formed between the semiconductor surface and the interconnect. A fuse layer having a link portion of a predetermined shape between the interconnects; and an isolation layer formed on the link portion, the isolation layer also having the predetermined shape of the fuse layer. And a semiconductor device including:

(27) The semiconductor device according to (26), further comprising a barrier layer formed between the interconnect and the semiconductor surface.

(28) The semiconductor device according to paragraph (26), wherein the interconnect comprises a first layer interconnect, and further comprising a second level electrical connection connected to one of the first level interconnects. Semiconductor device including electrical interconnects.

(29) A fuse link manufactured by the method described in paragraph (1).

(30) A fuse link manufactured by the method described in (14).

(31) A fuse link manufactured by the method described in paragraph (23).

(32) Fuse link 50 is formed using a method that provides greater scalability of the common conductive structure used to wire devices. An oxide mask 36 having the preferred fuse link shape is formed over the thin metallization layer 34. A barrier layer 38 is formed over the thin metallization layer 34. A conductive layer 40 is formed on the barrier layer 38. After applying the photoresist masks 42 and 44 to the conductive layer 40,
The conductive layer is etched to form interconnects 46,48. Next, the barrier layer 38 and the thin metallization layer 34 are etched, thus providing a fuse link 50 between the interconnects 46, 48 under the oxide mask 36.

[Brief description of the drawings]

1a and 1b are a plan view and a cross-sectional view of a conventional fuse link disposed between two interconnects. 2a and 2b show a cross section and a plan view of a first stage of the present invention, in which the isolation oxide layer,
A metallization layer and an oxide mask are formed over the substrate. 3a and 3b show a cross-section and a plan view of a second stage of the process, where a second metallization layer is formed, a first conductive layer is formed, and an interconnect is etched. Is applied. 4a and 4b show a cross section and a plan view of a third stage of the process, in which an interconnect is formed, the photoresist layer is removed, and the second metallization layer is etched. FIG. 5 shows a cross-sectional view of the planarization stage, in which an oxide and photoresist layer is formed for planarization purposes. FIG. 6 shows a cross-sectional view of a first stage forming an optional second level interconnect. FIG. 7 illustrates the second stage of the second level interconnect formation. FIG. 8 shows a cross-sectional view of a two-level embodiment of the present invention having a fuse link at the second level. FIG. 9 uses tungsten plugs between levels,
FIG. 4 shows a cross-sectional view of an alternative embodiment of the second level fuse link. FIG. 10 shows the first level with a fuse link, 2
Figure 5 illustrates another embodiment of the present invention that uses aluminum pillars between levels. FIG. 11 shows a cross-sectional view of another embodiment of the present invention using an aluminum pillar between levels having a fuse link at the second level. Key Description 28: Isolating Oxide 30: Substrate 31: Active Device 34: Thin Metallization 36: Oxide Mask 38: Barrier 40: Conductive 42, 44: Photoresist Mask 46, 48: Interconnect 50: Fuse link 66: Second thin metallization layer 70: Second conductive layer 72: Second level interconnect

 ────────────────────────────────────────────────── ─── Continuing the front page (72) Inventor Manuel Lewis Trueno, Jr. Meadow Lake Drive, Houston, Texas, USA 12207 (72) Inventor Everist Garcia, Jr. Rosenberg, Texas, USA, number 111 Bloom 725 (56) References JP-A-59-208854 (JP, A)

Claims (1)

(57) [Claims] 1. A method of forming a fuse link between two interconnects, the method comprising: forming a first conductive layer; and forming a fuse link of a preferred size over the first conductive layer. Forming a first mask on the mask; and forming a second conductive layer on the mask and on a portion of the first conductive layer that is not covered by the mask. Forming a third conductive layer on the second conductive layer; forming a second mask on the portion of the third conductive layer; and forming the second mask not covered with the second mask. Removing portions of the second and third conductive layers to form an interconnect consisting of remaining portions of the third conductive layer; and removing the interconnect not covered by the first mask or the second mask. Removing a portion of the first conductive layer and removing the first conductive layer under the first mask; Leave the fuse
Forming a fuse link.