JPH039524A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH039524A
JPH039524A JP14479889A JP14479889A JPH039524A JP H039524 A JPH039524 A JP H039524A JP 14479889 A JP14479889 A JP 14479889A JP 14479889 A JP14479889 A JP 14479889A JP H039524 A JPH039524 A JP H039524A
Authority
JP
Japan
Prior art keywords
conductor layer
film
contact
materials
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14479889A
Other languages
Japanese (ja)
Inventor
Toshio Nomura
俊雄 野村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14479889A priority Critical patent/JPH039524A/en
Publication of JPH039524A publication Critical patent/JPH039524A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve unstability existing in a contact part between different kind of materials by constituting contact connection at the contact part of multilayer wirings by using the same kind of materials. CONSTITUTION:A first conductor layer 2 constituted of multilayer formed on a substrate 1, and a second conductor layer 3 constituted of multilayer formed via an insulating film 3 are provided. At the connection part of the conductor layer 2 and the conductor layer 4, said layers are connected by using the same kind of materials 2A, 4A. As a result, the contact can be formed by not different kind of materials but the same kind of materials. Thereby, the movement of impurity and the discontinuity of interface can be improved, and reliability is enhanced.

Description

【発明の詳細な説明】 〔概要〕 本発明は半導体装置における積層構造を有する導体層と
のコンタクトに関し。
DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to contact with a conductor layer having a stacked structure in a semiconductor device.

異種材料間によるコンタクトを通じて不純物が移動した
り、又、界面が不連続になる等の影響でコンタクト抵抗
が高くなったり、ばらついたりするといった問題を改善
することを目的とし。
The purpose is to improve problems such as impurities moving through contacts between different materials, and contact resistance becoming high and fluctuating due to discontinuous interfaces.

基板上に形成された単層或いは多層からなる第1の導体
層と、絶縁膜を介して、単層或いは多層からなる第2の
導体層とを有し、該第1の導体層と該第2の導体層の接
続部において、該第1の導体層と該第2の導体層が同種
の材料により接続されていることにより構成する。
It has a first conductor layer formed on a substrate and made of a single layer or a multilayer, and a second conductor layer made of a single layer or a multilayer with an insulating film interposed between the first conductor layer and the first conductor layer. At the connection portion between the two conductor layers, the first conductor layer and the second conductor layer are connected by the same kind of material.

〔産業上の利用分野〕[Industrial application field]

本発明は、半導体装置における積層構造を有する導体層
とのコンタクトに関する。
The present invention relates to a contact with a conductor layer having a stacked structure in a semiconductor device.

近年、半導体装置の高集積化・高速化にともない2配線
を形成する導体層に積層構造が使用されるが、上層の導
体層とコンタクトする場合、異種の材料間でコンタクト
する場合があり、コンタクトが不安定であった。
In recent years, as semiconductor devices have become more highly integrated and faster, a laminated structure has been used for conductor layers forming two interconnections, but when making contact with the upper conductor layer, there are cases where contact is made between different materials. was unstable.

〔従来の技術〕[Conventional technology]

第3図は従来例を示す説明図である。 FIG. 3 is an explanatory diagram showing a conventional example.

図において、 13は基板、14は第1の導体層、15
は絶縁膜、16は第2の導体層、 17は基板、 18
は第1の導体層、19は絶縁膜、 20は第2の導体層
である。
In the figure, 13 is the substrate, 14 is the first conductor layer, 15
16 is an insulating film, 16 is a second conductor layer, 17 is a substrate, 18
is a first conductor layer, 19 is an insulating film, and 20 is a second conductor layer.

第3図(a)に示すように。As shown in FIG. 3(a).

基板13上に形成された積層構造を有する第1の導体層
14上に絶縁膜15を形成する。
An insulating film 15 is formed on a first conductor layer 14 having a laminated structure formed on a substrate 13 .

次に、コンタクトすべき領域の絶縁膜15をエツチング
除去し、その後第2の導体層16を形成していた。
Next, the insulating film 15 in the area to be contacted is removed by etching, and then the second conductive layer 16 is formed.

ここで、第1の導体層14の下層部14Aは第2の導体
層16と同種の材料、第1の導体層14の上層部14B
は第2の導体層16とは異種の材料とする。
Here, the lower layer part 14A of the first conductor layer 14 is made of the same material as the second conductor layer 16, and the upper layer part 14B of the first conductor layer 14 is made of the same material as the second conductor layer 16.
is made of a material different from that of the second conductor layer 16.

この場合、第1の導体層14の上層部14Bと第2の導
体層16がコンタクトするので、異種材料間のコンタク
トとなる。
In this case, the upper layer portion 14B of the first conductor layer 14 and the second conductor layer 16 are in contact, resulting in contact between different materials.

又、第3図(b)に示すように。Also, as shown in FIG. 3(b).

基板17上に形成された第1の導体層18上に絶縁膜1
9を形成する。
An insulating film 1 is formed on the first conductor layer 18 formed on the substrate 17.
form 9.

次に、コンタクトすべき領域の絶縁膜19をエツチング
除去し、その後第2の導体層20を形成していた。
Next, the insulating film 19 in the area to be contacted is removed by etching, and then the second conductor layer 20 is formed.

ここで、第2の導体層20の上層部20Bは第1の導体
層18と同種の材料、第2の導体層20の下層部20A
は第1の導体層18とは異種の材料とする。
Here, the upper layer part 20B of the second conductor layer 20 is made of the same material as the first conductor layer 18, and the lower layer part 20A of the second conductor layer 20 is made of the same material as the first conductor layer 18.
is made of a material different from that of the first conductor layer 18.

この場合、第1の導体層18と第2の導体層20の下層
部2OAがコンタクトするので、同じく異種材料間のコ
ンタクトとなる。
In this case, since the first conductor layer 18 and the lower layer portion 2OA of the second conductor layer 20 are in contact with each other, this also results in contact between different materials.

〔発明が解決しようとする課題] 従って、前記の異種材料間によるコンタクトを通じて不
純物が移動したり、又、界面が不連続になる等の影響で
コンタク1−抵抗が高(なったり。
[Problems to be Solved by the Invention] Therefore, the resistance of the contact 1 may become high due to the influence of impurities moving through the contact between different materials or discontinuity of the interface.

ばらついたりするといった問題を生じていた。This caused problems such as variations.

本発明は9上記の問題を改善することを目的とする。The present invention aims to improve the above-mentioned problems.

〔課題を解決するための手段〕[Means to solve the problem]

第1図は本発明の原理説明図である。 FIG. 1 is a diagram explaining the principle of the present invention.

図において、1は基板、2は第1の導体層、3は絶縁膜
、4は第2の導体層である。
In the figure, 1 is a substrate, 2 is a first conductor layer, 3 is an insulating film, and 4 is a second conductor layer.

本発明は、第1図に示すように、基板l上に形成された
単層或いは多層からなる第1の導体層2と、絶縁膜3を
介して、単層或いは多層の第2の導体層4とを有し、第
1の導体層2と第2の導体層4の接続部において、第1
の導体層2と第2の導体N4が同種の材料により接続さ
れている。
As shown in FIG. 1, the present invention includes a first conductor layer 2 formed on a substrate l, which is a single layer or a multilayer, and a second conductor layer 2, which is a single layer or a multilayer, with an insulating film 3 interposed therebetween. 4, and at the connection portion between the first conductor layer 2 and the second conductor layer 4, the first
The conductor layer 2 and the second conductor N4 are connected by the same kind of material.

〔作用〕[Effect]

本発明では、第1図の如く、多層配線のコンタクト部に
おいて、同種の材料によりコンタクト接続できる。
In the present invention, as shown in FIG. 1, contact connections can be made using the same type of material in the contact portions of multilayer wiring.

従って、異種材料間でのコンタクトにおいて見られる不
安定性がなくなる。
Therefore, the instability found in contacts between dissimilar materials is eliminated.

(実施例〕 第2図は本発明の一実施例の工程順模式断面図である。(Example〕 FIG. 2 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps.

図において、5はSi基板、6はポリSi膜、7はWS
ix膜、8はレジスト、9はSiO□膜、 10はレジ
スト、 11はポリSi膜、12は一5i2膜である。
In the figure, 5 is a Si substrate, 6 is a poly-Si film, and 7 is a WS
ix film, 8 is a resist, 9 is a SiO□ film, 10 is a resist, 11 is a poly-Si film, and 12 is a -5i2 film.

第2図(a)に示すように。As shown in FIG. 2(a).

Si基板5上ニCVD法により、シラ7(Sit14)
ガス流150cc/ll1in、真空度0.2Torr
、反応温度625°Cの条件で、ポリSi膜6を2,0
00人の厚さに形成し。
Sila 7 (Sit14) is formed on the Si substrate 5 by CVD method.
Gas flow 150cc/11in, vacuum degree 0.2Torr
, the poly-Si film 6 was heated at 2,0°C under the reaction temperature of 625°C.
Formed to a thickness of 0.00 people.

続いて、 SiH4ガス流量1,0OOcc/min、
 WFiガス流it 8cc/min、真空度QJTo
rr、反応温度360°Cの条件で、 WSi2膜7を
2,000人の厚さに積層して形成する。
Subsequently, SiH4 gas flow rate 1,000cc/min,
WFi gas flow it 8cc/min, vacuum degree QJTo
WSi2 film 7 is laminated to a thickness of 2,000 wafers under conditions of rr and reaction temperature of 360°C.

第2図(b)に示すように。As shown in FIG. 2(b).

レジスト8をパタニングし、レジスト8をマスクとして
、コンタクトホールより幅の広い大きさに−Si2膜7
をエツチングで開口する。
The resist 8 is patterned, and using the resist 8 as a mask, the -Si2 film 7 is patterned to a size wider than the contact hole.
Open by etching.

これは、コンタクトホール側面にも異種材料(WSi*
膜7)を露出させない為である。
This means that the sides of the contact hole are also made of a different material (WSi*).
This is to prevent the film 7) from being exposed.

更に1図示しないレジストをパタニングし、レジストを
マスクとして、 WSi2膜7とポリSi膜6をパタニ
ングして、下層の配線パターンを形成する。
Furthermore, a resist (not shown) is patterned, and using the resist as a mask, the WSi2 film 7 and the poly-Si film 6 are patterned to form a lower wiring pattern.

第2図(c)に示すように Sin、膜9をCVO法により9反応温度800°Cで
As shown in FIG. 2(c), a film 9 of Sin was formed by the CVO method at a reaction temperature of 800°C.

4.000人の厚さに被覆する。Coat to a thickness of 4.000 people.

第2図(d)に示すように。As shown in FIG. 2(d).

レジス)10をパタニングし、レジスト10をマスクと
して、 SiO□膜9にコンタクトホールをエツチング
で開口する。
The resist 10 is patterned, and a contact hole is opened in the SiO□ film 9 by etching using the resist 10 as a mask.

第2図(e)に示すように SiO□膜9及びコンタクトホール上に、 CVO法に
より、 51g4ガス流ff150cc/min、真空
度 0.2Torr反応温度625°Cの条件で、ポリ
Si膜11を2.000人の厚さに形成し、続いて、 
SiH4ガス流量L 、 000cc/min、 WF
aガス流!J、8cc/min、真空度 Q、2Tor
r。
As shown in FIG. 2(e), a poly-Si film 11 was formed on the SiO□ film 9 and the contact hole by the CVO method under the conditions of a 51g4 gas flow ff150cc/min, a degree of vacuum of 0.2 Torr, and a reaction temperature of 625°C. Formed to a thickness of 2.000 people, followed by
SiH4 gas flow rate L, 000cc/min, WF
a gas flow! J, 8cc/min, degree of vacuum Q, 2 Tor
r.

反応温度360°Cの条件で、匈S1□膜12を2,0
00人の厚さに積層して形成する。
Under the condition of reaction temperature 360°C, 2.0
Formed by laminating to a thickness of 0.00 people.

これにより、コンタクトホールにおいて、上層のポリS
i膜IIと下層のポリS4膜6が直接にコンタクトする
As a result, in the contact hole, the upper layer polyS
The i film II and the underlying poly S4 film 6 are in direct contact.

そして1図示しないレジストをパタニングし、レジスト
をマスクとして、 WSiz膜12とポリSi膜11を
パタニングして、上層の配線パターンを形成する。
Then, a resist (not shown) is patterned, and the WSiz film 12 and the poly-Si film 11 are patterned using the resist as a mask to form an upper layer wiring pattern.

〔発明の効果〕〔Effect of the invention〕

以上説明したように2本発明によれば異種材料間でのコ
ンタクトではなく、同種の材料どうしでコンタクトする
ことができるので、不純物の移動や界面の不連続性など
が改善され、コンタクトの信頼性向上に寄与するところ
が大きい。
As explained above, according to the present invention, it is possible to make contact not between different materials, but between materials of the same type, which improves the movement of impurities and discontinuities at the interface, improving the reliability of the contact. It greatly contributes to improvement.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理説明図。 第2図は本発明の一実施例の工程順模式断面図。 第3図は従来例の説明図である。 図において。 1は基板。 3は絶縁膜。 5はSi基板。 7は一3i2膜。 9はSiO□膜。 11はポリSi膜。 2は第1の導体層 4は第2の導体層 6はポリSi膜。 8はレジスト 10はレジスト 12はWSi2膜 7!、発明の原理勘明Z 第j閾 鴇2z FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps. FIG. 3 is an explanatory diagram of a conventional example. In fig. 1 is the board. 3 is an insulating film. 5 is a Si substrate. 7 is -3i2 membrane. 9 is a SiO□ film. 11 is a poly-Si film. 2 is the first conductor layer 4 is the second conductor layer 6 is a poly-Si film. 8 is resist 10 is resist 12 is WSi2 film 7! , Understanding the principles of invention Z jth threshold Toki 2z

Claims (1)

【特許請求の範囲】[Claims] 基板(1)上に形成された単層或いは多層からなる第1
の導体層(2)と、絶縁膜(3)を介して、単層或いは
多層からなる第2の導体層(4)とを有し、該第1の導
体層(2)と該第2の導体層(4)の接続部において、
該第1の導体層(2)と該第2の導体層(4)が同種の
材料により接続されていることを特徴とする半導体装置
A first layer consisting of a single layer or multiple layers formed on a substrate (1).
a conductor layer (2), and a second conductor layer (4) consisting of a single layer or multiple layers, with an insulating film (3) interposed between the first conductor layer (2) and the second conductor layer (4). At the connection part of the conductor layer (4),
A semiconductor device characterized in that the first conductor layer (2) and the second conductor layer (4) are connected by the same kind of material.
JP14479889A 1989-06-07 1989-06-07 Semiconductor device Pending JPH039524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14479889A JPH039524A (en) 1989-06-07 1989-06-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14479889A JPH039524A (en) 1989-06-07 1989-06-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH039524A true JPH039524A (en) 1991-01-17

Family

ID=15370708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14479889A Pending JPH039524A (en) 1989-06-07 1989-06-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH039524A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453400A (en) * 1990-06-28 1995-09-26 International Business Machines Corporation Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits
US5500560A (en) * 1991-11-12 1996-03-19 Nec Corporation Semiconductor device having low resistance values at connection points of conductor layers
JP2003047756A (en) * 2001-08-03 2003-02-18 Oizumi Corp Display device of game machine
KR200482278Y1 (en) * 2016-05-04 2017-01-06 허만회 Rotary protruding guide display device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62104138A (en) * 1985-10-31 1987-05-14 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62104138A (en) * 1985-10-31 1987-05-14 Nec Corp Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453400A (en) * 1990-06-28 1995-09-26 International Business Machines Corporation Method and structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits
US5672901A (en) * 1990-06-28 1997-09-30 International Business Machines Corporation Structure for interconnecting different polysilicon zones on semiconductor substrates for integrated circuits
US5500560A (en) * 1991-11-12 1996-03-19 Nec Corporation Semiconductor device having low resistance values at connection points of conductor layers
JP2003047756A (en) * 2001-08-03 2003-02-18 Oizumi Corp Display device of game machine
KR200482278Y1 (en) * 2016-05-04 2017-01-06 허만회 Rotary protruding guide display device

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