JPS63107141A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63107141A
JPS63107141A JP25396486A JP25396486A JPS63107141A JP S63107141 A JPS63107141 A JP S63107141A JP 25396486 A JP25396486 A JP 25396486A JP 25396486 A JP25396486 A JP 25396486A JP S63107141 A JPS63107141 A JP S63107141A
Authority
JP
Japan
Prior art keywords
film
aluminum
polycrystalline silicon
electrode window
silicon film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25396486A
Other languages
Japanese (ja)
Inventor
Hideki Fushimi
英樹 伏見
Mutsuo Yoshinami
睦男 良波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP25396486A priority Critical patent/JPS63107141A/en
Publication of JPS63107141A publication Critical patent/JPS63107141A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To form an aluminum wiring characterized by less wire breakdown, by depositing a polycrystalline silicon film on an insulating film before an electrode window is formed, opening and forming the window in both films simultaneously, depositing an aluminum film on the upper surface including the electrode window, forming an electrode and the aluminum wiring, thereby forming a gentle taper surface around the electrode window. CONSTITUTION:A PSG film 2 and a polycrystalline silicon film 10 are laminated and deposited on a semiconductor substrate 4. Then a resist film mask 5 for opening an electrode window is formed on the upper surface. The polycrystalline silicon film 10 and about one half of the PSG film 2 are isotropically etched by plasma etching. Then the remaining one half of the thickness of the PSG film 2 undergoes anisotropic etching, and the electrode window 13' is formed. Thereafter, the resist film mask 5 is removed, and an aluminum film 11 is deposited by sputtering. At this time, since the electrode window has a gently tapered side surface, the aluminum film is thickly deposited on the side of the electrode window. Thereafter, the aluminum film 11, under which the polycrystalline silicon film 10 is provided, is patterned, and a wiring is formed.

Description

【発明の詳細な説明】 [概要] 電極窓を窓開けする前に、絶縁膜上に多結晶シリコン膜
を被着し、両膜を同時に開口して電極窓を形成し、電極
窓を含む上面にアルミニウム膜を被着し、アルミニウム
膜と多結晶シリコン膜とを共にパターンニングして、絶
縁膜上に多結晶シリコン膜を下層にしたアルミニウム配
線を形成する。
[Detailed Description of the Invention] [Summary] Before opening an electrode window, a polycrystalline silicon film is deposited on an insulating film, both films are opened simultaneously to form an electrode window, and the upper surface including the electrode window is An aluminum film is deposited on the insulating film, and the aluminum film and the polycrystalline silicon film are patterned together to form an aluminum wiring with the polycrystalline silicon film as the lower layer on the insulating film.

そうすれば、アルミニウム配線は配線層および電橋部分
での断線が少なくなる。
This will reduce disconnections in the wiring layer and bridge portions of the aluminum wiring.

[産業上の利用分野コ 本発明は、半導体装置の製造方法にかかり、特に、アル
ミニウム配線の形成方法に関する。
[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming aluminum wiring.

ICやLSIなどの半導体装置においては、半導体基板
上に多数の素子が設けられ、これらを接続するための電
極配線が形成されている。このようなICの配線材料に
はアルミニウム(AI)が最も良く利用されており、そ
れはアルミニウムが電気伝導性が良くて且つ安価に得ら
れる材料であるからである。
In semiconductor devices such as ICs and LSIs, a large number of elements are provided on a semiconductor substrate, and electrode wiring is formed to connect these elements. Aluminum (AI) is most often used as a wiring material for such ICs because aluminum has good electrical conductivity and is a material that can be obtained at low cost.

一方、ICの信頼性を低下させる最大の原因は配線層の
断線や短絡のトラブルであり、従前よりその対策が採ら
れてきたが、ICの高集積化、微細化の進展と共に益々
その対策が困難になりつつあり、従って、その微細な電
極や配線に相応した対策が望まれている。
On the other hand, the biggest cause of reduced IC reliability is problems such as disconnections and short circuits in wiring layers, and countermeasures have been taken for a long time, but as ICs become more highly integrated and miniaturized, countermeasures are becoming more and more difficult. This is becoming increasingly difficult, and therefore, countermeasures suitable for the fine electrodes and wiring are desired.

[従来の技術と発明が解決しようとする問題点]第2図
はICにおけるアルミニウム配線の平面図を示しており
、1はアルミニウム配線、2は絶縁膜で、同図のように
、通常の配線幅は、例えば、2μmと狭いが、1.2μ
mφの電極3(点線で示す)との接続部は4μmと配線
幅を約2倍に広くして、断線しないように配慮しである
[Prior art and problems to be solved by the invention] Figure 2 shows a plan view of aluminum wiring in an IC. 1 is an aluminum wiring, 2 is an insulating film, and as shown in the figure, normal wiring The width is narrow, for example, 2μm, but it is 1.2μm.
The connection portion with the mφ electrode 3 (indicated by a dotted line) is made to have a wiring width of 4 μm, which is about twice as wide, in order to prevent disconnection.

第3図(a)〜(C)は、第2図の部分における従来の
アルミニウム配線の形成工程順断面図を示している。ま
ず、同図(a)に示すように、半導体基板4上の燐シリ
ケートガラス(P S G)膜2 (膜厚1〜1.5μ
m)からなる絶縁膜上に、電極窓を窓開けするためのレ
ジスト膜マスク5をフォトプロセスによって形成する。
FIGS. 3(a) to 3(C) show cross-sectional views of the conventional aluminum wiring forming process in the portion shown in FIG. 2. First, as shown in FIG.
A resist film mask 5 for opening an electrode window is formed on the insulating film consisting of m) by a photo process.

次いで、第3図(blに示すように、弗素系の反応ガス
を用いたドライエツチングによって、PSGS2O2厚
の半分程度まで等友釣にエツチングする。そうすれば、
レジスト膜マスク5の下にエツチング深さと同程度の幅
のアンダーカットが入る。
Next, as shown in FIG. 3 (bl), dry etching is performed using a fluorine-based reactive gas to uniformly etch to about half the thickness of PSGS2O2.
An undercut having a width comparable to the etching depth is formed under the resist film mask 5.

次いで、同図(C1に示すように、PSGS2O2厚の
残り半分を異方性エツチングして、直径1.2μmφの
電極窓(コンタクトホール)3°を開口する。
Next, as shown in the same figure (C1), the remaining half of the PSGS2O2 thickness is anisotropically etched to open an electrode window (contact hole) of 3° with a diameter of 1.2 μmφ.

次いで、レジスト膜マスク5を除去して、第3図(d)
に示すように、膜厚1μm程度のアルミニウム膜1を被
着する。しかる後、図示していないが、他のレジスト膜
マスクを形成し、アルミニウム膜をパターンニングして
、アルミニウム配線に形成する。
Next, the resist film mask 5 is removed, as shown in FIG. 3(d).
As shown in FIG. 2, an aluminum film 1 having a thickness of about 1 μm is deposited. Thereafter, although not shown, another resist film mask is formed, and the aluminum film is patterned to form aluminum wiring.

しかしながら、アルミニウムをスパッタ法又は蒸着法で
被着すると、被着の方向性のために凹部へのカバーレイ
ジ(被覆性)が悪く、第3図(d)ノ断面図に示すよう
に、電極窓は側面の急峻なテーバ−(傾斜)に阻まれて
電極窓の中にはアルミニウム膜は薄くしか被着せず、そ
のため、この電極部分で断線し易いと云う問題がある。
However, when aluminum is deposited by sputtering or vapor deposition, the coverage of the recesses is poor due to the directionality of the deposition, and as shown in the cross-sectional view of FIG. 3(d), the electrode window The problem is that the aluminum film is only thinly deposited inside the electrode window due to the steep taper (slope) of the side surface, and therefore, the wire is easily broken at this electrode portion.

また、アルミニウム配線はPSG膜などの絶縁膜上に設
けられるから、PSG膜中の燐が水分を吸収し、その水
分によってアルミニウムが酸化して断線し易いと云う欠
点がある。
Further, since the aluminum wiring is provided on an insulating film such as a PSG film, there is a drawback that phosphorus in the PSG film absorbs moisture, and the aluminum is easily oxidized by the moisture, resulting in wire breakage.

本発明は、これらの2つの問題点を共に低減して、断線
を減少させる製造方法を提案するものである。
The present invention proposes a manufacturing method that reduces both of these two problems and reduces wire breaks.

[問題点を解決するための手段] その目的は、絶縁膜と多結晶シリコン膜とを積層し、該
絶縁膜と多結晶シリコン膜とを同時に窓開けして電極窓
を形成し、該電極窓を含む前記多結晶シリコン膜上にア
ルミニウム膜を被着し、該アルミニウム膜と前記多結晶
シリコン膜とを同時にパターンニングして、前記電極窓
に接続したアルミニウム配線を形成する工程が含まれる
半導体装置の製造方法によって達成される。
[Means for solving the problem] The purpose is to stack an insulating film and a polycrystalline silicon film, open a window in the insulating film and the polycrystalline silicon film at the same time to form an electrode window, and A semiconductor device comprising the steps of: depositing an aluminum film on the polycrystalline silicon film containing the polycrystalline silicon film, and simultaneously patterning the aluminum film and the polycrystalline silicon film to form an aluminum wiring connected to the electrode window. This is achieved by the manufacturing method.

[作用コ 即ち、本発明は、電極窓を窓開けする前に、絶縁膜上に
多結晶シリコン膜を被着し、両膜を同時に窓開けして電
極窓を形成し、電極窓を含む上面にアルミニウム膜を被
着し、電極はアルミニウム膜で埋めて、絶縁膜上はアル
ミニウム膜/多結晶シリコン膜からなる配線を形成する
[In other words, in the present invention, before opening an electrode window, a polycrystalline silicon film is deposited on an insulating film, and both films are opened simultaneously to form an electrode window, and the upper surface including the electrode window is An aluminum film is deposited on the substrate, the electrodes are filled with the aluminum film, and a wiring made of an aluminum film/polycrystalline silicon film is formed on the insulating film.

そうすれば、電極窓の周囲がなだらかなテーパーに形成
されて、電極窓でアルミニウムが厚く被着して断線が少
な(なり、且つ、絶縁膜上の配線層は下層に多結晶シリ
コン膜を介在しているため、水分の侵入による断線が減
少する。
By doing so, the periphery of the electrode window will be formed into a gentle taper, and the electrode window will have a thick coating of aluminum, reducing disconnections (and the wiring layer on the insulating film will have a polycrystalline silicon film interposed underneath). This reduces disconnections due to moisture intrusion.

[実施例] 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

第1図(a)〜(d)は本発明にかかる形成工程順断面
図である。
FIGS. 1(a) to 1(d) are sequential sectional views of the forming steps according to the present invention.

第1図(a)に示すように、半導体基板4上に化学気相
成長法によって膜厚1〜1.5μmのPSGS2O2び
膜厚500〜2000人の多結晶シリコン膜10を積層
被着する。この多結晶シリコン膜は燐を含み、シート抵
抗を60Ωる程度まで下げた導電性の膜にする。
As shown in FIG. 1(a), a polycrystalline silicon film 10 having a thickness of 1 to 1.5 μm and a polycrystalline silicon film 10 of 500 to 2,000 layers is deposited on a semiconductor substrate 4 by chemical vapor deposition. This polycrystalline silicon film contains phosphorus and is made into a conductive film with sheet resistance reduced to about 60Ω.

次いで、第1図(b)に示すように、その上面に、電極
窓を窓開けするためのレジスト膜マスク5を形成し、C
F4 +02ガスを反応ガスとして、マイクロ波励起の
プラズマエツチングによって、多結晶シリコン膜10と
PSGS2O2エツチングし、PSGS2O2分程度の
膜厚まで等友釣にエツチングする。そうすると、多結晶
シリコン膜10のエツチング速度はPSGS2O2ツチ
ング速度より約二倍速く、そのため、まず、多結晶シリ
コン膜10がレジスト膜マスク5の下まで側方に深くエ
ツチングされて、アンダーカットが入り、次に、下方の
PSGS2O2ツチングされるから、図示のようになだ
らかなテーパーをもった電極窓13゛が形成される。
Next, as shown in FIG. 1(b), a resist film mask 5 for opening an electrode window is formed on the upper surface, and C
Using F4+02 gas as a reaction gas, the polycrystalline silicon film 10 and PSGS2O2 are etched by microwave-excited plasma etching, and the polycrystalline silicon film 10 and PSGS2O2 are uniformly etched to a film thickness of about PSGS2O2. Then, the etching speed of the polycrystalline silicon film 10 is about twice as fast as the PSGS2O2 etching speed, so that the polycrystalline silicon film 10 is first etched laterally and deeply below the resist film mask 5, creating an undercut. Next, since the lower PSGS2O2 is etched, an electrode window 13' having a gentle taper as shown in the figure is formed.

次いで、第1図(C)に示すように、PSGS2O2厚
の残り半分をCF4又はCHF3又はその混合ガスを反
応ガスとして異方性エツチングして、直径1.2μmφ
の電極窓13″を形成する。この異方性エツチングはり
アクティブイオンエツチング(RI E)と呼ばれるエ
ツチング法で、垂直にレジスト膜マスクの通りにエツチ
ングされる。
Next, as shown in FIG. 1(C), the remaining half of the PSGS2O2 thickness was anisotropically etched using CF4, CHF3, or a mixture thereof as a reaction gas to form a 1.2 μm diameter
An electrode window 13'' is formed in this anisotropic etching process using an etching method called active ion etching (RIE), which is etched vertically along the resist film mask.

次いで、レジスト膜マスク5を除去し、第1図(dlに
示すように、膜厚1μm程度のアルミニウム膜11をス
パッタ法で被着する。その時、電極窓はなだらかなテー
パーの側面をもった窓であるから、電極窓の内部に厚(
アルミニウム膜が被着する。
Next, the resist film mask 5 is removed, and as shown in FIG. Therefore, there is a thickness (
An aluminum film is deposited.

しかる後、図示していないが、多結晶シリコン膜10を
下層に介在させたアルミニウム膜11をパターンニング
して、配線を形成する。
Thereafter, although not shown, the aluminum film 11 with the polycrystalline silicon film 10 interposed therebetween is patterned to form wiring.

そうすれば、電極窓13°はアルミニウム膜のみで埋没
され、PSG膜上はアルミニウム膜/多結晶シリコン膜
(上/下)からなるアルミニウム膜主体の配線が形成さ
れる。このような配線層は、電極窓はアルミニウムが厚
く被着していて断線が少なく、且つ、PSG膜上の配線
は下層に多結晶シリコン膜を介在しているためにアルミ
ニウム膜への水分の侵入を抑止して、アルミニウムの酸
化による断線が減少する。従って、本発明にかかる形成
方法によれば、ICなど半導体装置の高信頼化に役立つ
Then, the electrode window 13° is buried only with the aluminum film, and on the PSG film, an aluminum film-based wiring consisting of an aluminum film/polycrystalline silicon film (top/bottom) is formed. In such a wiring layer, the electrode window is coated with aluminum thickly, so there are few disconnections, and the wiring on the PSG film has a polycrystalline silicon film interposed in the lower layer, so there is no possibility of moisture intrusion into the aluminum film. This reduces wire breakage due to aluminum oxidation. Therefore, the formation method according to the present invention is useful for increasing the reliability of semiconductor devices such as ICs.

[発明の効果] 以上の説明から明らかなように、本発明によればICな
ど半導体装置の信頼性向上に大きな効果があるものであ
る。
[Effects of the Invention] As is clear from the above description, the present invention has a significant effect on improving the reliability of semiconductor devices such as ICs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(al〜(d)は本発明にかかる形成工程順断面
図、第2図はアルミニウム配線の断面図、 第3図(al〜(dlは従来の形成工程順断面図である
。 図において、 1.11はアルミニウム配線又はアルミニウム膜、2は
絶縁膜またはPSG膜、 3は電極、 3’、13’は電極窓、 4は半導体基板、 5はレジスト膜マスク、 10は多結晶シリコン膜 を示している。 第1図 了ルミニークム西e糸蜜d1斗jジ図 第2図 従艇のボ分茂工寸し11面自析酌図 1 アルミニウム順 イメe、tc)→N$ 11’原111Mコ第3図
Figures 1 (al to d) are cross-sectional views in the order of the formation process according to the present invention, Figure 2 is a cross-sectional view of an aluminum wiring, and Figure 3 (al to (dl) are cross-sectional views in the order of the conventional formation process. 1.11 is an aluminum wiring or an aluminum film, 2 is an insulating film or a PSG film, 3 is an electrode, 3', 13' are electrode windows, 4 is a semiconductor substrate, 5 is a resist film mask, 10 is a polycrystalline silicon film Figure 1: Luminiqueum Nishi e Itomitsu d1 Toj Figure 2: Subordinate boat's dimensions and 11-sided autoanalysis Figure 1 Aluminum order image e, tc) → N$ 11' Hara 111Mko Figure 3

Claims (1)

【特許請求の範囲】[Claims] 絶縁膜と多結晶シリコン膜とを積層し、該絶縁膜と多結
晶シリコン膜とを同時に開口して電極窓を形成し、該電
極窓を含む前記多結晶シリコン膜上にアルミニウム膜を
被着し、該アルミニウム膜と前記多結晶シリコン膜とを
同時にパターンニングして、前記電極窓に接続したアル
ミニウム配線を形成する工程が含まれてなることを特徴
とする半導体装置の製造方法。
An insulating film and a polycrystalline silicon film are laminated, an electrode window is formed by simultaneously opening the insulating film and the polycrystalline silicon film, and an aluminum film is deposited on the polycrystalline silicon film including the electrode window. A method of manufacturing a semiconductor device, comprising the steps of simultaneously patterning the aluminum film and the polycrystalline silicon film to form an aluminum wiring connected to the electrode window.
JP25396486A 1986-10-24 1986-10-24 Manufacture of semiconductor device Pending JPS63107141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25396486A JPS63107141A (en) 1986-10-24 1986-10-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25396486A JPS63107141A (en) 1986-10-24 1986-10-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63107141A true JPS63107141A (en) 1988-05-12

Family

ID=17258393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25396486A Pending JPS63107141A (en) 1986-10-24 1986-10-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63107141A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007150367A (en) * 1994-12-29 2007-06-14 Stmicroelectronics Inc Constitutional body and method of forming enlarged head of plug used for eliminating enclosure requirement
JP2018085530A (en) * 2017-12-28 2018-05-31 富士電機株式会社 Semiconductor device and semiconductor device manufacturing method
JP2019091912A (en) * 2019-01-28 2019-06-13 富士電機株式会社 Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007150367A (en) * 1994-12-29 2007-06-14 Stmicroelectronics Inc Constitutional body and method of forming enlarged head of plug used for eliminating enclosure requirement
JP2018085530A (en) * 2017-12-28 2018-05-31 富士電機株式会社 Semiconductor device and semiconductor device manufacturing method
JP2019091912A (en) * 2019-01-28 2019-06-13 富士電機株式会社 Semiconductor device

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