JPH02206115A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02206115A
JPH02206115A JP2699589A JP2699589A JPH02206115A JP H02206115 A JPH02206115 A JP H02206115A JP 2699589 A JP2699589 A JP 2699589A JP 2699589 A JP2699589 A JP 2699589A JP H02206115 A JPH02206115 A JP H02206115A
Authority
JP
Japan
Prior art keywords
insulating film
film
hole
semiconductor substrate
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2699589A
Other languages
Japanese (ja)
Inventor
Yasushi Ueda
泰 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2699589A priority Critical patent/JPH02206115A/en
Publication of JPH02206115A publication Critical patent/JPH02206115A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enhance a step coverage of a wiring electrode and a protective film on its upper layer by a method wherein a first insulating film, a second insulating film and a third insulating film whose etching rate is higher than that of the second insulating film are formed as an interlayer insulating film, the third insulating film is etched anisotropically and a through-hole is formed on a conductive layer of a semiconductor substrate. CONSTITUTION:A first insulating film 3 whose stress is low with reference to a semiconductor substrate 1, a second insulating film 4 and a third insulating film 5 whose etching rate with reference to an isotropic etching operation is higher than that of the second insulating film are piled up, as an interlayer insulating film 7, one after another on the semiconductor substrate 1; the third insulating film 5 is etched isotropically by making use of a photoresist pattern 6 as a mask. After that, the second insulating film and the first insulating film 4, 3 are etched anisotropically by a reactive ion etching operation; a through-hole 8 reaching the surface of a conductive layer 2 is formed. Accordingly, an edge part of the through-hole at the third insulating film 5 is formed so as to be inclined. Thereby, when a protective film 10 is formed on the surface of the semiconductor substrate 1, a step coverage of a wiring electrode 9 and the protective film 10 on its upper layer is enhanced.

Description

【発明の詳細な説明】 〔産業上の利用分野] こめ発明は、半導体集積回路等の半導体装置の製造方法
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing semiconductor devices such as semiconductor integrated circuits.

〔従来の技術〕[Conventional technology]

近年、半導体集積回路の亮集積化に伴い、半導体装置に
形成されるスルーホールは、リアクティブイオンエツチ
ングにより異方性に形成されるようになってきている。
In recent years, as semiconductor integrated circuits have become more integrated, through holes formed in semiconductor devices have come to be formed anisotropically by reactive ion etching.

この種の従来の半導体装置の製造方法を第2図に基づい
て説明する。
A conventional method of manufacturing a semiconductor device of this type will be explained with reference to FIG.

この半導体装置の製造工程として、まずシリコン基板1
′に拡散層2′を形成し、この拡散層2′を形成したシ
リコン基板1′上に層間絶縁膜7′を堆積させ、第2図
(a)に示すように、さらに層間絶縁膜7′上にマスク
パターンとなるフォトレジストパターン6を形成する。
In the manufacturing process of this semiconductor device, first a silicon substrate
A diffusion layer 2' is formed on the silicon substrate 1' on which the diffusion layer 2' is formed, and an interlayer insulating film 7' is deposited on the silicon substrate 1', as shown in FIG. 2(a). A photoresist pattern 6 serving as a mask pattern is formed thereon.

つぎに、第2図Φ)に示すように、フォトレジストパタ
ーン6をマスクとしてリアクティブイオンエツチングに
より層間絶縁膜7′を異方性にエツチングし、スルーホ
ール8′を形成する。このとき、眉間絶縁膜7′は、異
方性にエツチングされるため、フォトレジストパターン
6の縁部に沿って垂直方向にエツチングされたスルーホ
ール8′が形成される。そして、第2図(C)に示すよ
うに、フォトレジスト(図示せず)をマスクとした選択
エツチングにより、スルーホール8′にアルミニウム配
線電極9′を形成し、さらにこのアルミニウム配線電極
9′を形成したシリコン基板1′の表面に保護膜10を
形成する。
Next, as shown in FIG. 2 Φ), the interlayer insulating film 7' is anisotropically etched by reactive ion etching using the photoresist pattern 6 as a mask to form a through hole 8'. At this time, the glabellar insulating film 7' is etched anisotropically, so that a through hole 8' is vertically etched along the edge of the photoresist pattern 6. Then, as shown in FIG. 2(C), an aluminum wiring electrode 9' is formed in the through hole 8' by selective etching using a photoresist (not shown) as a mask, and this aluminum wiring electrode 9' is then formed in the through hole 8'. A protective film 10 is formed on the surface of the formed silicon substrate 1'.

〔発明が解決しようとする課題] しかし、この従来の半導体装置の製造方法においては、
スルーホール8′を異方性にエツチングして形成するた
め、スルーホール8′に形成したアルミニウム配線電極
9′およびその上層の保護膜10のステップカバーレー
ジが悪くなり、配線抵抗が増加するなどし、信頼性が低
下するという問題があった。
[Problem to be solved by the invention] However, in this conventional method for manufacturing a semiconductor device,
Since the through hole 8' is formed by anisotropic etching, the step coverage of the aluminum wiring electrode 9' formed in the through hole 8' and the overlying protective film 10 deteriorates, resulting in an increase in wiring resistance. , there was a problem of decreased reliability.

したがって、この発明の目的は、スルーホールに形成さ
れた配線電極およびその上層に形成された保護膜のステ
ップカバーレージの向上を図り、配線抵抗の低減および
信頼性の向上を図ることのできる半導体装置の製造方法
を提供することである。
Therefore, an object of the present invention is to improve the step coverage of the wiring electrode formed in the through hole and the protective film formed on the upper layer of the wiring electrode, thereby reducing the wiring resistance and improving the reliability of a semiconductor device. An object of the present invention is to provide a method for manufacturing.

〔課題を解決するための手段] この発明の半導体装置の製造方法は、表面の一部の領域
に導電層を形成した半導体基板の表面に半導体基板に対
して低ストレスの第1の絶縁膜を形成し、この第1の絶
縁膜の表面に第2の絶縁膜を形成し、さらに第2の絶縁
膜の表面に等方性のエツチングに対して第2の絶縁膜よ
りも高いエツチングレートの第3の絶縁膜を形成して層
間絶縁膜を形成する工程と、第3の絶縁膜上にフォトレ
ジストパターンを形成する工程と、フォトレジストパタ
ーンをマスクとして導電層上の第3の絶縁膜を等方性に
エツチングし、つぎに第2および第1の絶縁膜をリアク
ティブイオンエツチングにより異方性にエツチングして
導電層の表面を露呈しスルーホールを形成する工程と、
スルーホールに配線電極を形成する工程と、配線電極を
形成した半導体基板の表面に保護膜を形成する工程とを
含んでいる。
[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes forming a first insulating film with low stress on the semiconductor substrate on the surface of the semiconductor substrate on which a conductive layer is formed in a part of the surface. A second insulating film is formed on the surface of the first insulating film, and a second insulating film is etched on the surface of the second insulating film at a higher etching rate than the second insulating film for isotropic etching. A step of forming an interlayer insulating film by forming the third insulating film, a step of forming a photoresist pattern on the third insulating film, and a step of forming the third insulating film on the conductive layer using the photoresist pattern as a mask. etching the second and first insulating films anisotropically by reactive ion etching to expose the surface of the conductive layer and form a through hole;
The method includes a step of forming a wiring electrode in the through hole, and a step of forming a protective film on the surface of the semiconductor substrate on which the wiring electrode is formed.

〔作 用〕[For production]

この発明の方法によれば、半導体基板に対して低ストレ
スの第1の絶縁膜と、第2の絶縁膜と、この第2の絶縁
膜よりも等方性のエツチングに対してエツチングレート
の高い第3の絶縁膜とを層間絶縁膜として半導体基板の
表面に順次重ねて形成し、フォトレジストパターンをマ
スクとして第3の絶縁膜を等方性にエツチングするよう
にしたので、第3の絶縁膜がフォトレジストパターンの
第3の絶縁膜側の縁部から水平および垂直方向に等しく
エツチングされ、エツチングにより形成された第3の絶
縁膜の開口は、フォトレジストパターンに形成されたエ
ツチングのための開口幅よりも大きくかつフォトレジス
トパターン側から第2の絶縁膜側に向かって小さくなる
ように傾斜して形成される。このとき、第3の絶縁膜の
下層となる第2の絶縁膜は、第3の絶縁膜よりも等方性
のエツチングに対してエツチングレートが低いためほと
んどエツチングされない。そして、その後リアクティブ
イオンエツチングにより第2および第1の絶縁膜を異方
性にエツチングするため、第2および第1の絶縁膜がフ
ォトレジストパターンの縁部に沿って垂直方向にエツチ
ングされ、導電層の表面に達するスルーホールが形成さ
れる。したがって、第3の絶縁膜のスルーホール縁部が
傾斜して形成されるため、スルーホールに配線電極を形
成し、配線電極を形成した半導体基板の表面に保護膜を
形成したときに、配線電極およびその上層の保護膜のス
テップカバーレージが向上される。
According to the method of the present invention, a first insulating film that has low stress on a semiconductor substrate, a second insulating film, and a second insulating film that has a higher etching rate than the second insulating film for isotropic etching. The third insulating film is formed as an interlayer insulating film on the surface of the semiconductor substrate, and the third insulating film is isotropically etched using the photoresist pattern as a mask. is etched equally horizontally and vertically from the edge of the photoresist pattern on the third insulating film side, and the opening in the third insulating film formed by etching is the same as the opening for etching formed in the photoresist pattern. It is formed to be larger than the width and to be inclined so as to become smaller from the photoresist pattern side toward the second insulating film side. At this time, the second insulating film, which is the lower layer of the third insulating film, is hardly etched because its etching rate is lower than that of the third insulating film with respect to isotropic etching. Then, the second and first insulating films are etched anisotropically by reactive ion etching, so that the second and first insulating films are vertically etched along the edges of the photoresist pattern, making them conductive. Through holes are formed that reach the surface of the layer. Therefore, since the edge of the through hole in the third insulating film is formed at an angle, when a wiring electrode is formed in the through hole and a protective film is formed on the surface of the semiconductor substrate on which the wiring electrode is formed, the wiring electrode And the step coverage of the overlying protective film is improved.

〔実施例〕〔Example〕

この発明の半導体装置の製造方法の一実施例を第1図に
基づいて説明する。
An embodiment of the method for manufacturing a semiconductor device according to the present invention will be described with reference to FIG.

この半導体装置の製造工程は、まず半導体基板となるシ
リコン基板1の表面の一部の領域に導電層となる拡散層
2を形成する。つぎに、第1図(a)に示すように、拡
散層2を形成したシリコン基板1の表面に、シリコン基
板1に対して低ストレスの第1の絶縁膜となる二酸化シ
リコン膜3を形成し、この二酸化シリコン膜3の表面に
第2の絶縁膜となる窒化シリコン膜4を形成する。さら
に窒化シリコン膜4よりも等方性のエツチングに対して
高いエツチングレートの第3の絶縁膜となるホスホ・シ
リケート・グラス膜5(以下PSG膜5と呼ぶ)を窒化
シリコン膜4の表面に形成し、二酸化シリコン膜3.窒
化シリコン膜4およびPSGSbO2なる眉間絶縁膜7
を形成する。つぎに、PSG膜5上にフォトレジストパ
ターン6を形成する。
In the manufacturing process of this semiconductor device, first, a diffusion layer 2, which becomes a conductive layer, is formed in a part of the surface of a silicon substrate 1, which becomes a semiconductor substrate. Next, as shown in FIG. 1(a), on the surface of the silicon substrate 1 on which the diffusion layer 2 has been formed, a silicon dioxide film 3, which becomes a first insulating film with low stress on the silicon substrate 1, is formed. A silicon nitride film 4, which becomes a second insulating film, is formed on the surface of this silicon dioxide film 3. Furthermore, a phosphosilicate glass film 5 (hereinafter referred to as PSG film 5), which serves as a third insulating film with a higher etching rate than the silicon nitride film 4 for isotropic etching, is formed on the surface of the silicon nitride film 4. and silicon dioxide film 3. Silicon nitride film 4 and glabella insulating film 7 made of PSGSbO2
form. Next, a photoresist pattern 6 is formed on the PSG film 5.

そして、第1図(b)に示すように、フォトレジストパ
ターン6をマスクとして、バッフアートぶつ酸を用いた
ウェットエツチング等によりPSGSbO2方性にエツ
チングする。このとき、PSGSbO2等方性のエツチ
ングによりフォトレジストパターン6のPSG膜5側の
縁部から水平および垂直方向に等しくエツチングされる
ため、エツチングにより形成されたPSGSbO2口は
、フォトレジストパターン6に形成された開口幅よりも
大きくかつフォトレジストパターン6側から窒化シリコ
ン膜4側に向かって小さくなるように傾斜して形成され
る。また、PSGSbO2層となる窒化シリコン膜4は
、PSGSbO2も等方性のエツチングに対してエツチ
ングレートが低いためほとんどエツチングされない。そ
して、第1図(C)に示すように、窒化シリコン膜4お
よび二酸化シリコン膜3を、バッチ式ドライエツチング
装置等を用いてリアクティブイオンエツチングにより異
方性にエツチングして拡散層2の表面を露呈させ、スル
ーホール8を形成する。このとき、窒化シリコン膜4お
よび二酸化シリコン膜3は異方性にエツチングされるた
め、フォトレジストパターン6の縁部に沿って垂直方向
にエツチングされ、拡散層2の表面に達するスルーホー
ル8が形成される。この場合、圧力を30〜100mT
orr、出力を1000〜1350Wとし、反応ガスを
CHF310□としてリアクティブイオンエツチングを
行った。
Then, as shown in FIG. 1(b), using the photoresist pattern 6 as a mask, etching is performed in the PSGSbO2 direction by wet etching using buffered butic acid. At this time, since PSGSbO2 isotropically etched from the edge of the photoresist pattern 6 on the PSG film 5 side in both the horizontal and vertical directions, the PSGSbO2 opening formed by etching is not formed in the photoresist pattern 6. The opening width is larger than the width of the opening, and the opening width is inclined so as to become smaller from the photoresist pattern 6 side toward the silicon nitride film 4 side. Further, the silicon nitride film 4 which becomes the PSGSbO2 layer is hardly etched because PSGSbO2 also has a low etching rate compared to isotropic etching. Then, as shown in FIG. 1(C), the silicon nitride film 4 and the silicon dioxide film 3 are anisotropically etched by reactive ion etching using a batch type dry etching device or the like, to thereby remove the surface of the diffusion layer 2. is exposed to form a through hole 8. At this time, since the silicon nitride film 4 and the silicon dioxide film 3 are etched anisotropically, they are etched vertically along the edge of the photoresist pattern 6, forming a through hole 8 that reaches the surface of the diffusion layer 2. be done. In this case, the pressure should be 30 to 100 mT.
Reactive ion etching was performed with an output of 1000 to 1350 W and a reaction gas of CHF310□.

つぎに、第1図(d)に示すように、スルーホール8に
フォトレジスト(図示せず)をマスクとじた選択エツチ
ングによりアルミニウム等からなる配線電極9を形成し
、この配線電極9を形成したシリコン基板lの表面に保
護膜10を形成する。このとき、PSGSbO2ルーホ
ール縁部が傾斜して形成されているため、スルーホール
8に配線電極9を形成し、配線電極9を形成したシリコ
ン基板1の表面に保護膜10を形成したときに、配線電
極9および保護膜10のステップカバーレージを向上す
ることができ、配線抵抗の低減および信頼性の向上を図
ることができる。
Next, as shown in FIG. 1(d), a wiring electrode 9 made of aluminum or the like was formed in the through hole 8 by selective etching using a photoresist (not shown) as a mask. A protective film 10 is formed on the surface of a silicon substrate l. At this time, since the edge of the PSGSbO2 through hole is formed with an inclination, when the wiring electrode 9 is formed in the through hole 8 and the protective film 10 is formed on the surface of the silicon substrate 1 on which the wiring electrode 9 is formed, the wiring Step coverage of the electrode 9 and the protective film 10 can be improved, wiring resistance can be reduced, and reliability can be improved.

また、この実施例においては、眉間絶縁膜7の中層部と
なる第2の絶縁膜としてウェットエツチングではほとん
どエツチングされない窒化シリコン膜4を用いたので、
PSGSbO2ェットエツチングを用いてオーバーエツ
チングすることにより、簡単にPSGSbO2口を傾斜
させて形成することができる。
Furthermore, in this embodiment, the silicon nitride film 4, which is hardly etched by wet etching, was used as the second insulating film that forms the middle layer of the glabella insulating film 7.
By over-etching using PSGSbO2 jet etching, it is possible to easily form the PSGSbO2 opening at an angle.

なお、この実施例においては、導電層として拡散層2に
ついて説明したが、多結晶シリコンゲート配線等からな
る導電層としてもよい。
In this embodiment, the diffusion layer 2 has been described as a conductive layer, but a conductive layer made of polycrystalline silicon gate wiring or the like may be used.

〔発明の効果〕〔Effect of the invention〕

この発明の半導体装置の製造方法によれば、半導体基板
に対して低ストレスの第1の絶縁膜と、第2の絶縁膜と
、この第2の絶縁膜よりも等方性のエツチングに対して
エツチングレートの高い第3の絶縁膜とを層間絶縁膜と
して半導体基板の表面に順次重ねて形成し、フォトレジ
ストパターンをマスクとして第3の絶縁膜を等方性にエ
ツチングし、その後節2および第1の絶縁膜をリアクテ
ィブイオンエツチングにより異方性にエツチングして半
導体基板に形成された導電層上にスルーホールを形成す
るようにしたので、第3の絶縁膜のスルーホール縁部を
傾斜させて形成することができ、スルーホールに形成し
た配線電極およびその上層の保護膜のステップカバーレ
ージの向上を図ることができ、配線抵抗の低減および信
転性の向上を図ることができる。
According to the method of manufacturing a semiconductor device of the present invention, the first insulating film and the second insulating film, which have low stress on the semiconductor substrate, and the second insulating film are etched more isotropically than the second insulating film. A third insulating film with a high etching rate is sequentially formed as an interlayer insulating film on the surface of the semiconductor substrate, and the third insulating film is isotropically etched using the photoresist pattern as a mask. Since the first insulating film was etched anisotropically by reactive ion etching to form a through hole on the conductive layer formed on the semiconductor substrate, the edge of the through hole in the third insulating film was inclined. It is possible to improve the step coverage of the wiring electrode formed in the through hole and the overlying protective film, thereby reducing wiring resistance and improving reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(d)はこの発明の一実施例の工程を示
す断面図、第2図(a)〜(C)は従来の半導体装置の
製造工程を示す断面図である。 1・・・半導体基板(シリコン基板)、2・・・導電層
(拡散層)、3・・・第1の絶縁膜(二酸化シリコン膜
)、4・・・第2の絶縁膜(窒化シリコン膜)、5・・
・第3の絶縁膜(ホスホ・シリケート・グラス(PSG
) 膜) 、6・・・フォトレジストパターン、7・・
・層間絶縁膜、8・・・スルーホール、9・・・配線電
極、10・・・保護膜
FIGS. 1(a) to 1(d) are cross-sectional views showing the steps of an embodiment of the present invention, and FIGS. 2(a) to (C) are cross-sectional views showing the conventional manufacturing steps of a semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate (silicon substrate), 2... Conductive layer (diffusion layer), 3... First insulating film (silicon dioxide film), 4... Second insulating film (silicon nitride film) ), 5...
・Third insulating film (phosphosilicate glass (PSG)
) film), 6... photoresist pattern, 7...
・Interlayer insulating film, 8... Through hole, 9... Wiring electrode, 10... Protective film

Claims (1)

【特許請求の範囲】[Claims] 表面の一部の領域に導電層を形成した半導体基板の表面
に前記半導体基板に対して低ストレスの第1の絶縁膜を
形成し、この第1の絶縁膜の表面に第2の絶縁膜を形成
し、さらに前記第2の絶縁膜の表面に等方性のエッチン
グに対して前記第2の絶縁膜よりも高いエッチングレー
トの第3の絶縁膜を形成して層間絶縁膜を形成する工程
と、前記第3の絶縁膜上にフォトレジストパターンを形
成する工程と、前記フォトレジストパターンをマスクと
して前記導電層上の前記第3の絶縁膜を等方性にエッチ
ングし、つぎに前記第2および第1の絶縁膜をリアクテ
ィブイオンエッチングにより異方性にエッチングして前
記導電層の表面を露呈しスルーホールを形成する工程と
、前記スルーホールに配線電極を形成する工程と、前記
配線電極を形成した前記半導体基板の表面に保護膜を形
成する工程とを含む半導体装置の製造方法。
A first insulating film having low stress with respect to the semiconductor substrate is formed on the surface of a semiconductor substrate having a conductive layer formed on a part of the surface, and a second insulating film is formed on the surface of the first insulating film. forming an interlayer insulating film by forming a third insulating film having a higher etching rate than the second insulating film with respect to isotropic etching on the surface of the second insulating film; , forming a photoresist pattern on the third insulating film; isotropically etching the third insulating film on the conductive layer using the photoresist pattern as a mask; etching the first insulating film anisotropically by reactive ion etching to expose the surface of the conductive layer and forming a through hole; forming a wiring electrode in the through hole; and forming a wiring electrode in the through hole. A method for manufacturing a semiconductor device, comprising the step of forming a protective film on the surface of the formed semiconductor substrate.
JP2699589A 1989-02-06 1989-02-06 Manufacture of semiconductor device Pending JPH02206115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2699589A JPH02206115A (en) 1989-02-06 1989-02-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2699589A JPH02206115A (en) 1989-02-06 1989-02-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02206115A true JPH02206115A (en) 1990-08-15

Family

ID=12208742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2699589A Pending JPH02206115A (en) 1989-02-06 1989-02-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02206115A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04171814A (en) * 1990-11-05 1992-06-19 Nec Yamagata Ltd Manufacture of semiconductor device
JP2010238988A (en) * 2009-03-31 2010-10-21 Oki Semiconductor Co Ltd Method of manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04171814A (en) * 1990-11-05 1992-06-19 Nec Yamagata Ltd Manufacture of semiconductor device
JP2010238988A (en) * 2009-03-31 2010-10-21 Oki Semiconductor Co Ltd Method of manufacturing semiconductor device

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