JPH01248537A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce generation of a defect of a product due to breaking of a lower wiring so as to improve an yield and reliability by forming a PSG film on the lower layer wiring arranged on an insulating film provided on a semiconductor substrate being divided in the width direction and mutually neighboring through insulating film while flattening the surface by the anisotropic etching. CONSTITUTION:The Al wirings 3a, 3b and 4 are provided on an insulating film 2 provided on a semiconductor substrate 1 and an interlayer insulating film 5 is formed on the surfaces including the Al wirings 3a, 3b and 4; thereafter, a PSG film is deposited by a spin coating method in order to flatten the surface. Then, the Al wirings 3a and 3b are divided in two in the width direction while being arranged mutually neighboring in order to reduce the wiring width. Next, the PSG film 6 located on the interlayer insulating film 5 on the Al wirings 3a, 3b and 4 is removed by etching, while the whole surfaces are etch-baked by an RIE method. And the etching is performed until the upper-most surface of the interlayer insulating film 5 is slightly exposed. Since excessive etching is avoided, the surfaces can be flattened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having multilayer metal wiring.

[Conventional technology]

Multilayer wiring, especially metal multilayer wiring, has low electrical resistance and is an effective method for increasing the speed of semiconductor integrated circuits. However, since the metal wiring is thick, the problem was how to reduce the level difference.

FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a conventional semiconductor integrated circuit.

As shown in FIG. 2(a), aluminum wires 3C and 4 are selectively formed on the insulating film 2 provided on the semiconductor substrate 1, thereby forming the aluminum wires 3c.

A glabellar insulating film 5 is formed on the surface including 4.

Next, as shown in FIG. 2(b), a silicate glass film (hereinafter referred to as PS
G film) 6 is provided to smooth the surface.

Next, as shown in FIG. 2(c), the PSG film 6 is etched back by reactive ion etching (hereinafter referred to as RIE) to remove the PSGSeO2 present on at least the glabella insulating film 5 above the aluminum wiring 3C94. Remove completely.

Next, as shown in FIG. 2(d), the aluminum wiring 3
A contact hole is formed in the glabella insulating film 6 above the contact hole, an aluminum layer is deposited on the surface including the contact hole, and this is selectively etched to form the aluminum wiring 3.
An aluminum wiring 7 connected to c is formed.

Here, if PSGM 6 remains on the glabellar insulating film 5 on the aluminum wiring 3C, PSGSeO2 is released on the side surface of the contact hole, gas is released from there during the formation of the aluminum layer, and the aluminum wiring 7 of the contact hole There is a problem in that it adversely affects the electrical characteristics of the Furthermore, excessive etch-back is required to completely remove the PSGl 16 in the contact hole portion, which poses a problem in that smoothing of the surface is inhibited.

[Problem to be solved by the invention]

The above-described conventional semiconductor integrated circuit has a drawback in that flattening cannot be achieved as a result of excessively etching back the surface smoothed by the coating film. In other words, if the PSG film remains on the interlayer insulating film on the lower aluminum wiring,
Gas is generated from the sides of the contact hole in a vacuum during the deposition of the upper aluminum layer. This is because the PSG film has extremely high hygroscopicity, and water is released from the PSG film. This gas causes a problem in that the conductivity between the lower layer aluminum wiring and the upper layer aluminum wiring deteriorates. Further, in order to prevent the PSG film from remaining, excessive etchback is necessary, and as a result, the flatness effect is lost.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes a lower layer wiring that is divided in the width direction and arranged close to each other in order to reduce the wiring width on an insulating film provided on a semiconductor substrate, and the lower layer wiring. A first insulating film provided on the surface, and a second insulating film formed on the first insulating film by spin coating and etched back by anisotropic etching to smooth the surface. have.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1(c) are cross-sectional views of a semiconductor chip shown in order of steps for explaining an embodiment of the present invention.

As shown in FIG. 1(a), an aluminum wiring 3a is formed on an insulating film 2 provided on a semiconductor substrate 1.

3b and 4 are selectively provided, and the aluminum wiring 3
After forming the glabellar insulating film 5 on the surface including a, 3b, and 4,
The surface is flattened with PSGSeO2 by the spin coating method in the same manner as in the conventional example.

Here, the aluminum wirings 3a and 3b are divided into two in the width direction and arranged close to each other in order to reduce the wiring width. This was done in order to thin the PSGSeO2 layer provided on the glabellar insulating film 5 on the aluminum wirings 3a, 3b. That is, it was discovered that the thickness of PSGSeO2 provided through an interlayer insulating film changes with the width of the lower wiring, and this is utilized.

As the width of the lower layer wiring becomes narrower, the thickness of the PSG film on the step becomes thinner, and as the width of the wiring becomes wider, the thickness of the PSG film becomes thicker. Therefore, by dividing the lower layer wiring and narrowing the wiring width, the thickness of the PSG film on the step can be reduced.

Next, as shown in FIG. 1(b), the entire surface is etched back by the RIB method to remove PSGSeO2 existing on the glabellar insulating film 5 on the aluminum wirings 3a, 3b, and 4. At this time, etching is carried out until the uppermost surface of the interlayer insulating film 5 is just exposed, but a slanted surface can be obtained to flatten the surface to avoid excessive etching. Next, contact holes are formed by selectively etching the glabella insulating film 5 on the aluminum wirings 3a and 3b, an aluminum layer is deposited on the surface including the contact holes, and this is selectively etched to form contact holes. An aluminum wiring 7 is formed to connect to the aluminum wirings 3a and 3b of the holes.

[Effects of the Invention] As explained above, the present invention completely removes the BSG film remaining in the glabella insulating film in order to reduce the thickness of the PSG film provided on the lower wiring via the interlayer insulating film. It is no longer necessary to perform excessive etch-back to improve the surface of the interlayer insulating film, and the flatness of the surface of the interlayer insulating film can be improved, thereby reducing the occurrence of product defects due to cuts in the underlying wiring. This has the effect of improving the reliability of the semiconductor device.

[Brief explanation of the drawing]

1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a manufacturing method according to an embodiment of the present invention;
FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a conventional method of manufacturing a semiconductor integrated circuit. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3a, 3b. 3C24...Aluminum wiring, 5...Interlayer insulating film, 6...PSG film, 7...Aluminum wiring.

Claims (1)

[Claims] A lower layer wiring that is divided in the width direction and arranged close to each other in order to reduce the wiring width on an insulating film provided on a semiconductor substrate, and a first insulator provided on a surface including the lower layer wiring. and a second insulating film formed on the first insulating film by a spin coating method and etched back by anisotropic etching to smooth the surface. circuit.