JPH04348054A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an interconnection pattern in which a void and a slit-shaped defect are not produced and in which a disconnection is not caused. CONSTITUTION:A substratum insulating film is formed on a semiconductor substrate via a lower-layer interconnection 5; grooves 13 in a prescribed pattern are formed at definite intervals in the insulating film so as not come into contact with the lower-layer interconnection 5; after that, an interconnection layer is formed by using a chemical vapor deposition method, a sputtering method, an ion cluster beam method or the like; the interconnection layer is worked to a prescribed pattern; an interconnection pattern 3 which is provided with a plurality of grooves 13 at definite intervals at the lower part is formed. It is possible to relax a stress from an insulating film applied onto the interconnection pattern 3 or from an interlayer insulating film formed at the upper part of the interconnection pattern 3, to relax the stress of the interconnection pattern itself and to restrain a stress migration.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More specifically, the present invention relates to a method for forming wiring materials in semiconductor devices such as MOS type LSIs.

0002

2. Description of the Related Art As shown in FIG. 7, a conventional semiconductor device is constructed on a silicon substrate 1 having a semiconductor element (not shown) including a gate electrode, an impurity diffusion layer, etc., and is provided with contacts leading to the gate electrode and the impurity diffusion layer. An insulating film (silicon oxide film) 12 having a hole (not shown) is formed, an Al-based alloy layer is laminated thereon to fill the contact hole, and the Al
The Al-based alloy layer is etched into a predetermined pattern as shown in FIG. 8 to form Al-based alloy wiring 3.

0003

[Problems to be Solved by the Invention] In the Al-based alloy wiring 3 formed by the conventional technique, there is a problem of stress migration, that is, after the formation of the Al-based alloy film 3, a protective film (silicon oxide film, Due to the stress exerted by the silicon nitride film (composed of a silicon nitride film or a laminated film of these films), or the residual stress of the Al-based alloy film itself, metal atoms move, resulting in voids and slit-like defects. There is a problem that this occurs, leading to disconnection. In particular, the above-mentioned defects are noticeable in long wiring lines. In addition, in a multilayer wiring structure in which a wiring film is formed, an insulating film is laminated, and a wiring film is further formed on the upper layer using the same procedure, the stress applied to the lower wiring film is greater than that of the upper layer, so disconnections occur. There is a risk that it will be encouraged. This invention was made to solve the above problems, and
It is an object of the present invention to provide a method for manufacturing a semiconductor device that can form an Al-based alloy wiring layer that does not generate defects such as voids or slits and does not cause disconnection.

0004

[Means for Solving the Problems] The present invention provides a method (i ) Forming a plurality of grooves at arbitrary intervals on the underlying insulating film in the wiring area where wiring is intended; (ii)
In this method of manufacturing a semiconductor device, a wiring layer is laminated on the entire surface of the underlying insulating film including these grooves, and then a wiring pattern is formed in the wiring region so as to cover the grooves. In this invention, a wiring film is formed on a semiconductor substrate via an underlying insulating film using a chemical vapor deposition method (CVD method), a sputtering method, an ion cluster beam method, or the like. The semiconductor substrate can be made of, for example, Si, GaAs, GaP, InP, etc., and usually a silicon substrate can be used. The underlying insulating film is, for example, silicon oxide, B
It can be constructed using PSG (glass containing boron and phosphorus), PSG (glass containing phosphorus), silicon nitride, tantalum oxide, or the like. In this invention, the wiring layer is A
l-based alloy wiring is preferable, and Al-Si layer or Al-Si-
Examples include a Cu layer or an Al-Si-Pd layer. However, in the present invention, a similar low melting point metal layer may be used as the wiring layer in addition to the Al-based alloy layer. Of course, a high melting point metal layer such as W or Cu can generally be used as a wiring layer, but since these high melting point metal wirings are inherently less affected by stress migration, there is no point in applying the present invention. After forming a plurality of via holes as grooves in a predetermined pattern on the insulating film, an Al-based alloy film is laminated on the entire surface of the insulating film including the via holes to cover the via holes. Al-based alloy wiring is formed by processing it into a predetermined pattern. The above-mentioned processing can usually be performed by a known photolithography method. At this time, as shown in FIG. 5, the underlying wiring 5 (for example,
In a single layer wiring structure in a MOS type semiconductor device, this is a gate electrode layer or a source/drain, or in a multilayer wiring structure, it is an Al-based alloy wiring formed below with an underlying insulating film interposed therebetween. ) and the Al-based alloy wiring (wiring layer) 3.
For example, the BPSG film (underlying insulating film) 2
It is preferable that the step of forming the groove 13 (see FIG. 4) is performed by a known method before or after the step of forming the groove 13 (see FIG. 4). Further, as shown in FIGS. 4 and 2, the method of forming the groove 13 in the underlying insulating film 2 is also performed using ordinary photolithography technology and etching technology. In this invention, the groove is of course formed in the underlying insulating film of the Al-based alloy wiring as a single-layer wiring, but in a multilayer wiring structure in which multiple wiring layers are stacked, it is necessary to Grooves may be provided only in the underlying insulating film of the layer, or grooves may be provided in each of the underlying insulating layers of the wiring layers present in all wiring layers. In short, the present invention may be appropriately applied to the underlying insulating layer in the wiring where disconnection can be expected. In this invention, forming a plurality of grooves at arbitrary intervals means that the groove intervals may be determined arbitrarily, and the grooves on the same wiring may be spaced at different intervals or evenly spaced. Further, the present invention is more effective when the patterned wiring is particularly long. Furthermore, as shown in FIG.
When laminating the wiring layer 3 by providing the above-mentioned well-known method,
That is, the wiring layer is laminated inside the trench along the inner wall 13a using the CVD method, sputtering method, or ion cluster beam method, but in order to ensure a photo margin, the wiring layer is 3 is preferably formed to have an overlapping portion 33 on the groove. That is, in general, as shown in FIGS. 5 and 6, the via hole 2
It is a well-known fact that such an overlapping portion 53 is provided for the same purpose when forming 3. Of course, in this invention, as shown in FIG. 3, an overlap part 43 similar to the overlap part 53 is formed in the via hole part 23 for connecting the lower layer wiring 5 and the upper layer wiring 3, and the groove part 13 A feature of the present invention is that the overlapping portion 33 is also formed at both ends. As a result, even if the thin wiring portion 3a of the inner wall 13a shown in FIG.
This structure prevents wire breakage. In the present invention, a semiconductor device can be manufactured by appropriately forming an element, an insulating layer, a protective film, etc. on the semiconductor substrate on which the Al-based alloy layer is formed.

[0005]

[Effect] The long wiring pattern (Al-based alloy wiring) is exposed to stress from the protective film attached thereon or the interlayer insulating film formed above the wiring pattern, as well as stress from the wiring pattern itself. To prevent the movement of metal atoms due to stress and the generation of voids and slit-like defects, which lead to disconnection, it is necessary to provide grooves at appropriate intervals in the wiring area of the underlying insulating film for long wiring patterns that are intended to be formed. Accordingly, the stress applied to the wiring pattern can be alleviated.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on an embodiment of a multilayer wiring structure shown in the drawings. This invention is not limited thereby. As shown in FIG. 1, a BPSG film 2 is formed on a silicon substrate 1. Although not shown in FIG. 1, there is already a lower layer wiring 5 directly under the BPSG film 2.
is formed (see Figure 3). Grooves 13 are formed in the film 2 in a predetermined pattern using a known method. An Al-based alloy film (not shown) is formed thereon using a known method and processed into a predetermined shape as shown in FIGS.
form. At this time, since an overlap portion 33 is provided in the trench to ensure a photo margin, disconnection of the wiring within the trench does not pose a problem. In the wiring 3 (see FIG. 3) formed as described above, the stress of the protective film or the upper layer Al-based alloy film itself, which is subsequently applied on the wiring, is relaxed, stress migration can be suppressed, and the highly reliable Al-based Alloy wiring 3 can be formed.

[0007]

[Effects of the Invention] According to the present invention, the stress applied to the Al-based alloy wiring can be alleviated by forming a plurality of grooves in the wiring area of the underlying insulating layer, and as a result, stress migration can be suppressed. This has the effect of making it possible to obtain highly reliable Al-based alloy wiring that does not cause disconnection defects.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the first step of the manufacturing process in an embodiment of the present invention.

FIG. 2 is a diagram showing the second step of the manufacturing process in the above embodiment.

FIG. 3 is a configuration explanatory diagram showing pattern wiring in the above embodiment.

FIG. 4 is a configuration explanatory diagram for explaining the formation of grooves in the above embodiment.

FIG. 5 is a configuration explanatory diagram for explaining a normal via hole.

FIG. 6 is a configuration explanatory diagram showing wiring in a conventional example.

FIG. 7 is a diagram showing the first step of a manufacturing process in a conventional example.

FIG. 8 is a diagram showing the second step of the manufacturing process in the conventional example.

[Explanation of symbols]

1 Silicon substrate 2 BPSG film (underlying insulating film) 3 Al
Alloy wiring (wiring pattern) 5 Lower layer wiring 13 Groove

Claims (1)

[Claims] [Claim 1] When forming a single-layer wiring or a multilayer wiring that is electrically connected to a semiconductor element through an underlying insulating film on a semiconductor substrate having a semiconductor element, (i) a wiring area where the wiring is intended; (ii) After laminating a wiring layer over the entire surface of the underlying insulating film including these grooves, a wiring pattern is formed in the wiring area so as to cover the grooves. A method of manufacturing a semiconductor device formed by forming a semiconductor device.