JPH08222627A - Connecting method for multilayer interconnection - Google Patents

Abstract

PURPOSE: To prevent the contact between wiring patterns and to alleviate the surface step by forming a contact hole at an intersection between a substrate side wiring layer and a front layer, side wiring layer at an interlayer insulating film, and forming a stress dispersing hole at the position disposed on the substrate side wiring layer. CONSTITUTION: A substrate side wiring layer 1 in a laminated layer structure on a semiconductor substrate is electrically connected to a front surface layer side wiring layer 2. In this case, the layer 1 is deposited, the layer 1 is then etched to form a pattern, and then an interlayer insulating layer 3 is deposited on the layer 1. Then, a contact hole 4 is formed at an intersection between the layer 1 and the layer 2 at the layer 3, and a stress dispersing hole 5 is formed at the position disposed on the layer 1. Thereafter, the layer 2 is deposited on the film 3 formed with the holes 4 and 5, and the layer 2 is etched to form a pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for connecting multi-layer wirings, and more particularly to a technique effectively applied to connection of multi-layer wirings for electrically connecting circuit elements formed on a semiconductor wafer.

[0002]

2. Description of the Related Art In today's semiconductor integrated circuit devices,
Due to the demand for finer wiring and higher current density with higher integration and higher speed of devices, the aspect ratio of wiring has been remarkably increased. On the other hand, multi-layered wiring is an even more important technology because it substantially reduces the wiring area to achieve high device integration, shortens the average wiring length, and suppresses the delay in operating speed due to wiring resistance. Has become.

Under such circumstances, as a technique for electrically connecting two wiring layers in a laminated structure formed on a semiconductor wafer, for example, "LSI Handbook" (Showa 59, published by Ohmsha Co., Ltd.) Issued on November 30th), P280 to P281, contact holes should be formed in the interlayer insulating film formed on the lower wiring layer (substrate side wiring layer), and the contact holes should be filled. There is known a technique of forming an upper wiring layer (surface wiring layer) and making contact with the lower wiring layer.

[0004]

However, according to the technique described above, when the wiring width is miniaturized to, for example, about 1.5 μm, the internal stress of the interlayer insulating film and the heat in the process of forming the wiring layer lower the wiring. The stress applied to the side wiring layer becomes large. As a result, the inventors of the present invention have examined the result of FIG.
In the contact hole 54 formed at the intersection of the lower wiring layer 51 and the upper wiring layer 52 shown in FIG.
The phenomenon that it penetrates into the inside occurs. Then, as shown in FIG. 9, when the upper wiring layer 52 is deposited, the contact hole 5 of the interlayer insulating film 53 in the upper wiring layer 52 is formed.
The part of 4 will be greatly excited.

When the upper wiring layer 52 rises,
There is a problem in that the formed wiring patterns are brought into contact with each other by a subsequent heat treatment or the like to cause poor conduction.

Further, such swelling causes a large surface step, which adversely affects the quality of lithography and etching.

Therefore, an object of the present invention is to provide a connecting technique of multilayer wirings which can prevent the mutual contact of wiring patterns due to the bulging of the surface side wiring layer.

Another object of the present invention is to provide a technique for connecting multi-layered wiring, which can alleviate the surface step.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The typical ones of the inventions disclosed in the present application will be outlined below.

That is, the method for connecting multilayer wirings according to the present invention electrically connects the wiring layer on the substrate side and the wiring layer on the surface layer in the laminated structure formed on the semiconductor substrate. And a step of etching the substrate side wiring layer to form a pattern, a step of depositing an interlayer insulating film on the substrate side wiring layer, and a step of forming a substrate side wiring layer with respect to the interlayer insulating film. Forming a contact hole at the intersection with the surface side wiring layer and forming a stress distribution hole at a position located on the substrate side wiring layer, and on the interlayer insulating film where the contact hole and the stress distribution hole are formed. The method includes a step of depositing a surface wiring layer and a step of etching the surface wiring layer to form a pattern.

In this case, the contact hole and the stress distribution hole can be formed at equal intervals. Further, it is desirable that the contact hole and the stress distribution hole are formed at an interval of about 50 μm or less.

In the above case, the stress distribution hole may be formed near the contact hole.

[0014]

According to the above-mentioned means, the protrusion of the wiring layer on the substrate side due to the internal stress of the interlayer insulating film, the stress of the heat treatment process, etc. can be divided into the contact hole and the stress distribution hole, and the wiring on the surface layer side. The swelling of the contact hole portion when the layer is deposited does not occur.

Therefore, it is possible to prevent the defective conduction due to the mutual contact of the wiring patterns of the formed surface wiring layer.

Further, since the swelling at the portion of the contact hole is eliminated and the surface step is alleviated, it becomes possible to finish the subsequent processing such as lithography and etching in a good state.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view showing a lower wiring layer and an upper wiring layer which are connected by a method of connecting multi-layered wiring according to an embodiment of the present invention, and FIG. 2 is a main part of FIG. Cross section,
FIG. 3 is a flow chart showing a method of connecting the multi-layer wiring of FIG.

As shown in FIG. 1, the multilayer wiring connection technique according to the present embodiment employs a lower wiring layer (substrate-side wiring layer) made of aluminum formed on a semiconductor substrate (not shown) made of, for example, single crystal silicon. ) 1 and an upper wiring layer (surface layer wiring layer) 2 also made of aluminum, are electrically connected to each other. A contact hole 4 is formed at a position where both of the interlayer insulating films 3 intersect, and a lower wiring is formed. A stress dispersion hole 5 is formed in the portion located on the layer 1.

According to the study by the present inventors, the above-mentioned phenomenon of the lower wiring layer 1 penetrating into the contact hole 4 hardly occurs when the wiring length of the lower wiring layer 1 is about 50 μm.
It became clear that it became remarkable when it became 100 μm or more. Therefore, in the present embodiment, the hole spacing between the contact hole 4 and the stress distribution hole 5 is set to W ₁ = W ₂ = W ₃ = 50 μm. Therefore, the wiring length of the lower wiring layer 1 is about 150 μm and the line width is, for example, 1.5 μm. In addition, including the following cases, the numerical values of the wiring length and the line width in this embodiment are merely examples, and the present invention is not limited to these. In addition, although it is not always necessary to form the holes at regular intervals of 50 μm in this way, since penetration is noticeable at 100 μm or more, the hole interval is 1
It is desirable that the thickness is 00 μm or less, preferably 50 μm or less.

FIG. 2 shows a sectional view of the contact hole 4 and the stress distribution hole 5 formed.

As shown in the figure, for example, a lower wiring layer 1 is formed on a SiO ₂ film 6, and a contact hole 4 and a stress distribution hole 5 are formed in an interlayer insulating film 3 formed on the lower wiring layer 1. Has been established. The portions corresponding to the holes 4 and 5 of the lower wiring layer 1 are the holes 4 and 5, respectively.
The line width is wide corresponding to the hole diameter of No. 5. The upper wiring layer 2 is formed on the interlayer insulating film 3. The upper wiring layer 2 is deposited so as to penetrate into the contact hole 4, and contacts the lower wiring layer 1 for electrical connection.

A method of connecting such multilayer wiring will be described with reference to FIGS.

First, for example, CVD (Chemical Vapor Deposition)
The lower wiring layer 1 made of aluminum is deposited by the (position) method (first step S ₁ ), a resist (not shown) is applied thereon, and the wiring pattern of the lower wiring layer 1 is transferred by a photomask and etched. A pattern is formed on the lower wiring layer 1 by etching by the technique (second step S
₂ ). The lower wiring layer 1 and the upper wiring layer 2 are not limited to aluminum, and various other various materials such as polycrystalline silicon, tungsten, titanium / tungsten, titanium nitride, titanium, chromium, molybdenum, etc. can be used. A conductive material can be used.

Next, the interlayer insulating film 3 is deposited (third step S ₃ ). Here, in the present embodiment, as the interlayer insulating film 3, as shown in FIG. 2, first, a first PSG (Phospho-Silicate Glass) film 3a doped with P (phosphorus) is deposited by a CVD method, After this is annealed and flattened, an SOG (Spin On Glass) film 3b is applied, and a second PSG film 3c is deposited and flattened. The interlayer insulating film 3 need not be formed in three layers in this way, and may be one layer, two layers, or four or more layers. In addition to the PSG films 3a and 3c, for example, BPSG (B
oro-Phospho-Silicate Glass) film, BSG (Boro-Silica)
te Glass) film, ASG (Arseno-Silicate Glass) film, T
An EOS (Tetra-Ethyl-Ortho-Silicate) film or the like can be applied to the interlayer insulating film 3. A glass film not doped with impurities such as P and B (boron) may be used.

Then, a contact hole 4 and a stress distribution hole 5 are formed in the interlayer insulating film 3 (fourth step S ₄ ). That is, the contact hole 4 is provided at a location where the lower wiring layer 1 and the upper wiring layer 2 are electrically connected, and the stress distribution holes are provided at a location above the lower wiring layer 1 at regular intervals of 50 μm. 5 is formed. Each of the holes 4 and 5 is, for example, in the same manner as the pattern formation of the lower wiring layer 1 described above,
It is performed by a photo etching technique.

After forming the holes 4 and 5, the upper wiring layer 2 is deposited on the interlayer insulating film 3 by, for example, the CVD method (fifth step S ₅ ), and a pattern is formed in the same manner as the lower wiring layer 1. Is performed (sixth step S ₆ ).

By connecting the lower wiring layer 1 and the upper wiring layer 2 in this way, as shown in FIG. 2, it is applied to the lower wiring layer 1 by the internal stress of the interlayer insulating film 3 and the heat treatment process. Even if the stress increases, the protrusion of the lower wiring layer 1 that cannot withstand this stress is distributed to the contact hole 4 and the stress distribution hole 5. As a result, even if the upper wiring layer 2 is deposited, the phenomenon that the portion of the contact hole 4 is greatly raised does not occur.

Therefore, it is possible to prevent in advance the conduction failure that the wiring patterns of the upper wiring layer 2 formed by the raised portions of the contact holes 4 contact each other.

Further, since the swelling at the portion of the contact hole 4 is eliminated and the surface step is alleviated, the subsequent processes such as lithography and etching can be finished in good condition.

(Embodiment 2) FIG. 4 is a plan view showing a lower wiring layer and an upper wiring layer which are connected by a method of connecting multi-layer wiring according to another embodiment of the present invention. It should be noted that, in the following, members common to those in the above-described first embodiment will be described with common reference numerals.

As shown in the figure, in this embodiment, the stress distribution hole 5 is formed near the contact hole 4. In this way, the lower wiring layer (board-side wiring layer) 11
If the wiring length is about 100 μm, the stress distribution hole 5 may be formed near the contact hole 4 as in the present embodiment. In addition, including the following third and subsequent embodiments, the multilayer wiring is formed by the method shown in the flowchart of FIG.

Also according to the method of connecting the laminated wirings shown in this embodiment, the protrusion of the lower wiring layer 11 causes the contact hole 4
And the stress distribution holes 5 are dispersed, and the portion of the contact hole 4 in the upper wiring layer (surface layer wiring layer) 12 does not rise significantly.

Therefore, the conduction failure in which the wiring patterns of the upper wiring layer 12 are in contact with each other is prevented, and the surface step is reduced.

(Embodiment 3) FIG. 5 is a plan view showing a lower wiring layer and an upper wiring layer connected by a multi-layer wiring connecting method according to another embodiment of the present invention.

As shown in the drawing, in the present embodiment, unlike the above-described first and second embodiments, the line width of the portion corresponding to the stress distribution hole 5 in the lower wiring layer (substrate-side wiring layer) 21 is different. The parts are the same, and the spaces between them are the same.

The line width of the lower wiring layer 21 is, for example, 1.0 μm.
When the width becomes narrower than the following, the line width may not be widened due to the stress distribution hole 5 and may be formed to have the same width as other wiring portions. In this case, since the hole diameter of the stress distribution hole 5 becomes small and the protruding area of the lower wiring layer 21 becomes narrow, it is desirable to form the holes 4 and 5 at intervals of 30 to 40 μm, for example.

Also according to the method of connecting the laminated wirings shown in this embodiment, the protruding portion of the lower wiring layer 21 is exposed in the contact hole 4.
And the stress-dispersion holes 5 are dispersed to prevent swelling of the contact holes 4 in the upper wiring layer (surface-side wiring layer) 22 and prevent the conduction failure in which the wiring patterns of the upper wiring layer 22 contact each other. At the same time, the surface step is reduced.

(Embodiment 4) FIG. 6 is a plan view showing a lower wiring layer and an upper wiring layer connected by a multi-layer wiring connecting method according to still another embodiment of the present invention.

In the illustrated case, the line width of the portion corresponding to the stress distribution hole 5 in the lower wiring layer (substrate side wiring layer) 31 is the same as that of the other portions, and is formed in the vicinity of the contact hole 4. ing.

Thus, the line width of the lower wiring layer 31 is narrowed to, for example, 1.0 μm or less, and the wiring length is set to 100 μm, for example.
In the case of about m, the line width may be formed in the vicinity of the contact hole 4 for the stress dispersion hole 5.

Also by the method of connecting the laminated wirings shown in this embodiment, the swelling of the portion of the contact hole 4 in the upper wiring layer (surface wiring layer) 32 is eliminated, and the conduction failure in the upper wiring layer 32 is prevented. , The surface step is reduced.

(Embodiment 5) FIG. 7 is a plan view showing a lower wiring layer and an upper wiring layer connected by a multi-layer wiring connecting method which is still another embodiment of the present invention.

In the multi-layer wiring connection method according to this embodiment,
This is different from the case of the first embodiment in that the stress distribution holes 5 are formed in an elliptical shape.

As described above, the stress distribution hole 5 can be formed in any shape such as the ellipse shown in this embodiment, the ellipse, or the prism. In addition, the second embodiment
It is needless to say that even when the stress dispersion holes 5 are formed as in the cases of 4 to 4, they can be similarly formed into an arbitrary shape.

Also according to the method of connecting the laminated wirings shown in the present embodiment, the protrusion of the contact hole 4 in the upper wiring layer (surface layer wiring layer) 42 due to the protrusion of the lower wiring layer (substrate wiring layer) 41. Is eliminated, the conduction failure in the upper wiring layer 42 is prevented, and the surface step is mitigated.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the semiconductor substrate may be another semiconductor substrate such as germanium, or SOS (S
It may be an SOI (Silicon On Insulator) semiconductor substrate in which a single crystal silicon film is grown on an insulator such as silicon on insulator, or a compound semiconductor substrate such as GaAs.

Furthermore, each wiring layer 1, 2, 11, 12, 2
The deposition of 1, 22, 31, 32, 41, 42 and the interlayer insulating film 3 may be performed by a physical method such as a sputtering method instead of a chemical method such as a CVD method. Further, for those etchings, either wet etching or dry etching may be used.

Further, in the present embodiment, the stress distribution holes 5 are formed at two places, but they may be formed at one place or at three or more places.

[0051]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.

(1) That is, according to the laminated wiring connection technique of the present invention, by forming the stress distribution holes, the wiring layer on the substrate side caused by the internal stress of the interlayer insulating film, the stress of the heat treatment process, or the like is formed. The protrusion is distributed to the contact hole and the stress distribution hole. Therefore, swelling of the contact hole portion does not occur when the surface wiring layer is deposited.

(2) As a result, it is possible to prevent the conduction failure due to the contact between the wiring patterns of the formed surface wiring layer.

(3) Also, since the swelling at the contact hole portion is eliminated and the surface step is reduced,
It becomes possible to finish the lithography and etching in the subsequent steps in good condition.

[Brief description of drawings]

FIG. 1 is a plan view showing a lower wiring layer and an upper wiring layer connected by a method for connecting multilayer wiring according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part of FIG.

FIG. 3 is a flowchart showing a method of connecting the multi-layer wiring of FIG.

FIG. 4 is a plan view showing a lower wiring layer and an upper wiring layer which are connected by a method for connecting multi-layer wiring according to a second embodiment of the present invention.

FIG. 5 is a plan view showing a lower wiring layer and an upper wiring layer, which are connected by a multi-layer wiring connecting method according to a third embodiment of the present invention.

FIG. 6 is a plan view showing a lower wiring layer and an upper wiring layer which are connected by a multi-layer wiring connecting method according to a fourth embodiment of the present invention.

FIG. 7 is a plan view showing a lower wiring layer and an upper wiring layer which are connected by a method for connecting multi-layer wiring according to a fifth embodiment of the present invention.

FIG. 8 is a plan view showing a lower wiring layer and an upper wiring layer which have been studied by the present inventors.

9 is a cross-sectional view of the main parts of FIG.

[Explanation of symbols]

1 Lower Wiring Layer (Substrate Side Wiring Layer) 2 Upper Wiring Layer (Surface Layer Side Wiring Layer) 3 Interlayer Insulating Film 3a First PSG Film 3b SOG Film 3c Second PSG Film 4 Contact Hole 5 Stress Dispersion Hole 6 SiO ₂ Film 11 Lower wiring layer (board wiring layer) 12 Upper wiring layer (surface layer wiring layer) 21 Lower wiring layer (board wiring layer) 22 Upper wiring layer (surface layer wiring layer) 31 Lower wiring layer (board Side wiring layer) 32 upper wiring layer (surface layer wiring layer) 41 lower wiring layer (board wiring layer) 42 upper wiring layer (surface layer wiring layer) 51 lower wiring layer (board wiring layer) 52 upper wiring layer (Surface layer side wiring layer) 53 Interlayer insulating film 54 Contact hole S ₁ First step S ₂ Second step S ₃ Third step S ₄ Fourth step S ₅ Fifth step S ₆ Sixth step

Claims (4)

[Claims] 1. A method of connecting multi-layer wiring for electrically connecting a substrate side wiring layer and a surface side wiring layer in a laminated structure formed on a semiconductor substrate, the method comprising depositing the substrate side wiring layer, Etching the substrate-side wiring layer to form a pattern, depositing an interlayer insulating film on the substrate-side wiring layer, the substrate-side wiring layer and the surface layer with respect to the interlayer insulating film Forming a contact hole at an intersection with the side wiring layer and forming a stress distribution hole at a position located on the substrate side wiring layer; and the interlayer insulating film having the contact hole and the stress distribution hole formed therein. A method of connecting multi-layer wiring, comprising: a step of depositing a surface layer side wiring layer on the top surface; and a step of etching the surface layer side wiring layer to form a pattern. 2. The method of connecting multilayer wirings according to claim 1, wherein the contact holes and the stress distribution holes are formed at equal intervals. 3. The method for connecting multilayer wirings according to claim 1, wherein the contact holes and the stress distribution holes are formed at intervals of about 50 μm or less. 4. The method for connecting multilayer wirings according to claim 1, wherein the stress distribution hole is formed in the vicinity of the contact hole.