JPH067576B2 - Method of manufacturing semiconductor device having multilayer wiring structure - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a connection between wiring layers of a semiconductor device having a multilayer wiring structure.

[Conventional technology]

Conventionally, a method of manufacturing a semiconductor device of this type has been one in which an interlayer insulating film is formed on a lower wiring layer and then a contact hole is provided to form an upper wiring layer.

[Problems to be solved by the invention]

That is, since the above-described conventional method for manufacturing a semiconductor device having a multilayer wiring structure is intended only to connect a lower wiring layer and an upper wiring layer, for example, the wiring of the first layer and the wiring of the third layer are In the connection between the multiple layers such as the connection, there is a disadvantage that the contact hole must be opened only in the portion covered by the interlayer insulating film without the second layer wiring, and the integration degree is lowered.

[Means for solving problems]

A method of manufacturing a semiconductor device having a multilayer wiring structure according to the present invention includes at least a first insulating film, a first wiring layer, and a second insulating layer on a semiconductor substrate or a conductive layer provided on the semiconductor substrate via an insulating layer. Steps of sequentially forming films, and selectively etching the second insulating film, the first wiring layer, and the first insulating film to form an opening having a lateral hole in the first wiring layer portion. And a step of forming a contact hole having an insulating side wall on the side surface of the opening by performing anisotropic etching after depositing the third insulating film.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1A to 1E are vertical cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, p made of silicon is used.
An n-type diffusion layer 12 is selectively formed on the type semiconductor substrate 11,
A first insulating film 13 made of PSG having a thickness of 500 nm, a first wiring layer 14 made of polycrystalline silicon having a thickness of 300 nm, and a second insulating film 15 made of PSG having a thickness of 500 nm are sequentially formed thereon. . Next, photoresist mask 1
6 is formed, the second insulating film 15 is selectively removed by chemical etching or plasma etching as shown in FIG. By selective etching to form lateral holes 17 in the first wiring layer 14. Further, anisotropic etching such as reactive ion (RIE) is used to selectively remove the first insulating film 13 to form an opening 18 reaching the n-type diffusion layer 12.

Next, as shown in FIG. 1 (c), the photoresist mask 16 is removed, and a thickness of 3 is formed on the entire surface of the semiconductor substrate by the CVD method.
A 00 nm nitride film is deposited to form a third insulating film 19. At this time, the lateral holes 17 formed in the first wiring layer 14 are completely filled with the insulating film 19 shown in FIG. Further, anisotropic etching such as RIE is performed on the entire surface of the semiconductor substrate to remove the third insulating film on the n-type diffusion layer to remove the insulating property on the side surface of the opening 18 as shown in FIG. 1 (d). By providing the side wall 20, the contact hole 21 reaching the n-type diffusion layer 12 can be obtained. Further, as shown in FIG. 1 (e), Al
The second wiring layer 22 made of is formed.

In the case of etching the second insulating film 15, by increasing the etching selection ratio between the second insulating film 15 and the first wiring layer 14, the variation in etching is alleviated in the portion of the first wiring layer. A contact hole with good uniformity can be obtained.

In this way, even in the place where the wiring layer is in the middle, the contact hole can be provided and connected between the upper wiring layer and the lower wiring layer, so that the degree of integration of the semiconductor device is improved.

FIG. 2 is a vertical sectional view of a semiconductor chip showing an application example of the present invention.

This is a MOS integrated circuit manufactured by applying the present invention. The first wiring layer 3 is made of Al and has a thickness of 300 nm.
4 is provided as a shield layer. Mutual interference between the n-type diffusion layer 32 ′ which is the source region of the MOS transistor and the second wiring layer 42 which is the drain electrode can be blocked, which is advantageous in reducing noise.

〔The invention's effect〕

As described above, the present invention forms a contact hole for connecting an upper wiring layer and a lower wiring layer of a multilayer wiring,
If there is a wiring layer in the middle, an opening with a lateral hole is provided in the middle wiring layer section, and then an insulating side wall is provided on the side surface of the opening, so that the upper layer is insulated from the middle wiring layer. Since the lower wiring layer can be connected to the lower wiring layer, there is no restriction on the place where the contact hole is provided, so that the degree of integration of the semiconductor device having the multilayer wiring structure can be improved.

[Brief description of drawings]

1 (a) to 1 (e) are sectional views of a semiconductor chip arranged in the order of steps for explaining an embodiment of the present invention, and FIG. 2 is a sectional view of a MOS integrated circuit chip showing an application example of the present invention. Is. 11, 31 ... P-type semiconductor substrate, 12, 32, 32 '... n
Type diffusion layer, 13, 33 ... First insulating film, 14, 34 ... First wiring layer, 15, 35 ... Second insulating film, 16 ... Photoresist mask, 17 ... Horizontal hole, 18 ... Open hole, 19 ... Third insulating film, 20, 30 ... Insulating side wall, 21 ... Contact hole, 22, 42 ... Second wiring layer, 43 ... Gate insulating film,
44 ... Gate electrode.

Claims (1)

[Claims] 1. A step of sequentially forming at least a first insulating film, a first wiring layer and a second insulating film on a semiconductor substrate or a conductive layer provided on the semiconductor substrate with an insulating layer interposed therebetween, Two
The insulating film, the first wiring layer and the first insulating film are selectively etched to form an opening having a lateral hole in the first wiring layer portion, and the third insulating film is covered. A method of manufacturing a semiconductor device having a multilayer wiring structure, comprising a step of performing anisotropic etching after forming and forming a contact hole having an insulating side wall on a side surface of the opening.