JPH0653328A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the contact resistance of contacts, formed collectively, between wiring layers in a contact hole in a semiconductor device of multilayer interconnection. CONSTITUTION:The title semiconductor device is obtained by depositing a plurality of polycrystalline silicon wiring layers 37, 38, 39 and 42 with layer insulating films 32, 33, 34 and 35 in-between, respectively and a plurality of specified wiring layers 39, 38 and 37, exposed at the inside face of a contact hole 40, are interconnected with one another through a connecting wiring 42A. In the semiconductor device the layer instulating films 33, 34 and 35, exposed at the inside face of the contact hole 40, are recessed from the ends of the wiring layers 38 and 39. Further, the connecting wiring 42A is deposited so as to cover the side, upper and lower faces of the projected portions of the wiring layers 38 and 39 and thereby increase the surface area of contact.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention has a multilayer wiring layer,
The present invention relates to a semiconductor device in which a plurality of required wiring layers are interconnected by contact openings, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, semiconductor devices having a multi-layer wiring structure have been developed along with the high integration. In such a semiconductor device, a plurality of required wiring layers among the wiring layers formed in multiple layers are interconnected at some contact openings.

Conventionally, in order to simplify interconnection of multi-layer wiring, instead of forming a contact opening portion for each layer and connecting wiring layers between adjacent layers, after forming the multi-layer wiring layer, 1 A method has been proposed in which contact openings are collectively formed and a conductive film for connection is formed on the inner surface of the contact opening to interconnect the wiring layers of the layers facing the inner surface of the contact opening.

FIGS. 6 to 8 show such a connection method as CMO.
S type SRAM, that is, CMOS type SR using a thin film transistor advantageous for high integration as a load P-MOS transistor
This is an example applied to AM.

First, as shown in FIG. 6A, in the semiconductor region of the first conductivity type, the diffusion layers 2 and 3 of the second conductivity type serving as the source and drain of the driver transistor and the diffusion layers serving as the source / drain of the access transistor ( (Not shown), a SiO ₂ layer 4 or the like for element isolation by selective oxidation is formed, and becomes a gate electrode of a driver transistor or an access transistor via a gate insulating film 5 made of SiO ₂ or the like on this semiconductor region 1. A first layer of polycrystalline silicon, for example, a polycide wiring layer 6 is formed.

Next, as shown in FIG. 6B, for example, SiO 2
_{The second-} layer polycrystalline silicon wiring layer 9 to be the bottom gate electrode of the thin film transistor via the interlayer insulating film 8 made of ₂ etc.
Is formed. Next, as shown in FIG. 7C, for example, Si
A third-layer polycrystalline silicon wiring layer 11 to be an active layer of a thin film transistor and a Vcc line is formed via an interlayer insulating film (including a gate insulating film) 10 such as O ₂ .

Next, as shown in FIG. 7D, for example, SiO
Upper layer insulation film (including gate insulation film) consisting of ₂ etc.
After forming 12, the contact opening 13 is formed so as to reach from the interlayer insulating film 12 to the first polycide wiring layer 6 connected to the diffusion layer 3.

Next, as shown in FIG. 8E, a fourth-layer polycrystalline silicon wiring layer 14 serving as a top gate electrode of the thin film transistor is formed, and a connecting wiring 14A extending integrally is formed in the contact opening portion. 1 is formed along the inner surface of 13 and faces the inner surface of the contact opening 13.
The polycide wiring layer 6 of the second layer, the polycrystalline silicon wiring layer 9 of the second layer, and the polycrystalline silicon wiring layer 11 of the third layer are interconnected. Here, the second-layer and third-layer polycrystalline silicon wiring layers 9 and 11 are connected to the connection wiring 14A only on the side surface corresponding to the film thickness.

Then, as shown in FIG. 8F, for example, Si
A fifth-layer polycrystalline silicon wiring layer 16 serving as a ground line is formed via an interlayer insulating film 15 of O ₂ or the like. 17
Is an interlayer insulating film.

[0010]

By the way, in a semiconductor device having a multilayer wiring structure, for example, the above-mentioned CMOS SRAM, a connection wiring 14A extending from the fourth-layer polycrystalline silicon wiring 14 in the contact opening 13 thereof. The second and third polycrystalline silicon wiring layers 9 and 11
In this case, the second-layer and third-layer polycrystalline silicon wiring layers 9 and 11 are connected to the connection wiring 14A only on the side surface corresponding to the film thickness. Therefore, since the contact surface area between the connection wiring 14A and the second and third polycrystalline silicon wiring layers 9 and 11 is small and the contact resistance is high, the on-current of the thin film transistor may be suppressed. It was

In view of the above points, the present invention provides a semiconductor device capable of interconnecting multiple layers of wirings (that is, conductors) so as to increase the contact surface area and reduce the contact resistance, and a manufacturing method thereof. is there.

[0012]

According to the present invention, an interlayer insulating film 3 is provided.
2, 33, 34, and 35, which have multilayer conductor layers 37, 38, 39, 42 that are laminated via the contact opening portion 40.
In the semiconductor device in which a plurality of required conductor layers 37, 38, 39 facing the inner surface of the contact layer 40 are interconnected by the connecting conductor film 42A, the interlayer insulating films 33, 34, 35 facing the inner surface of the contact opening 40 are formed as conductor layers. Retreat from 38, 39,
A plurality of required conductor layers 3 including the recessed space 41
A connecting conductor film 42A for interconnecting 7, 38 and 39 is adhered and formed.

Further, in the method of manufacturing a semiconductor device according to the present invention, the step of forming the multi-layered conductor layers 37, 38, 39, 42 via the interlayer insulating films 32, 33, 34, 35, and the interlayer insulating film 35. , 34, 33 and the conductor layers 38, 39 to form the contact opening 40, a step of etching back the interlayer insulating films 33, 34, 35 exposed to the inner surface of the contact opening 40, and the contact opening 40.
Connection conductor film 42A including the space 41 receding on the inner surface of the
And depositing and connecting the required plurality of conductor layers 37, 38, 39.

[0014]

In the semiconductor device according to the present invention, the interlayer insulating films 33, 34, 35 facing the inner surface of the contact opening 40 are formed.
Is retracted from the conductor layers 38 and 39, the end portions of the conductor layers 38 and 39 of the plurality of layers are in a state of protruding in the contact opening 40. Then, by forming the connecting conductor film 42A by including the space 41 formed by this receding, the connecting conductor film 42A is formed on the conductor layers 38, 39 protruding from the inner surface of each contact opening 40. , Not only the side surface but also the upper surface and the lower surface are contacted, and the contact surface area is increased. Therefore, the contact resistance in the contact portion is reduced.

In the manufacturing method according to the present invention, after forming the multi-layered conductor layers 37, 38 and 39, the contact openings 40 are collectively formed to simplify the step of forming the contact portions. Moreover, the occupied area of the contact portion is reduced. Moreover, after the contact opening 40 is formed,
By etching back only the interlayer insulating layers 35, 34, 33 exposed to the inner surface of the contact opening 40, each conductor layer 38 exposed to the inner surface of the contact opening 40,
It is possible to partially project 39. Thereafter, by forming the connecting conductor film 42A by including the space 41 formed by the receding, the contact surface area between the connecting conductor film 42A and the connecting conductor film 42A is increased. Can be interconnected.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a basic structure of a semiconductor device having multi-layer wiring according to the present invention, particularly a contact portion thereof.
In this example, the interlayer insulating film 32,
3 made of, for example, polycrystalline silicon or the like via 33, 34
The conductor layers, that is, the wiring layers 37, 38, 39 are formed, and the contact openings 40 extending from the upper interlayer insulating film 35 to the first wiring layer 37 are formed in predetermined portions. This contact opening 40 is formed by anisotropic etching. Therefore, the contact opening 40 is formed to have a vertical step.

Then, on the inner surface of the contact opening 40, only the interlayer insulating films 33, 34 and 35 are formed on the wiring layer 3.
The exposed end faces of 8, 39 are retracted from the so-called side faces. The receding of the interlayer insulating films 38, 39 can be achieved by selectively removing only the interlayer insulating films 33, 34, 35 by isotropic etching, for example.

Then, on the inner surface of the contact opening 40,
A connection wiring 42A is integrally formed with the fourth conductor layer, that is, the wiring layer 42 made of, for example, polycrystalline silicon, so as to extend along the space 41 formed by the receding of the interlayer insulating films 33, 34 and 35. Adhering and forming each wiring layer 3
7, 38, 39 are connected to each other.

According to this structure, the contact opening 4
In FIG. 0, each wiring layer 38 in which the connection wiring 42A partially protrudes due to the receding of the interlayer insulating films 33, 34 and 35,
By making contact with the side surface, the upper surface, and the lower surface of 39, the contact surface area can be increased as compared with the case where only the side surface of the conventional wiring layer is contacted. Therefore, the contact resistance at the contact portion can be reduced.

Further, since the contact opening 40 is formed in a lump after the multi-layered wiring layers 37, 38, 39 are formed, the manufacturing process is simplified and the area occupied by the contact opening 40 is reduced. The size of the semiconductor device can be reduced and the density of the semiconductor device can be increased.

3 to 5 show the above-mentioned CMO of the present invention.
An example applied to an S-type SRAM will be shown together with its manufacturing method. In the figure, the parts corresponding to those in FIGS. 6 to 8 are designated by the same reference numerals. First, as shown in FIG. 3A, in the first conductive type semiconductor region 1, the second conductive type diffusion layers 2 and 3 serving as the source and drain of the driver transistor, and the diffusion layers serving as the source and drain of the access transistor (not shown). No),
An SiO ₂ layer 4 for element isolation by selective oxidation is formed. On this semiconductor region 1, a first layer of polycrystalline silicon, for example, a polycide wiring layer 6 which will be the gate electrodes of the driver transistor and the access transistor is formed via a gate insulating film 5 made of SiO ₂ or the like.

Next, as shown in FIG. 3B, for example, SiO 2
_{The second-} layer polycrystalline silicon wiring layer 9 to be the bottom gate electrode of the thin film transistor via the interlayer insulating film 8 made of ₂ etc.
To form.

Next, as shown in FIG. 3C, for example, SiO 2
An interlayer insulating film (including a gate insulating film) 10 such as ₂ is formed, and an active layer of a thin film transistor, and a third-layer polycrystalline silicon wiring layer 11 to be a Vcc line are formed. FIG. 3A-
The steps up to FIG. 3C are the same as the steps up to FIG. 6A to FIG. 7C described above.

Next, as shown in FIG. 4D, for example, SiO 2
After forming an interlayer insulating film (including a gate insulating film) 12 made of ₂ or the like, for example, RIE is performed through a resist mask 25.
Vertical steps reaching the first polycide wiring layer 6 from the interlayer insulating film 12 through the third and second polycrystalline silicon wiring layers 11 and 9 by anisotropic etching such as (reactive ion etching). The contact opening 40 is formed.

Next, as shown in FIG. 4E, using the same resist mask 25, so-called isotropic etching such as wet etching or plasma etching is performed.
Interlayer insulating films 8 and 1 facing the inner surface of the contact opening 40
Selectively remove 0 and 12. As a result, the interlayer insulating films 8, 10 and 12 recede inwardly from the end faces (so-called side faces) of the polycrystalline silicon wiring layers 9 and 11 facing the contact openings 40 to form a space 41. That is, in other words, the end portions of the polycrystalline silicon wiring layers 9 and 11 on the contact opening 40 side are partially projected from the interlayer insulating films 8, 10 and 12.

Next, as shown in FIG. 5F, a fourth-layer polycrystalline silicon wiring layer 14 serving as a top gate electrode of the thin film transistor is formed on the interlayer insulating film 12 and, at the same time, it is integrally extended. 14A is deposited along the inner surface of the contact opening 40, and the contact opening 4 is formed.
The polycrystalline silicon wiring layers 11 and 9 and the polycide wiring layer 6 facing the inner surface of 0 are mutually connected.

In this case, the polycrystalline silicon wiring layer 14 is C
Since it is formed by the VD (Chemical Vapor Deposition) method, it also enters the space 41 due to the receding of the interlayer insulating films 8, 10, 12.
The polycrystalline silicon wiring layers 9 and 11 of the second and third layers are deposited and formed not only on the side surfaces but also on the upper and lower surfaces.

Then, as shown in FIG. 5G, for example, S
A fifth-layer polycrystalline silicon wiring layer 16 to be a ground line is formed via an interlayer insulating film 15 of iO ₂ or the like. 17
Is an interlayer insulating film.

According to such a CMOS type SRAM, the second and third polycrystalline silicon wiring layers 9 and 11 in the contact opening 13 are connected to the connection wiring 14A on the side surface, the upper surface and the lower surface, respectively. Therefore, the contact surface area is increased and the contact resistance can be reduced.
As a result, the on-current of the thin film transistor can be properly obtained.

FIG. 2 shows another embodiment of the present invention. In this example, as shown in FIG. 2A, three wiring layers 37, 38 and 39 made of, for example, polycrystalline silicon are formed on a semiconductor substrate 31 with interlayer insulating films 32, 33 and 34 interposed therebetween, and further upper layers are formed. After forming the inter-layer insulating film 35, the contact opening 40 is formed through the resist mask 25 by selective etching such as isotropic etching.

At this time, the etching conditions are selected so that the interlayer insulating films 33, 34 and 35 are etched slightly earlier than the conductor layers 38 and 39, and the wiring layers 39 and 38 and the interlayer insulating films are formed in one etching step. Both 35, 34 and 33 are selectively etched. As a result, on the inner surface of the contact opening 40, the interlayer insulating films 33, 34 and 35 are etched so as to recede from the side surfaces of the wiring layers 38 and 39,
And finally, since the etching is isotropic, the opening width becomes larger toward the upper part of the contact opening 40.

Then, as shown in FIG. 2B, a connecting wiring 42A is integrally extended along the inner surface of the contact opening 40 with the wiring layer 42 of the fourth-layer polycrystalline silicon.
Wiring layers 37, 38 and 39 which are formed by deposition to face the inner surface
Interconnect each other.

Also in this structure, the wiring layers 38 and 39 are formed in the contact openings 40 by the interlayer insulating films 35 and 3.
Since the protrusions 4 and 33 are protruded, the contact resistance between the connection wiring 42A and the wiring layers 38 and 39 can be reduced as described above. Moreover, in this example,
Since the opening width of the contact opening portion becomes larger toward the upper portion, the coverage of the connection wiring 42A in the opening portion 40 also becomes good.

[0035]

According to the present invention, in a semiconductor device having a multi-layered conductor layer, the contact surface area can be increased within the contact opening to make interconnection between the conductor layers of each layer, thereby reducing the contact resistance. Can be planned.

Further, in the manufacturing method, when the multiple conductor layers are formed, the contact openings are collectively formed to simplify the process and reduce the area occupied by the contact openings. Therefore, the density of semiconductor devices can be increased.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part showing an example of a semiconductor device according to the present invention.

FIG. 2 is a manufacturing process diagram of a main part showing another example of the semiconductor device according to the invention.

FIG. 3 is a manufacturing process diagram (1) in the case where the present invention is applied to a CMOS SRAM.

FIG. 4 is a manufacturing process diagram (2) when the present invention is applied to a CMOS SRAM.

FIG. 5 is a manufacturing process diagram (3) when the present invention is applied to a CMOS SRAM.

FIG. 6 is a manufacturing process diagram (1) of a conventional CMOS SRAM.

FIG. 7 is a manufacturing process diagram (2) of a conventional CMOS SRAM.

FIG. 8 is a manufacturing process diagram (3) of the conventional CMOS SRAM.

[Explanation of symbols]

 31 semiconductor substrate 32, 33, 34, 35 interlayer insulating film 37, 38, 39, 42 wiring layer 40 contact opening 41 space 42A connection wiring.

Claims (2)

[Claims] 1. A semiconductor device having a plurality of conductive layers laminated via an interlayer insulating film, wherein a plurality of required conductor layers facing an inner surface of a contact opening are interconnected by a connecting conductor film. The interlayer insulating film facing the inner surface of the contact opening recedes from the conductor layer, and the connecting conductor film interconnecting the required plurality of conductor layers including the recessed space is deposited and formed. Comprising semiconductor device. 2. A step of forming a multi-layer conductor layer via an interlayer insulating film, a step of forming a contact opening through the interlayer insulating film and the conductor layer, and the interlayer insulating facing the inner surface of the contact opening. Etching the film to make it recede, and depositing a connecting conductor film on the inner surface of the contact opening including the receding space to interconnect the required conductor layers. A method for manufacturing a characteristic semiconductor device.