JPH0653441A - Cell structure and sram memory cell structure having thin film transistor and formation thereof - Google Patents

Abstract

PURPOSE:To provide a cell structure having TFT and formation thereof in which no retriction is imposed on the layout of TFT which can thereby be laid out even if a unit cell is shortened in one direction. CONSTITUTION:In a cell structure comprising a layer constituting a thin film transistor(TFT), a layer constituting at least one transistor other than the TFT, and a TFT having cell structure formed by these transistors, power supply lines 17a, 17a' for TFT are placed at the upper or lower side of a cell and channel parts 17b, 17b' of TFT are formed substantially perpendicular to the power supply lines. The power supply lines are isolated from a contact hole 18 through a dielectric film formed on the side wall of the contact hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell structure provided with a thin film transistor (hereinafter sometimes abbreviated as "TFT" as appropriate), an SRAM memory cell structure provided with a thin film transistor, and a method for forming a cell structure provided with a thin film transistor. .

[0002]

2. Description of the Related Art As a cell structure including a thin film transistor, for example, a TFT load type SRAM memory cell structure is known. FIG. 14 shows a general CMOS-SRAM
As an example of the memory cell structure, a word transistor and a driver transistor are formed on a Si substrate, and a TFT is stacked as a load element on the upper layer portion of the memory cell. A substrate structure of a unit cell having a structure in which transistors (the electrodes of which are shown by 8 and 9) are arranged substantially in parallel and point-symmetrically with respect to the cell center is shown.

FIG. 15 showing a memory unit cell circuit.
Inside, transistors 1 and 6 are word transistors,
Transistors 2 and 5 are driver transistors,
The transistors 3 and 4 are TFTs that form load transistors.

In the highly integrated memory after 4MSRAM,
Word transistor and driver transistor are formed on Si substrate, and load transistor is PMOS-TFT.
It is customary to configure with, and an example thereof is the structure shown in FIG. However, FIG. 14 shows only the arrangement of the gate electrodes of the word transistor and the driver transistor and the related contacts. That is, the electrode 7 is a word line (corresponding to the word transistors 1 and 6 in FIG. 15) and the electrodes 8 and 9 are driver transistors (corresponding to the driver transistors 2 and 5 in FIG. 15).
The part indicated by medium code 10 is an element isolation region for separating them. The signal extracted from the node contact 11 passes through the word transistor 7 and is extracted from the bit contact 12 via the diffusion layer below the contact portion of the electrode 8. In the figure, S indicates a signal.

There are various proposals for the layout of the power supply line of such a unit cell and the TFT channel structure. For example, the applicant has previously proposed a configuration in which a power supply line is placed in the center of the cell and an L-shaped TFT channel is branched from the power supply line. This structure is
By making the channel L-shaped, the channel length can be increased and it is effective in suppressing the league current to be low. However, on the other hand, if the size of the cell in the Y direction becomes smaller, the design around the contact becomes very strict, which makes it difficult to perform layout.

[0006]

SUMMARY OF THE INVENTION The present invention solves the above problems and provides a TFT
In the cell structure including the above, the problem that the layout is limited is solved, and the thin film transistor can be laid out even if one direction of the unit cell (for example, the Y direction in which the cells are arranged side by side) is shortened. The present invention provides a cell structure and a method for forming the same, and is applied to the cell structure of SRAM to solve the layout limitation of the load TFT and to improve the soft error resistance. An object is to provide a memory cell structure.

[0007]

The invention according to claim 1 of the present application has a layer forming a thin film transistor and a layer forming at least one transistor other than the thin film transistor, and these transistors form a cell structure. In a cell structure including a thin film transistor that is formed, a power supply line to the thin film transistor is arranged on at least one of the upper side and the lower side of the cell, and the channel part of the thin film transistor is formed substantially vertically from the power supply line. Insulation between the supply line and the contact hole is a cell structure provided with a thin film transistor characterized in that this insulation is performed by a sidewall insulating film formed in the contact hole, which solves the above problems. .

A second aspect of the invention of the present application is a thin film transistor having a layer forming a thin film transistor and a layer forming at least a pair of transistors other than the thin film transistor, and a cell structure being formed by these transistors. In the cell structure including, the power supply line to the thin film transistor is arranged on the upper side and the lower side of the cell, and the channel portion of the thin film transistor is formed substantially vertically from the power supply line and substantially point symmetrical with respect to the cell center. The insulation between the supply line and the contact hole is
A cell structure provided with a thin film transistor is characterized in that this insulation is performed by a sidewall insulating film formed in a contact hole, which solves the above problems.

According to a third aspect of the present invention, an SRAM memory cell is provided with a thin film transistor having a structure in which a word line is arranged near the center of the cell, and one driver transistor is arranged on each side of the word line substantially in parallel and in substantially point symmetry. In the structure, power supply lines to the thin film transistor are arranged on the upper side and the lower side of the cell, and the channel part of the thin film transistor is formed substantially perpendicular to the power supply line and substantially point-symmetric with respect to the cell center, and contacts with the power supply line. Insulation from holes is an SRAM memory cell structure provided with a thin film transistor characterized in that this insulation is performed by a side wall insulating film formed in the contact hole, which solves the above problems.

The invention of claim 4 of the present application is an SRAM memory cell structure provided with the thin film transistor according to any one of claims 1 to 3, wherein the thin film transistor is a PMOSTFT, which solves the above problems. Is.

The invention of claim 5 of the present application comprises a thin film transistor having a layer forming a thin film transistor and a layer forming at least one transistor other than the thin film transistor, and a cell structure is formed by these transistors. In the method for forming a cell structure, a step of forming a conductive film, a step of forming a contact hole, and a step of forming an insulating film in a structure in which a power supply line to a thin film transistor is arranged on at least one of an upper side and a lower side of the cell. A step of forming an insulating film on at least the side wall of the contact hole by etching,
This is a method for forming a cell structure having a thin film transistor, characterized in that the power supply line and the contact hole are insulated from each other by the sidewall insulating film formed in the contact hole. It is a solution to the problem.

[0012]

According to the invention of the present application, a cell including a thin film transistor having a layer forming a thin film transistor and a layer forming at least one transistor other than the thin film transistor, and having a cell structure formed by these transistors In the structure (and SRAM cell structure), a power supply line to the thin film transistor is arranged on one or both of the upper side and the lower side of the cell, and the channel portion of the thin film transistor is formed substantially perpendicular to the power supply line and the power supply line. Insulation from contact holes
Since the side wall insulating film formed in the contact hole is used for this insulation, the thin film transistor can be laid out even if the unit cell is shortened in one direction, and such a cell structure can be easily formed. You can In addition, the load TF is applied to the cell structure of SRAM.
It is possible to solve the restriction on the layout of T and improve the soft error resistance.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. However, it should be understood that the present invention is not limited to the illustrated embodiments.

Example 1 In this example, a PMOSTFT is used as a load transistor.
The invention of the present application is applied to the formation of an SRAM cell structure having

The cell structure has a layer forming a thin film transistor and a layer forming at least one transistor other than the thin film transistor, and the cell structure is formed by these transistors. Figure 1
In this cell structure, the power supply lines 17a and 17a 'to the thin film transistors are arranged on at least one of the upper side and the lower side of the cell (in this embodiment, they are arranged on both the upper side and the lower side). ), The channel portions 17b and 17b 'of the thin film transistor are formed substantially vertically from the power supply line. Also, as shown in FIG.
Power supply line 17a and contact hole 12 (Vss
The insulation from the contact 18) is performed by the side wall insulating film 22 formed in the contact hole.

In this embodiment, the channel portions 17a and 17b 'of the thin film transistor are formed substantially perpendicular to the power supply line and substantially point symmetrical with respect to the cell center.

The cell structure of this embodiment is specifically as follows.
This is an SRAM memory cell structure including a thin film transistor (particularly a PMOSTFT) having a structure in which a word line is arranged near the center of the cell and one driver transistor is arranged on both sides thereof in a substantially parallel and substantially point symmetrical manner.

The cell structure of this example was manufactured by the following steps. That is, as shown in FIGS. 2 to 5, a step of forming a power supply line 17a to the thin film transistor by a conductive film in a configuration in which it is arranged on the upper side and the lower side of the cell, and a step of forming a contact hole 18 (FIG. 2). , Insulating film 2
2 '(FIG. 3) and a step of forming a sidewall insulating film 22 on at least the sidewall of the contact hole 18 by etching (FIG. 4), whereby a power supply line 17a is formed as shown in FIG. Contact hole 12,
Insulation from the side wall insulating film 22 formed in the contact holes 12 and 18 is carried out.

More specifically, the transistor arrangement on the Si substrate in this embodiment is as shown in FIG. The same reference numerals as those in FIG. 1 indicate corresponding components. 7 to 9 show the layer-by-layer configuration of this embodiment, which is an exploded view of FIG. 7 shows the pattern of the element isolation region 10 (the hatched region is the active layer), and FIG. 8 shows the word line 7
(And word transistor), FIG. 9 shows the driver transistor 8. When forming a pattern using a Levenson type phase shift mask, the phase of the left and right patterns in FIG. 7 is 0 / π, and the upper pattern in FIG. 8 is 0 and the lower pattern is π in FIG. As for the cell next to it, it is preferable that the upper pattern is π and the lower pattern is 0.

In FIG. 6, the signal taken out from the node contact 11 passes through the word transistor 8 and
It is pulled out from the bit contact 12.

The structure of the (TFT) forming the load transistor of the SRAM cell of this embodiment will be described below. In the prior art, the power supply line is placed in the center of the cell, but this cannot be laid out unless there is a margin in the Y direction of the cell. On the other hand, the present embodiment is configured as follows.

FIG. 10 shows the node contact 11
And the capacitor plate 16 that extends over the driver gate contact 13.

FIG. 11 shows a TFT gate electrode 21.
The part covered with 〇 is a capacitor. The equivalent circuit is shown in FIG.

FIG. 1 shows the channel portion 17 of the TFT.
b, 17b 'and power supply lines 17a, 17a'. The characteristic of this structure is that the power supply lines 17a and 17a 'are connected to the bit contact 12 and Vs.
It is over the s contact 18.

The method of manufacturing the cell structure of this embodiment will be described below with reference to the sectional views of the respective steps shown in FIGS.

First, the power supply line 17a is made of polycrystalline Si.
After forming the inter-layer insulation 23 of Si oxide or the like, the Vss contact 18 is opened to obtain the structure of FIG.

Further, an insulating film 22 'for side wall insulation is formed of a Si nitride film or the like (FIG. 3).

After that, the Si surface at the bottom of the contact is exposed while leaving the sidewalls by utilizing the characteristic of anisotropic etching, and the sidewall insulating film 22 is formed as shown in FIG.

After forming the Vss line 19, the bit line 20 is formed through the same steps, thereby obtaining the structure of FIG.

In this configuration example, the Vss line 19 is processed so as not to reach the bit contact 12 in advance.
It is also possible to etch 2 at the same time when opening.

FIG. 13 shows an example of a cross section of the gate contact 13 portion. In this configuration example, the layout is such that the driver gate 9, the capacitor plate 16, and the TFT gate 21 are simultaneously contacted when the contact 13 of the TFT channel 17 is opened.

[0032]

According to the invention of the present application, the problem that the layout is limited in the cell structure including the TFT can be solved. That is, it was possible to provide a cell structure including a TFT capable of laying out a thin film transistor even when one direction of a unit cell (for example, a Y direction in which cells are arranged side by side) is shortened, and a method of forming the cell structure. Further, it was possible to provide an SRAM memory cell structure including a TFT that can be applied to the SRAM cell structure to solve the limitation of the layout of the load TFT and improve the soft error resistance.

[Brief description of drawings]

FIG. 1 is a diagram showing a planar structure of a TFT channel portion and a power supply line of Example 1.

FIG. 2 is a cross-sectional view showing a manufacturing process (1) of the first embodiment.

FIG. 3 is a cross-sectional view showing a manufacturing process (2) of the first embodiment.

FIG. 4 is a cross-sectional view showing a manufacturing process (3) of the first embodiment.

FIG. 5 is a cross-sectional view showing a manufacturing process (4) of the first embodiment.

FIG. 6 is a diagram showing a transistor layout on a substrate of Example 1 in a pattern plane structure.

FIG. 7 is a layer-by-layer configuration diagram of Example 1, showing an element isolation pattern.

FIG. 8 is a layer-by-layer configuration diagram of the first embodiment and illustrates a word transistor pattern.

FIG. 9 is a layer-by-layer configuration diagram of Example 1, showing a driver transistor pattern.

FIG. 10 is a diagram showing a planar structure of a capacitor plate.

FIG. 11 is a diagram showing a planar structure of a gate electrode.

FIG. 12 is a circuit diagram showing an equivalent circuit of the first embodiment.

FIG. 13 is a diagram showing a configuration example of a cross section of a gate contact portion.

FIG. 14 shows a planar structure of a conventional example.

FIG. 15 shows a circuit diagram of a general unit cell circuit.

[Explanation of symbols]

17a, 17a 'Power supply line 17b, 17b' Channel part 18 Contact hole (Vss contact) 22 Sidewall insulating film

Claims (5)

[Claims] 1. A cell structure comprising a thin film transistor having a layer forming a thin film transistor, and a layer forming at least one transistor other than the thin film transistor, wherein a cell structure is formed by these transistors. The power supply line is disposed on at least one of the upper side and the lower side of the cell, the channel portion of the thin film transistor is formed substantially vertically from the power supply line, and the insulation between the power supply line and the contact hole is formed in the contact hole. A cell structure provided with a thin film transistor characterized in that this insulation is performed by a side wall insulating film. 2. A cell structure comprising a thin film transistor having a layer forming a thin film transistor, and a layer forming at least one pair of transistors other than the thin film transistor, wherein a cell structure is formed by these transistors. Power supply lines to the upper and lower sides of the cell, and the channel portion of the thin film transistor is formed substantially perpendicular to the power supply line and substantially point-symmetric with respect to the center of the cell to insulate the power supply line from the contact hole. Is a cell structure having a thin film transistor characterized in that this insulation is performed by a sidewall insulating film formed in a contact hole. 3. An SRA provided with a thin film transistor having a structure in which a word line is arranged near the center of a cell, and one driver transistor is arranged on each side of the word line substantially in parallel and in substantially point symmetry.
In the M memory cell structure, power supply lines to the thin film transistor are arranged on the upper and lower sides of the cell, and the channel part of the thin film transistor is formed substantially perpendicular to the power supply line and substantially point symmetrical with respect to the cell center. The line and the contact hole are insulated from each other by a side wall insulating film formed in the contact hole.
M memory cell structure. 4. An SRAM memory cell structure having a thin film transistor according to claim 1, wherein the thin film transistor is a PMOS TFT. 5. A method for forming a cell structure, comprising a thin film transistor, and a thin film transistor having a layer forming at least one transistor other than the thin film transistor, wherein the cell structure is formed by these transistors, A step of forming a power supply line to the thin film transistor on at least one of the upper side and the lower side of the cell by a conductive film, a step of forming a contact hole, and a step of forming a contact film by etching an insulating film. And a step of forming an insulating film on at least a side wall, whereby a power supply line and a contact hole are insulated from each other by the side wall insulating film formed on the contact hole. Method of forming cell structure.