JPH09172078A - Wiring structure of semiconductor device and its forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a further highly integrated semiconductor device, avoiding the increase of the number of its manufacturing processes. SOLUTION: On a semiconductor substrate 1, an insulation film 4 is formed to form selectively a groove 4a and contact hole 4b therein. Then, burying tungsten in both the groove 4a and hole 4b, a buried wiring 5 and plug 6 are formed respectively, forming a tungsten film on the insulation film 4. Subsequently, patterning the foregoing tungsten film, a wiring 7b is formed. Still, diffusion layers 2 on the surface of the substrate 1 are interconnected electrically by the buried wiring 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor device and a method of forming the same, and more particularly, to a wiring structure of a semiconductor device and a method of forming the same, which can further increase the density of the semiconductor device. 2. Description of the Related Art In recent years, with the increase in integration of integrated circuits (ICs), it has been required to form a logic part and a memory part such as SRAM in the same chip with high density.

[0002]

25 is a plan view showing an example of a wiring structure of a conventional semiconductor device, and FIG. 26 is a sectional view taken along the line FF of FIG. Diffusion regions 72 and 73 formed by selectively introducing impurities are provided on the surface of the semiconductor substrate 71. An insulating film 74 is formed on the substrate 71. Contact holes 74a, 74b, 74c are selectively formed on the diffusion regions 72, 73 of the insulating film 74. A conductor is embedded in these holes 74a, 74b, 74c to form plugs 75a, 75b, 75c. Further, wirings 77a, 77 are formed on the insulating film 74.
b and 77c are formed, and the wiring 77a is a plug 75.
The wiring 77b is connected to the diffusion regions 72 via the plugs 75b.

[0003]

However, in the above-described wiring structure of the conventional semiconductor device, due to the restrictions on the mask formation in the photolithography process, the distance between adjacent wirings (for example, wirings 77a and 77b in FIGS. 25 and 26) is increased.
Since it is difficult to reduce the space between the wirings, there is a problem in that the occupied area of the wiring is increased and high integration is hindered, or the number of wiring layers increases and the manufacturing process becomes complicated. .

In Japanese Patent Laid-Open No. 4-249346, after forming a first wiring on the insulating film, a second insulating film is formed on the entire surface and is etched back to form the first wiring. By forming an insulating side wall on the side part, further forming a metal layer on the entire surface, and etching back this to form a second wiring on the side of the first wiring via the insulating side wall,
High integration has been proposed. However, according to this method, the pattern width of the second wiring is determined by the insulating side wall in a self-aligned manner, so that the second wiring having a desired pattern width cannot be obtained.

The present invention was created in view of the problems of the above-mentioned conventional example, and it is possible to avoid an increase in the number of manufacturing steps and to further increase the degree of integration of a semiconductor device. It is intended to provide a structure and a method for forming the structure.

[0006]

Means for Solving the Problems The above-mentioned problems have been solved by forming an insulating film formed on a semiconductor substrate, an embedded wiring embedded in a groove provided in the insulating film, and an insulating film formed on the insulating film. A semiconductor device having a second wiring, wherein the embedded wiring electrically connects two conductive layers at different positions when viewed from above.

Further, the above-mentioned problem exists in a position different from the step of forming an insulating film on a semiconductor substrate when viewed from above.
A step of forming a groove for exposing one conductive layer in the insulating film, and a step of forming a buried wiring by burying a conductor in the groove and forming a second wiring on the insulating film. This is solved by a method for forming a wiring structure of a semiconductor device, which is characterized by:

In the present invention, a groove is formed in the insulating film,
A conductor is embedded in this groove to form a wiring. Also,
Second wiring is formed on the insulating film. In this case, since the groove and the second wiring are formed in separate steps, the groove and the second wiring (in other words, the embedded wiring and the second wiring).
Wiring) can be arranged close to each other. This enables high integration of semiconductor devices such as SRAMs. In addition, the groove may be formed at the same time when the contact hole is formed in the insulating film, and the conductive film to be the second wiring may be formed at the same time when the conductive material is embedded in the groove. It is possible to avoid an increase in the number of steps. Further, since the wiring is embedded in the insulating film, the upper portion of the embedded wiring portion is flattened. That is, planarization cannot be achieved by forming the plug buried in the contact hole.
On the other hand, by arranging the wiring embedded in the insulating film so as not to overlap the lower wiring, the wiring can be connected to the lower wiring without a plug, which promotes flattening of the multilayer wiring.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. (First Embodiment) FIG. 1 is a plan view showing a first embodiment of a wiring structure of a semiconductor device of the present invention, and FIG. 2 is a line A--A of FIG.
It is sectional drawing by a line.

Diffusion regions 2 and 3 formed by diffusing impurities are formed in parallel with each other on the surface of the semiconductor substrate 1. An insulating film 4 is formed on the substrate 1. A groove 4a extending in a direction orthogonal to the diffusion regions 2 and 3 when viewed from above and a contact hole 4b are selectively formed in the insulating film 4, and a conductor is formed in the groove 4a and the hole 4b. Are embedded to form the embedded wiring 5 and the plug 6. The diffusion regions 2 and 3 are electrically connected to each other via a buried wiring 5.

Wirings 7a and 7b are formed on the insulating film 4 in parallel with the embedded wiring 5 when viewed from above. The wiring 7a is connected to the diffusion region 2 on the surface of the substrate 1 via the plug 6.
Is electrically connected to 3 to 6 are sectional views showing the method of forming the wiring structure of the semiconductor device of this embodiment in the order of steps.

First, as shown in FIG. 3, diffusion regions 2 and 3 are formed by diffusing impurities into a predetermined region on the surface of the semiconductor substrate 1. After that, the insulating film 4 is formed on the substrate 1 to have a desired thickness. The insulating film 4 can be formed by a method such as depositing SiO ₂ on the substrate 1 by the CVD method. Next, as shown in FIG. 4, a photoresist film 11 is formed on the insulating film 4, and an exposure and development process is performed,
The resist film 11 in the portion corresponding to the groove 4a and the hole 4b to be formed is removed. Then, the resist film 11 is used as a mask to etch the insulating film 4 to form the groove 4a and the hole 4b, and a part of the diffusion regions 2 and 3 is exposed. After that, the resist film 11 is removed.

Next, as shown in FIG. 5, while covering the entire surface with a conductor so as to fill the groove 4a and the hole 4b with the conductor, a conductive film 12 is formed on the entire surface of the substrate 1. As the conductor, for example, W (tungsten), Al
(Aluminum), Cu (copper), Ti (titanium), Ti
It is possible to use N (titanium nitride) or a laminate of two or more selected from these.

Next, as shown in FIG. 6, a photoresist film is used to form a resist film 13 only on the regions where the wirings 7a and 7b are to be formed on the conductive film 12. And RIE
The conductive film 12 is etched by the (reactive ion etching) method. At this time, the RIE is stopped when the conductive film 12 on the insulating film 4 in the portion not covered with the resist film 13 is completely removed. As a result, the wirings 7a and 7b are formed and the embedded wiring 5 is formed. Then, by removing the resist film 13,
The wiring structure of the semiconductor device shown in is completed.

In this embodiment, the wiring 5 is connected to the insulating film 4
Since the groove 4a and the wiring 7a are formed by another photolithography process, the embedded wiring 5 and the wiring 7a can be arranged close to each other. Therefore, the chip size of the semiconductor device can be further reduced as compared with the conventional one. The groove 4a is formed at the same time as the contact hole 4b, and the conductor is embedded in the groove 4a and the wirings 7a and 7b are formed.
Since the formation of the conductive film 12 for forming is simultaneously performed, an increase in the number of steps can be avoided.

(Second Embodiment) FIG. 7 is a plan view showing a second embodiment of the wiring structure of a semiconductor device of the present invention, and FIG. 8 is a sectional view taken along line BB of FIG. Diffusion regions 2 and 3 are formed on the surface of the semiconductor substrate 1 in parallel with each other.
An insulating film 4 is formed on the substrate 1. This insulating film 4
The contact hole 4b and the diffusion regions 2 and 3 when viewed from above.
A groove 4a extending in a direction orthogonal to the buried wiring 5a and the plug 5b is formed by a conductor (for example, W, Al, Cu, Ti and TiN) embedded in the groove 4a and the hole 4b. Are formed. The diffusion regions 2 and 3 are electrically connected by the embedded wiring 5a.

An insulating film 8 is further formed on the insulating film 4. The insulating film 8 has a buried wiring 5a when viewed from above.
Grooves 8a and 8b extending in a direction parallel to are formed.
Then, the conductors (for example, W, Al, Cu, Ti, and TiN) embedded in the grooves 8a and 8b form the embedded wirings 7c and 7d, and the embedded wiring 7c is diffused through the plug 5b. 2 is electrically connected.

The method of forming the wiring structure of the semiconductor device of this embodiment will be described below with reference to FIGS. Since the steps up to the step shown in FIG. 5 are the same as those in the first embodiment, the subsequent steps will be described. After forming the conductive film 12 as shown in FIG. 5, the conductive film 12 on the insulating film 4 is removed by RIE to leave the conductor only in the trenches 4a and the holes 4b as shown in FIG. , The embedded wiring 5a and the plug 5b are obtained. The embedded wiring 5
The a may be formed by the polishing method instead of the so-called etch back method.

Next, as shown in FIG. 10, after forming an insulating film 8 on the entire surface of the substrate 1, a photoresist film 13 is formed on the insulating film 8 and, after exposure and development steps, grooves 8a, 8 are formed.
b A portion corresponding to the area to be formed is opened. Then, the insulating film 8 is etched using the resist film 13 as a mask to form the grooves 8a and 8b. After that, the resist film 1
3 is removed.

Then, as shown in FIG. 11, the grooves 8a, 8
A conductor is embedded in b, and a conductor is deposited on the insulating film 8 to form the conductive film 14. After that, the conductive film 14 on the insulating film 8 is removed by the RIE method, and the conductor is left only in the trenches 8a and 8b.
c, 7d are formed. As a result, the wiring structure of the semiconductor device shown in FIGS. 7 and 8 is completed.

Also in this embodiment, since the wiring 5a is embedded in the insulating film 4a and the groove 4a and the wiring 7c are formed in separate steps, the wiring 5a and the wiring 7c can be arranged close to each other. As a result, high integration of the semiconductor device can be achieved, and an increase in manufacturing process can be avoided. Furthermore, the insulating film 4,
8 is flattened. (Third Embodiment) FIG. 12 is a plan view showing a wiring structure of a semiconductor device according to a third embodiment of the present invention, and FIG.
It is sectional drawing by the CC line of 2.

Diffusion regions 2 and 3 are formed on the surface of the semiconductor substrate 1 in parallel with each other. An insulating film 4 is formed on the substrate 1. The insulating film 4 is provided with a contact hole 4b and a groove 4a extending in a direction orthogonal to the diffusion regions 2 and 3 when viewed from above. The conductor embedded in the groove 4a and the contact hole 4b. (For example, W, A
1, Cu, Ti, TiN, etc.)
a and the plug 5b are formed. The diffusion regions 2 and 3 are electrically connected by the embedded wiring 5a.

A wiring 7f extending in a direction parallel to the embedded wiring 5a when viewed from above and a rectangular isolated pattern 7e connected to the plug 5b are formed on the insulating film 4. The insulating film 8 is formed on the entire surface of the insulating film 4. A contact hole 8c is formed in a region of the insulating film 8 on the isolated pattern 7e, and a conductor is embedded in the contact hole 8c to form a plug 9.

A wiring 10 is formed on the insulating film 8 and extends in a direction parallel to the embedded wiring 5a when viewed from above.
The wiring 10 is electrically connected to the diffusion region 2 on the surface of the substrate 1 via the plug 9, the isolated pattern 7e, and the plug 5b. Hereinafter, a method for forming the wiring structure of the semiconductor device of this embodiment will be described with reference to FIGS. Since the steps up to the step shown in FIG. 9 are the same as those in the second embodiment, the subsequent steps will be described.

After the buried wiring 5a and the plug 5b are formed as shown in FIG. 9, a conductive film is formed on the entire surface and the conductive film is patterned by photolithography as shown in FIG. 14 to form an isolated pattern 7e. And the wiring 7f is formed. At this time, the isolated pattern 7e is connected to the plug 5b. Next, as shown in FIG. 15, an insulating film 8 is formed on the entire surface so as to cover the isolated pattern 7e and the wiring 7f, and a photoresist 15 is formed on the insulating film 8. Then, the resist film portion corresponding to the region where the contact hole 8c is to be formed is opened through the exposure and development steps,
The insulating film 8 is etched using the resist film 15 as a mask to form a contact hole 8c. Then, the resist film 15 is removed.

Next, the contact hole 8c is filled with a conductor to form the plug 9, a conductive film is formed on the insulating film 8, and the conductive film is patterned by the photolithography method to form the wiring 10. As a result, the wiring structure of the semiconductor device shown in FIGS. 12 and 13 is completed. Also in this embodiment, the same effects as those of the first and second embodiments can be obtained.

(Fourth Embodiment) FIG. 16 shows a fourth embodiment of the present invention.
A plan view showing the wiring structure of the semiconductor device according to the embodiment of
FIG. 17 is a sectional view taken along the line DD of FIG. Diffusion regions 2 and 3 are formed on the surface of the semiconductor substrate 1 in parallel with each other, and an insulating film 4 is formed on the substrate 1. A contact hole 4b and a groove 4a extending in a direction orthogonal to the diffusion regions 2 and 3 when viewed from above are formed in the insulating film 4, and a conductor (the conductor embedded in the groove 4a and the hole 4b ( For example, the embedded wiring 5a and the plug 5b are formed of W, Al, Cu, Ti, TiN, or the like. The diffusion regions 2 and 3 are electrically connected to each other via the embedded wiring 5a.

On the insulating film 4, a wiring 7f extending in a direction parallel to the embedded wiring 5a when viewed from above is formed.
An insulating film 8 is formed on the insulating film 4.
A contact hole 8c is formed in the insulating film 8 at a position aligned with the plug 5b. Then, a conductor is embedded in the hole 8c to form the plug 9. A wiring 10 is formed on the insulating film 8, and the wiring 10 is electrically connected to the diffusion region 2 on the surface of the substrate 1 via the plugs 9 and 5b.

The method for forming the wiring structure of the semiconductor device according to this embodiment will be described below with reference to FIGS. Since the steps up to the step shown in FIG. 9 are the same as those in the second embodiment, the subsequent steps will be described. After forming the embedded wiring 5a and the plug 5b as shown in FIG. 9, a conductive film is formed on the entire surface and the conductive film is patterned by photolithography to form a wiring 7f, as shown in FIG.

Next, as shown in FIG. 19, an insulating film 8 is formed on the entire surface so as to cover the wiring 7f, and a photoresist film 16 is formed on the insulating film 8. Then, through the exposure and development steps, the resist film 16 on the region where the contact hole 8c is to be formed is opened. After that, the contact hole 8c is formed by etching the insulating film 8 using the resist film 16 as a mask. After that, the resist film 16 is removed.

Next, a conductor film is formed on the entire surface so as to fill the contact hole 8c, and then the conductor film on the insulating film 8c is removed by etching to form the contact hole 8c.
The plug 9 is formed by leaving the conductor only inside. After that, a conductive film is formed on the entire surface, and the conductive film is patterned by a photolithography method to form the wiring 10.
To form As a result, the wiring structure of the semiconductor device shown in FIGS. 16 and 17 is completed. Also in the present embodiment, the first
~ The same effect as that of the third embodiment can be obtained.

(Fifth Embodiment) FIG. 20 shows the SR of the present invention.
FIG. 21 is a plan view showing an example applied to the wiring structure of the AM cross-couple section, and FIG. 21 is a circuit diagram of the SRAM. Also,
22 to 24 are cross-sectional views showing the manufacturing process seen from the cross section taken along the line EE of FIG. First, steps required until a plane structure as shown in FIG. 20 is formed will be described.

On the silicon semiconductor substrate 31, the N well 3
2 and P well 33 are adjacent. This N well 3
A field insulating film 34 made of SiO ₂ is formed on the surfaces of 2 and the P well 33 by a selective oxidation method.
Then, in the N well 32, the field insulating film 3
4, the first active region 35 is partitioned into a substantially T-shape when viewed from above, and in the P-well 33, the field active film 34 partitions the second active region 36 into a substantially U-shape viewed from above. ing. First and second active regions 3
5 and 36 are in a positional relationship such that the U-shaped bottom portion and the T-shaped head portion face each other with a gap.

The load transistor Q of the SRAM shown in FIG. 21 is formed in the first active region 35 by the following steps.
_Two p-type MOS transistors serving as ₁ and Q ₂ are formed, and drive transistors Q ₃ and Q are formed in the second active region 36.
₄ and _four n-type MOS transistors serving as transfer transistors Q ₅ and Q ₆ are formed. The gate electrode of the CMOS inverter forming the SRAM cell is formed by the following steps.

After cleaning the surfaces of the N well 32 and P well 33 existing in the first and second active regions 35 and 36 with hydrofluoric acid or the like, the surfaces are thermally oxidized to form a gate insulating film made of SiO _2. 37 is formed to a thickness of 5 to 10 nm. After that, a conductive polycrystalline silicon film (not shown) is formed on the entire surface to a thickness of 15 to 25 nm, and a SiO ₂ film is formed to a thickness of 10 to 100 nm on this silicon film by the CVD method.

Subsequently, the silicon film and the SiO ₂ film are patterned by a photolithography method to form two stripe-shaped dual gate patterns 38, 3 passing through the first active region 35 and the second active region 36.
9 are formed separately from each other, and a word line pattern 40 is formed. The dual gate patterns 38 and 39 cross the region corresponding to the T-shaped horizontal line of the first active region 35 at right angles, and straddle the region corresponding to the U-shaped underline of the second active region 36. Is arranged as. In addition, the word line pattern 40 passes through the regions corresponding to the two U-shaped vertical lines in the second active region 36,
Moreover, they are arranged so as to extend in the direction orthogonal to the dual gate patterns 38 and 39. Also, the dual gate pattern 38 has a convex portion 38 a protruding toward the dual gate pattern 39 on the P well 33, and the dual gate pattern 39 has a convex portion 39 a protruding toward the dual gate pattern 38 in the N well 32. Have on.

The portions of the dual gate patterns 38 and 39 that overlap the first active region 35 function as the gate electrodes of the load transistors Q ₁ and Q ₂ shown in FIG. 21, and also overlap the second active region 36. The portion functions as the gate electrodes of the drive transistors Q ₃ and Q ₄ . Further, a portion of the word line pattern 40 overlapping the second active region 36 functions as a gate electrode of the transfer transistors Q ₅ and Q ₆ .

Thus, the dual gate pattern 3
After forming 8, 39, the step of forming the source / drain regions of the MOS transistor is started. That is, a photoresist pattern is applied to the entire surface of the substrate, and the photoresist is exposed and developed to form a resist pattern for covering the P well 33. Then, dual gate pattern 3
P-type impurities such as boron are ion-implanted into the first active region 35 by using 8 and 39 as masks, and the sources of the transistors Q ₁ and Q ₂ are implanted into the first active regions 35 on both sides of the dual gate patterns 38 and 39. -Form a drain region.

Next, a new resist is used to selectively cover the region of the N well 32. Then, using the dual gate patterns 38 and 39 and the word line pattern 40 as a mask, the second active region 36 is ion-implanted with an n-type impurity such as arsenic or phosphorus, and the dual gate patterns 38 and 39 and the word line pattern 40 are implanted. a second active region 36 on both sides to form the source and drain regions 41 of the transistor Q ₃ to Q ₆ of.

The transistors Q _{1 to} Q ₆ may have an LDD structure. In this case, a p-type impurity or an n-type impurity is implanted at a low concentration into the first and second active regions 35 and 36 on both sides of the dual gate patterns 38 and 39 and the word line pattern 40, and then the dual gate patterns 38 and 39. 39 and sidewalls are formed on both sides of the word line pattern 40, p-type impurities or n-type impurities are formed on the first and second active regions 35 and 36 on both sides of the dual gate patterns 38 and 39 and the word line pattern 40 again. Is highly ion-implanted.

In this way, the load transistors Q ₁ ,
After forming Q ₂ , the driving transistors Q ₃ and Q ₄ and the transfer transistors Q ₅ and Q ₆ , the process moves to the step of forming a local interconnect (local wiring). First, FIG.
As shown in FIG. 5, a part of the insulating film 43 on the convex portions 38a, 39a of the dual gate patterns 38, 39 is removed to open a window 43a exposing the silicon layer. Then, a 40 nm thick cobalt (Co) or titanium (Ti) film is formed on the entire surface by sputtering. After that, the entire substrate is
N-well 32, P-well 3 by heating to 00-700 ° C
3 and the silicon constituting the dual gate patterns 38 and 39 are reacted with cobalt or titanium. Thus, a salicide on the surface of the source-drain region 41 of the portion of the window 43a of the dual gate patterns 38, 39 and the transistor Q ₁ ~Q ₆ (CoSi ₂ or TiSi ₂₎
The film 44 is formed.

In order to stabilize the reaction between cobalt or titanium and silicon, a titanium nitride film may be formed as a cap film on the cobalt or titanium film. Next, as shown in FIG. 23, as the etching stopper layer 45, for example, Al ₂ O ₃ or S is formed on the entire surface.
An iN film is formed to a thickness of about 15 nm.

Next, SiO ₂ is deposited on the entire surface to a thickness of 250 nm by the CVD method, and further SOG (Spin-On-
An insulating film 46 having a flattened surface is obtained by applying (Glass). Instead of such an insulating film 46, chemical polishing or BPSG (Boron-doped Silicate Glas) is used.
s) An insulating film having a flat surface may be formed by reflow.

Thereafter, a resist is patterned on the insulating film 46, and the insulating film 46 is etched by, for example, an etching solution containing HF as a main component to form contact holes 46c and trenches 46a and 46b for embedded wiring. These grooves 46a and 46b are portions outside the dual gate patterns 38 and 39 as viewed from above and extending in parallel with the dual gate patterns 38 and 39, and the other dual gate pattern straddling the dual gate patterns 38 and 39. 38 and 39, and has a substantially T-shape when viewed from above. The width of the grooves 46a and 46b is
For example, it is set to 0.3 μm. This etching stops when the etching stopper layer 45 is exposed.

After that, the etching stopper layer 45 in the grooves 46a and 46b and the plug hole 46c is selectively removed by sputter etching. Next, as shown in FIG. 24, a TiN (or Ti and TiN) film 47 is formed in a thickness of 50 nm on the portions where the embedded wirings 48 and 49 and the plug 50 are to be formed, by a sputtering method.

Thereafter, the grooves 46a, 46 are formed by the CVD method.
b and the hole 46c are filled with tungsten (W) to form the buried wirings 48 and 49, and the insulating film 46 is formed.
Tungsten is deposited thereon to a thickness of 300 nm to form a tungsten film. Then, this tungsten film is patterned to form an isolated pattern 51. At this time, in the logic portion which is formed on the substrate at the same time as the memory cell, the tungsten film on the insulating film 46 is simultaneously patterned to form the wiring.

After that, an interlayer insulating film 55 is formed on the entire surface, and then a via hole 55a is formed on the isolated pattern 51,
Tungsten is embedded in the via hole 55a to form a plug 56. Then, TiN is formed on the interlayer insulating film 55.
A laminated body of / Al / Ti (100 nm / 600 nm / 50 nm) is formed, and the laminated body is patterned by the photolithography method to form the wiring 57. In this way, the SRAM having the embedded wirings 48 and 49 in the cross couple portion is completed.

By the way, in this embodiment, the groove 46 is
When forming a and 46b and the contact hole 46c, Al ₂ O ₃ or Si is used as the etching stopper layer 45 in advance.
Since the N film is formed in advance, the etching of the insulating film 46 stops when the etching stopper layer 45 is exposed. This makes it easier to set etching conditions,
Over-etching and under-etching can be avoided.

Further, the wirings 48, 49 of the cross couple portion
Are embedded in the insulating film 46, the upper portion of the cross-couple portion is flattened. Furthermore, the embedded wirings 48, 4
Since 9 can be formed at the same time as the wiring of the logic part formed on the same substrate, it is possible to avoid an increase in the number of manufacturing processes. In addition, in each of the above-described embodiments, the case where the embedded wiring connects between the plurality of conductive layers (diffusion regions or wirings) arranged therebelow has been described, but the present invention is not limited to this. The embedded wiring may connect a plurality of conductive layers arranged above the embedded wiring,
Further, the conductive layer arranged below the conductive layer may be connected to the conductive layer arranged above.

[0050]

As described above, according to the present invention,
Since the embedded wiring is formed so as to be embedded in the groove provided in the insulating film, the embedded wiring and the second wiring on the insulating film can be arranged close to each other, and Higher integration can be achieved. Further, according to the present invention, since the embedded wiring and the conductive film to be the second wiring can be formed in the same step, an increase in manufacturing steps can be avoided. Further, there is an advantage that the embedded wiring is flattened.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment of a wiring structure of a semiconductor device of the present invention.

FIG. 2 is a sectional view taken along the line AA of FIG.

FIG. 3 is a view (No. 1) showing the method for forming the wiring structure of the semiconductor device according to the first example.

FIG. 4 is a diagram (No. 2) showing the method for forming the wiring structure of the semiconductor device according to the first example.

FIG. 5 is a view (No. 3) showing the method for forming the wiring structure of the semiconductor device according to the first example.

FIG. 6 is a view (No. 4) showing the method for forming the wiring structure of the semiconductor device according to the first example;

FIG. 7 is a plan view showing a second embodiment of the wiring structure of the semiconductor device of the present invention.

FIG. 8 is a sectional view taken along line BB of FIG. 7;

FIG. 9 is a view (No. 1) showing the method for forming the wiring structure of the semiconductor device according to the second example.

FIG. 10 is a diagram (No. 2) showing the method for forming the wiring structure of the semiconductor device according to the second example.

FIG. 11 is a view (No. 3) showing the method for forming the wiring structure of the semiconductor device according to the second example.

FIG. 12 is a plan view showing a wiring structure of a semiconductor device according to a third embodiment of the present invention.

13 is a sectional view taken along the line CC of FIG.

FIG. 14 is a view (No. 1) showing the method for forming the wiring structure of the semiconductor device according to the third example.

FIG. 15 is a diagram (No. 2) showing the method for forming the wiring structure of the semiconductor device according to the third example.

FIG. 16 is a plan view showing a wiring structure of a semiconductor device according to a fourth embodiment of the present invention.

17 is a cross-sectional view taken along the line DD of FIG.

FIG. 18 is a view (No. 1) showing the method for forming the wiring structure of the semiconductor device according to the fourth example;

FIG. 19 is a diagram (No. 2) showing the method for forming the wiring structure of the semiconductor device according to the fourth example;

FIG. 20 is a plan view showing a fifth embodiment in which the present invention is applied to a wiring structure of a cross-couple section of SRAM.

FIG. 21 is a circuit diagram of the SRAM.

FIG. 22 is a view (No. 1) showing the process of manufacturing the semiconductor device having the wiring structure according to the fifth example.

FIG. 23 is a view (No. 2) showing the process of manufacturing the semiconductor device having the wiring structure according to the fifth example.

FIG. 24 is a view (No. 3) showing the process of manufacturing the semiconductor device having the wiring structure according to the fifth example.

FIG. 25 is a plan view showing an example of a wiring structure of a conventional semiconductor device.

26 is a cross-sectional view taken along the line FF of FIG.

[Explanation of symbols]

 1, 31 substrate 2, 3 diffusion region 4, 8, 43, 46, 55 insulating film 4a, 8a, 8b groove 4b, 8c, 74a, 74b, 74c hole 5, 5a, 7c, 7d, 48, 49 embedded wiring 6 , 5b, 9, 50, 75a, 75b, 75c Plugs 7a, 7b, 7f, 10 Wiring 7e Isolated pattern 11, 13, 15, 16 Photoresist film 12, 14 Conductive film 32 N well 33 P well 34 Field insulating film 35 , 36 Active region 38, 39 Dual gate pattern 40 Word line pattern 43a Window 44 Salicide film 45 Etching stopper layer

Claims (5)

[Claims] 1. An insulating film formed on a semiconductor substrate, a buried wiring embedded in a groove provided in the insulating film, and a second wiring formed on the insulating film, The wiring structure of a semiconductor device, wherein the embedded wiring electrically connects two conductive layers at different positions when viewed from above. 2. The wiring structure of a semiconductor device according to claim 1, wherein the embedded wiring electrically connects the wiring below the embedded wiring and the wiring above the embedded wiring. 3. The embedded wiring is arranged so as to intersect with one of a pair of dual gate patterns serving as gates of a load transistor and a drive transistor of an SRAM,
2. The wiring structure for a semiconductor device according to claim 1, wherein the other dual gate pattern and the transfer transistor are connected to each other. 4. A step of forming an insulating film on a semiconductor substrate, a step of forming a groove in the insulating film to expose two conductive layers at different positions when viewed from above, and a conductor in the groove. And a buried wiring is formed to form a second wiring on the insulating film, and a method for forming a wiring structure of a semiconductor device. 5. A step of forming an etching stopper layer under the insulating film using a material having an etching rate lower than that of the insulating film with respect to an etchant used for forming the groove. Item 5. A method for forming a wiring structure of a semiconductor device according to Item 4.