JPH08288407A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide a semiconductor memory device and a method for the manufacture thereof wherein accurate contact is simply obtained with the diffusion layer of MOS transistors. CONSTITUTION: The semiconductor memory device consists of NMOS transistors 13, 14; a silicon oxide film 45 as a first planarization insulating film; a TFT 15 formed on the silicon oxide film 45; another silicon oxide film 57 as a second planarization insulating film; and laminated aluminum traces 17 on the silicon oxide film 57. A polycrystalline silicon layer 41b (contact plug) having a T-shaped vertical cross section that extends to the source and drain regions (diffusion layer) of the MOS transistors through the silicon oxide film 45, is connected to the laminated aluminum traces 17 through a metal plug 60. A polysilicon layer 41a as ground wiring formed in the upper regions of the NMOS transistor 14 is excellent in planarity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as SRAM (Static Random Access Memory) and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory device of this type, for example, an SRAM device, a diffusion layer as a source / drain of an access transistor in a memory cell region and a first metal wiring layer (aluminum wiring etc.) as a bit line. It was difficult to form a contact that directly connects the (1) and (3) because the aspect ratio is high (contact height / contact width). Therefore, a conductive layer (polycrystalline silicon layer or the like) is formed so as to be connected to the diffusion layer, and a contact that connects the diffusion layer and the metal wiring layer is formed via this conductive layer.

[0003]

However, in order to form a contact with the conductive layer in a fine pattern by the lithography technique, it is necessary to suppress misalignment between the conductive layer and the contact, and it is necessary to change the design rule or alignment. It is necessary to improve accuracy. However, it is difficult to improve the alignment accuracy with the current lithographic technology, and changing the design rule is against the trend of chip miniaturization because it increases the size of the memory cell. is there.

The present invention has been made in view of the above problems, and its problem is to prevent the diffusion layer of a MOS transistor from being changed without changing the design rule and without requiring special alignment accuracy in the lithography technique. It is an object of the present invention to provide a semiconductor memory device capable of making a contact accurately and easily and a manufacturing method thereof.

[0005]

According to another aspect of the present invention, there is provided a semiconductor memory device including: a MOS transistor formed on a substrate; and a first interlayer insulating film formed to cover the entire surface including the MOS transistor. A conductive layer having a T-shaped vertical cross-sectional shape formed so as to penetrate the first interlayer insulating film to reach a diffusion layer as a source / drain region of the MOS transistor, and the conductive layer and the first interlayer. A second interlayer insulating film formed to cover the entire surface including the insulating film and a second interlayer insulating film penetrating the second interlayer insulating film and reaching a contact pad formed on the upper surface of the conductive layer. And a metal wiring layer formed on the metal plug so as to be electrically connected to the metal plug.

A method of manufacturing a semiconductor memory device according to a second aspect of the present invention comprises a step of forming a MOS transistor on a substrate,
A step of forming a first interlayer insulating film so as to cover the entire surface including the MOS transistor, and a step of penetrating the first interlayer insulating film to reach a diffusion layer as a source / drain region of the MOS transistor. A step of forming a conductive layer having a mold vertical cross-section, a step of forming a second interlayer insulating film so as to cover the entire surface including the conductive layer and the first interlayer insulating film, and the second interlayer Forming a metal plug through the insulating film to reach the bit contact pad formed on the upper surface of the conductive layer; and forming a metal wiring layer on the metal plug so as to be electrically connected to the metal plug. And a step of forming.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, wherein a pair of first conductivity type access Ms are provided on a substrate.
A step of forming an OS transistor and a pair of driver MOS transistors, a step of forming a first planarization insulating film on the entire surface including these MOS transistors, and an etching on the entire surface of the first planarization insulating film. A step of forming a first conductive layer as a stop layer and a groove penetrating the first conductive layer and reaching a predetermined depth of the first planarization insulating film are formed in the source / source of the access MOS transistor. Simultaneously forming in the upper region of the diffusion layer as the drain and in the upper region of the driver MOS transistor, and penetrating the first planarization insulating film remaining at the bottom of the groove formed in the upper region of the diffusion layer. Forming a contact hole reaching the diffusion layer, and forming a second conductive layer on the entire surface so as to cover the groove and the contact hole, and A contact plug having a T-shaped vertical cross-section with respect to the diffusion layer and the driver are formed by performing an etch-back process for removing the second conductive layer except the inside of the contact hole and the first conductive layer to planarize the entire surface. Of simultaneously forming a flattened wiring pattern in the upper region of the MOS transistor for use, a step of forming an interlayer insulating film on the entire surface including the contact plug and the wiring pattern, and an interlayer in the upper region of the wiring pattern. Forming a pair of second conductive type thin film transistors on the insulating film; forming a second planarizing insulating film over the entire surface including these thin film transistors; and the second planarizing insulating film and the interlayer. Forming a metal plug penetrating the insulating film and reaching the contact plug, and forming a metal plug on the metal plug so as to be electrically connected to the metal plug. And a step of forming a wiring layer.

[0008]

In the semiconductor memory device according to claim 1 or the method for manufacturing a semiconductor memory device according to claim 2, a T-shaped vertical cross-sectional shape which penetrates the first interlayer insulating film covering the MOS transistor and reaches the diffusion layer thereof. Is provided, and the upper surface (contact pad) of the conductive layer and the metal wiring layer are connected by a metal plug.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, wherein an etch stop layer (first conductive layer) is formed on a first planarization insulating film that covers a MOS transistor and then the access MOS transistor is formed. Grooves are simultaneously formed in the etch stop layer and the first planarization insulating film in the upper region of the diffusion layer and the driver MOS transistor. Regions other than these trenches are masked with an etch stop layer to protect portions other than the trench regions when forming contact holes to the diffusion layer. Then, these trenches and contact holes are filled with the second conductive layer, and then the entire surface is flattened. As a result, the contact plug having a T-shaped vertical cross-section with respect to the diffusion layer and the flattening of the upper region of the driver MOS transistor are flattened. The wiring pattern is formed at the same time. Then, a thin film transistor is formed on the interlayer insulating film covering them, and further a second flattening insulating film and a metal wiring layer are respectively formed. The metal wiring layer and the contact plug are electrically connected by a metal plug penetrating the second planarization insulating film and the interlayer insulating film.

The device structure and manufacturing method of the present invention are applied to, for example, an SRAM device.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. Here, an SRAM device will be described as an example of the semiconductor memory device.

FIG. 1 shows a sectional structure of an SRAM device according to an embodiment of the present invention, and FIG. 2 shows a circuit structure of the SRAM device. In FIG. 2, symbol WL indicates a word line, symbols BL and / BL indicate a bit line, a bit bar line, symbol Vdd indicates a power line, and symbol Vss indicates a ground line.

This SRAM device includes a memory cell formation region 11 and a peripheral circuit portion (not shown). In the memory cell formation region 11, an NMOS transistor 13 (13 ') which is an access MOS transistor and a gate
N is a diffusion region self-aligned driver transistor
A MOS transistor 14 (14 ') and a P-type TFT 15 (15') as a load transistor are formed,
The peripheral circuit section (not shown), a polycrystalline silicon layer and the power source line contact between the P ⁺ -type impurity region, and the contact electrode as plug region for P ⁺ -type impurity regions, laminated aluminum wiring layer as a power supply line (Vdd) Are formed. Each of these portions is formed using the silicon base 21 as a substrate.

Silicon substrate 2 in memory cell forming region 11
1, a P-type well region 23 is formed, and on the P-type well region 23 and the silicon substrate 21 of the peripheral circuit portion, a device isolation region (LOCOS (Local Oxidati
A silicon oxide film 22 is formed as an on of Silicon region). An NM having a so-called LDD (Lightly Doped Drain) structure is formed on the P-type well region 23 of the memory cell formation region 11 partitioned by the silicon oxide film 22.
The OS transistor 13 is formed. That is, P
Silicon oxide film 24 formed on the mold well region 23
A polycide layer 27 as a gate electrode of the NMOS transistor is formed via the (gate insulating film), and the P-type well region 2 adjacent to the patterned gate electrode 2 is formed.
3 is a low concentration impurity diffusion region near the surface of N ^{− 3.}
A type impurity region 29 is formed. A silicon oxide film side wall 35 is formed on the side surface of the polycide layer 27 as the gate electrode.
Is formed, and an N ⁺ -type impurity region 36 which is a high-concentration impurity diffusion region is formed near the surface of the P-type well region 23 in a self-aligned manner.

A silicon oxide film 38 as an interlayer insulating film is formed on the polycide layer 27. NMO
On the silicon oxide film 38 in the upper region of the S transistor 14, a flat polycrystalline silicon layer 41a (second conductive layer) as a ground (Vss) line extending in the direction perpendicular to the paper surface penetrates the silicon oxide film 45. Is provided. Also,
Source / drain region (N
^{In the +} type impurity region 36), a polycrystalline silicon layer 41b (second conductive layer) having a T-type vertical cross-sectional shape that penetrates the silicon oxide film 45 and reaches the N ⁺ type impurity region 36 is formed at the same time as the Vss line. Is formed, and constitutes a contact plug for leading out the bit line. Then, a silicon oxide film (SiO ₂ ) 48 as an interlayer insulating film is formed so as to cover these. The silicon oxide film 48 and the silicon oxide film 4
5 through the diffusion layer (N
⁺ Type impurity region 36 and N ⁻ type impurity region 29) and N
A shared contact opening 46 for simultaneously making contact with the gate electrode layer (polycide layer 27) of the MOS transistor 14 is formed.

Polycrystalline silicon layer 41 as Vss line
TF is formed on the silicon oxide film 48 in the region where a is formed.
A polycrystalline silicon layer 47 to be the gate electrode of T15 is formed. This polycrystalline silicon layer 47 is shared
With respect to the polycide layer 27 serving as the gate electrode of the NMOS transistor 14 and the diffusion regions (N ⁻ type impurity region 29 and N ⁺ type impurity region 36) serving as the source / drain regions of the NMOS transistor 13 extending to the contact opening 46. Connected at the same time.

A silicon oxide film 52 having an opening 53 in a part thereof is formed on the polycrystalline silicon layer 47, and a polysilicon film as a channel region, a source / drain region and a power supply (Vdd) line of the TFT 15 is further formed thereon. A crystalline silicon layer 56 is formed and connected to the polycrystalline silicon layer 47 at the opening 53.

Then, a silicon oxide film 57 as a second flattening insulating film is formed so as to cover the above element structure.

Contact plugs (polycrystalline silicon layer 4) are formed in the silicon oxide films 57, 52 and 48 so as to penetrate them.
1b), a contact hole 58 reaching the upper surface (contact pad) of the titanium / titanium nitride layer 61 is formed.
And a tungsten layer 62 are filled with the metal plug 60. Then, the tungsten layer 62 is
Titanium / titanium nitride layer 63, aluminum layer 6
4 and the titanium nitride layer 65 are connected to the first layer laminated aluminum wiring 17 of a predetermined pattern.

In the SRAM device of the present embodiment, a T-type vertical section that penetrates the silicon oxide film 45 (first interlayer insulating film) covering the NMOS transistor 13 to reach its source / drain region (N ⁺ -type impurity region 36). A planar-shaped polycrystalline silicon layer 41b (second conductive layer, bit line lead-out contact plug) is provided, and the polycrystalline silicon layer 41 is provided.
A metal plug 60 connects between the upper surface (contact pad) of b and the metal wiring layer 17. Therefore, the contact pad surface is wide, and a sufficient alignment margin can be secured when the contact pad surface is connected to the metal wiring layer 17 by the metal plug 60. In addition, the aspect ratio of the contact plug does not need to be higher than in the case where the diffusion layer is directly contacted, which facilitates manufacturing.

Next, a method of manufacturing the SRAM device having the above structure will be described.

First, as shown in FIG. 3, a silicon oxide film 22 having a thickness of about 400 nm is selectively formed on the surface of an N-type silicon substrate 21 by the LOCOS method. As a result, an element isolation region in which the silicon oxide film 22 is formed and an element active region surrounded by the silicon oxide film 22 are divided.

Next, as shown in FIG. 4, after boron (B) is selectively ion-implanted into the silicon substrate 21 to form the P-type well region 23, a silicon oxide film 24 as a gate insulating film is formed. Are formed on the surface of the element active region. Then, the polycide layer 27 is formed by sequentially depositing a polycrystalline silicon layer 25 having a thickness of about 70 to 150 nm and a silicide layer such as a tungsten silicon layer 26 by a CVD (Chemical Vapor Deposition) method or a sputtering method. Then, the polycide layer 27 is patterned to form the gate electrodes of the NMOS transistors 13 and 14. The polycide layer 27 in the peripheral circuit portion (not shown) is removed. Then, in the memory cell formation region 11, the N ⁻ type impurity region 29 is formed in self-alignment with the gate electrode. That is, a portion of the memory cell formation region 11 other than the source / drain formation region 28 is covered with a resist (not shown), and arsenic (A _S ) is used as a mask.
Is ion-implanted to form a low concentration N ⁻ -type impurity region 29. Similarly, boron is ion-implanted into a power line contact portion region of a peripheral circuit portion (not shown) to form a low concentration P ⁻ -type impurity region.

Next, as shown in FIG. 5, CVD is performed on the entire surface.
After a silicon oxide film is deposited by the method, it is anisotropically etched to form a silicon oxide film side wall 35 on the side surface of the polycide layer 27 as a gate electrode, and further in self-alignment with the silicon oxide film side wall 35. A high concentration N ⁺ type impurity region 36 is formed. That is, the memory cell formation region 1
A portion other than the source / drain formation region 28 of No. 1 is again covered with a resist (not shown), and high-concentration arsenic is ion-implanted by using this resist and the side wall 35 of the silicon oxide film as a mask to form the N ⁺ -type impurity region 36 Form. Thus
The LDD-structured NMOS transistors 13 and 14 are formed. Similarly, high-concentration boron is ion-implanted into the power supply line contact region of the peripheral circuit portion (not shown) to form a P ⁺ -type impurity region. In the figure, the NMOS transistor 14 has source / drain regions formed in a direction perpendicular to the plane of the drawing.

Next, as shown in FIG. 6, after forming an interlayer insulating film such as a silicon oxide film 38 on the entire surface, a silicon oxide film 45 as a first flattening insulating film is formed. Specifically, by reacting O ₃ and TEOS, B is deposited by CVD.
20 PSG (Boron Phosphorus Silicate Glass) film
It is formed to a thickness of 0 to 500 nm, annealed at a temperature of 850 to 900 ° C., and flattened by reflow. As a result, the surface is sufficiently flattened. Next, a polycrystalline silicon layer 49 (first conductive layer) as an etch stop layer is formed on the entire surface of the flattened silicon oxide film 45.

Next, as shown in FIG. 7, by applying a resist 81 having a predetermined pattern on the polycrystalline silicon layer 49 and etching it, the silicon oxide film 45 and the polycrystalline silicon layer 49 are almost oxidized. Grooves 82 and 83 reaching the upper surface of the film 38 are formed. Of these, the groove 82 is N
The trench 83 is formed in the formation region of the MOS transistor 14 for the ground line, and the trench 83 is formed in the source / drain region of the NMOS transistor 13 for the contact plug. At this time, the bottom surfaces of these grooves are favorably flattened by etching.

Next, after removing the resist 58, FIG.
As shown in FIG. 6, a contact hole 85 that penetrates the silicon oxide films 45 and 38 and reaches the N ⁺ type impurity region 36 is formed in the groove 83 by applying and etching a resist 84 having a predetermined pattern. To do. At this time, even if the contact hole pattern of the resist 84 covers the area other than the groove 83 due to misalignment, the polycrystalline silicon layer 49 as the etch stop layer masks all the area other than the groove. Areas other than 83 are not etched. For this reason, the position of the contact plug is regulated by the groove 83, and self-alignment is performed.

Next, after removing the resist 84, FIG.
As shown in FIG.
A (second conductive layer) is formed on the entire surface of about 200 to 600 nm. Then, the entire surface is etched back until the polycrystalline silicon layer 49 as the etch stopper is completely removed. At this time, the polycrystalline silicon layer 41 and the polycrystalline silicon layer 49 in the portions other than the trenches 82 and 83 are uniformly removed, so that the flatness of the device surface after the etching back becomes good. Then, the grooves 82 and 83 and the contact hole 85
Phosphorus is ion-implanted into the polycrystalline silicon layer 41 which fills the gates. As a result, a polycrystalline silicon layer 41a serving as a ground line (wiring pattern) is formed in the groove 82, and at the same time, a polycrystalline silicon layer 41b serving as a contact plug having a T-shaped vertical cross-section is formed in the groove 83. To be done.

Next, as shown in FIG. 10, a silicon oxide film 45 as an interlayer insulating film is formed on the entire surface. The flatness of the formed silicon oxide film 45 is good.

Next, as shown in FIG. 11, a polycide layer 27 as a gate electrode of the NMOS transistor 13 is formed.
Further, a shared contact opening 46 for simultaneously making contact with both the diffusion layer (N ⁻ type impurity region 29 and N ⁺ type impurity region 36) as the source / drain region is formed.

Next, as shown in FIG.
The polycrystalline silicon layer 47 to be the gate electrode of
A film having a thickness of about nm is formed, and arsenic, which is an N-type impurity, is ion-implanted on the entire surface and then patterned. At this point, the shared contact opening 4
6, the electrical connection between the polycide layer 27 as the gate electrode of the NMOS transistor 14 and the polycrystalline silicon layer 47 as the gate electrode of the TFT is completed.

Next, as shown in FIG.
After forming a silicon oxide film 52 to be a gate insulating film with a film thickness of about 20 to 50 nm by CVD or the like,
An opening 53 for making contact with the gate electrode (polycrystalline silicon layer 47) of the TFT 15 is formed, and the CV is further formed.
The channel region and source of the TFT 15
The polycrystalline silicon layer 56 to be the drain region is formed with a thickness of 10-20.
After forming with a film thickness of about nm, and patterning this,
Boron, which is a P-type impurity, is ion-implanted into the polycrystalline silicon layer 56 of the source / drain region of the TFT 15 and the polycrystalline silicon layer 56 of the power supply line contact portion of the peripheral circuit portion (not shown) to form a P-type high concentration impurity region. To do.
As a result, the channel region of the TFT 15 and the power source (V
dd) Line formation is complete. By providing an offset region formed by separating the drain region from the gate and forming a low-concentration P-type region on the drain side, the drain electric field can be relaxed and the on-current does not decrease. Further, the off current can be reduced.
The polycrystalline silicon layer 56 is provided on the TFT 1 in the opening 53.
5 is connected to the polycrystalline silicon layer 47 forming the gate electrode. This polycrystalline silicon layer 56 is used as a power supply line in the memory cell formation region 11, and
It is led out to the power supply line contact region of the peripheral circuit portion (not shown), and is directly connected to the P ⁺ -type impurity region formed in the silicon substrate 21 at the bottom of the power supply line contact opening.

Next, as shown in FIG. 13, a silicon oxide film 57 as a second flattening insulating film is formed. Specifically, TEOS is reacted with O ₃ gas to form a BPSG reflow film having a thickness of about 200 to 500 nm, and then 850
Anneal at a temperature of ~ 900 ° C and planarize by reflow.

Next, a contact hole 58 for making contact with the bit line lead-out contact plug (polycrystalline silicon layer 41b) is formed. Then, after filling the contact hole 58 with a metal plug 60 made of a titanium / titanium nitride (Ti / TiN) layer 61 and the like as a barrier metal layer and an adhesion layer and a tungsten layer 62,
After forming a titanium / titanium nitride layer 63 as a barrier metal layer etc. and an aluminum layer 64 containing Cu, and further forming a titanium nitride layer 65 as an antireflection layer etc., these are patterned to form a first layer. The laminated aluminum wiring 17 (metal wiring layer) of the layer is formed. Here, since the contact plug for pulling out the bit line (polycrystalline silicon layer 41b) has a T-shaped vertical cross-sectional shape, the contact pad surface is wide, and the metal plug 60 connects the laminated aluminum wiring 17 (metal wiring layer). A sufficient alignment margin can be secured when doing.

Thus, the SRAM device shown in FIG. 1 is completed. After that, although not shown, an interlayer insulating film and a second-layer laminated aluminum wiring are formed, and a silicon nitride (Si ₃ N ₄ ) layer as an overcoat film is further formed by a plasma CVD method. Complete all manufacturing processes.

The present invention has been described with reference to the examples.
The present invention is not limited to the above embodiment, but can be variously modified. For example, in the above embodiment, the present invention is
Although the example applied to the RAM device has been described, the present invention can also be applied to other memory devices.

[0037]

As described above, in the method of manufacturing the semiconductor memory device according to claim 1 or the semiconductor memory device according to claim 2, the first interlayer insulating film covering the MOS transistor is penetrated and diffused. A conductive layer having a T-shaped vertical cross section reaching the layer is provided, and the upper surface (contact pad) of the conductive layer and the metal wiring layer are connected by a metal plug, so that the contact pad surface is wide. A sufficient alignment margin can be secured when connecting to the layer with a metal plug, and the aspect ratio of the contact plug does not need to be high compared to the case of making a direct contact with the diffusion layer, which facilitates manufacturing. Become.

In the method of manufacturing a semiconductor memory device according to the present invention, an access stop MOS transistor is formed after forming an etch stop layer (first conductive layer) on the first planarization insulating film covering the MOS transistor. Since a groove is formed in the etch stop layer in the upper region of the diffusion layer and in the upper region of the driver MOS transistor and the first planarization insulating film, regions other than these trenches are masked by the etch stop layer. . Therefore, when the contact hole to the diffusion layer is formed inside the groove in the upper region of the diffusion layer, the portion other than the groove region is protected from etching. That is, since the position of the contact plug is regulated by the groove and self-alignment is possible, the alignment margin can be reduced. Further, since the groove and the contact hole are filled with the second conductive layer and the entire surface is etched back to be flattened, the wiring pattern having good flatness is formed in the upper region of the driver MOS transistor. Therefore, even the interlayer insulating film formed thereon can have sufficient flatness for forming a thin film transistor thereon. Further, the contact plug formed so as to reach the diffusion layer has a T-shaped vertical sectional shape,
Since the upper surface is wide, a sufficient alignment margin is secured when connecting the contact plug and the metal wiring layer with the metal plug. Further, the aspect ratio of the contact plug does not have to be higher than in the case where the diffusion layer is directly contacted.

[Brief description of drawings]

FIG. 1 is a side sectional view showing an SRAM device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a circuit configuration of this SRAM device.

FIG. 3 is a side sectional view for explaining the first step of the method for manufacturing the SRAM device of FIG.

FIG. 4 is a side sectional view for explaining a step following FIG.

FIG. 5 is a side sectional view for explaining a step following FIG.

FIG. 6 is a side sectional view for explaining a step following FIG.

7 is a side sectional view for explaining a step following FIG.

FIG. 8 is a side sectional view for explaining a step following FIG.

FIG. 9 is a side sectional view for explaining a step following FIG.

FIG. 10 is a side sectional view for explaining a step following FIG.

11 is a side sectional view for explaining a step following FIG.

FIG. 12 is a side sectional view for explaining a step following FIG.

FIG. 13 is a side sectional view for explaining a step following FIG.

[Explanation of symbols]

11 memory cell formation region 13 NMOS transistor (access MOS transistor) 14 NMOS transistor (driver MOS transistor) 15 TFT (load thin film transistor) 17 laminated aluminum wiring (metal wiring layer) 21 silicon substrate 22 silicon oxide film (element isolation film) ) 23 P-type well region 24 Silicon oxide film (gate insulating film) 27 Polycide layer (NMOS transistors 13 and 14)
Gate electrode layer) 29 N ^- type impurity region (source / drain region) 36 N ⁺ type impurity region (source / drain region) 38 Silicon oxide film 41 Polycrystalline silicon layer (second conductive layer: bit line extraction contact) Plug, Vss line) 45 Silicon oxide film (first flattening insulating film) 46 Shared contact opening 47 Polycrystalline silicon layer (gate electrode layer of TFT15) 48 Silicon oxide film (interlayer insulating film) 49 Polycrystalline silicon Layer (first conductive layer: etch stop layer) 52 silicon oxide film (gate insulating film of TFT15) 56 polycrystalline silicon layer (channel, drain, Vdd line of TFT15) 57 silicon oxide film (second planarizing insulating film) )

Claims (6)

[Claims] 1. A MOS transistor formed on a substrate, a first interlayer insulating film formed to cover the entire surface including the MOS transistor, and the MOS transistor penetrating the first interlayer insulating film. A conductive layer having a T-shaped vertical cross-section formed so as to reach the diffusion layer serving as the source / drain region, and a first layer formed so as to cover the entire surface including the conductive layer and the first interlayer insulating film. A second interlayer insulating film, a metal plug formed so as to penetrate the second interlayer insulating film to reach a contact pad formed on the upper surface of the conductive layer, and a metal plug formed on the metal plug and the electrical plug And a metal wiring layer formed so as to be electrically connected to each other. 2. The semiconductor memory device according to claim 1, wherein the MOS transistor is a pair of access transistors forming an SRAM device. 3. A step of forming a MOS transistor on a substrate, a step of forming a first interlayer insulating film so as to cover the entire surface including the MOS transistor, and a step of penetrating the first interlayer insulating film. A step of forming a conductive layer having a T-shaped vertical cross-sectional shape so as to reach a diffusion layer as a source / drain region of a MOS transistor; and a step of covering the entire surface including the conductive layer and the first interlayer insulating film. Forming a second interlayer insulating film, forming a metal plug penetrating the second interlayer insulating film so as to reach a contact pad formed on the upper surface of the conductive layer, and And a step of forming a metal wiring layer so as to be electrically connected thereto. 4. The method of manufacturing a semiconductor memory device according to claim 1, wherein the MOS transistor is a pair of access transistors forming an SRAM device. 5. A step of forming a pair of first conductivity type access MOS transistors and a pair of driver MOS transistors of a first conductivity type on a substrate, and a first planarization insulating film over the entire surface including these MOS transistors. A step of forming, a step of forming a first conductive layer as an etch stop layer on the entire surface of the first flattening insulating film, and a step of penetrating the first conductive layer to form the first flattening insulating film. A step of simultaneously forming a groove reaching a predetermined depth of the film in an upper region of a diffusion layer serving as a source / drain of the access MOS transistor and an upper region of the driver MOS transistor, and forming in the upper region of the diffusion layer A step of forming a contact hole penetrating the first planarization insulating film remaining at the bottom of the formed groove and reaching the diffusion layer; After the second conductive layer is formed on the entire surface as described above, an etch-back process is performed to remove the second conductive layer excluding the inside of each groove and the contact hole and the first conductive layer to planarize the entire surface. By doing
A step of simultaneously forming a contact plug having a T-shaped vertical cross-section with respect to the diffusion layer and a flattened wiring pattern in an upper region of the driver MOS transistor, and interlayer insulation over the entire surface including the contact plug and the wiring pattern. Forming a film, forming a pair of second conductivity type thin film transistors on the interlayer insulating film in the upper region of the wiring pattern, and forming a second planarization insulating film on the entire surface including these thin film transistors. And a step of forming a metal plug penetrating the second flattening insulating film and the interlayer insulating film to reach the contact plug, and electrically connecting to the metal plug on the metal plug. A method of manufacturing a semiconductor memory device, comprising the step of forming a metal wiring layer. 6. The pair of access MOS transistors, the contact plug serving as a bit line leading contact pad and the wiring pattern serving as a ground wiring.
6. The method of manufacturing a semiconductor memory device according to claim 5, wherein the SRAM device is configured with a pair of driver MOS transistors and a pair of thin film transistors.