JP2001102541A - Semiconductor memory and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory which has a structure suitable for micro machining and its manufacturing method. SOLUTION: A contact, which is connected to a lower electrode 13 and upper electrodes 15a and 15b of a high-dielectric capacitor, is positioned directly above the source/drain region 10A1 of a semiconductor substrate. While this makes contact with at least the side face of this contact, another contact extends to the source/drain region 10A1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device having a ferroelectric memory cell and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIGS. 54 and 54 are plan views of a ferroelectric capacitor of a conventional chain type ferroelectric memory cell.
55 is a cross-sectional view taken along the line AB of FIG.

FIGS. 54 and 55 show the positional relationship between a capacitor lower electrode 540, a contact 541 to the capacitor lower electrode 540, and contacts 542a and 542b to a source / drain diffusion layer of a transistor formed below. FIG. Contact 542b is the first
Contact 542a formed in the interlayer insulating film 547 of FIG.
Is formed in the second interlayer insulating film 549. Lower electrode 5
Upper electrodes 546a and 546b are formed on both sides of the contact 541 with the contact 541 therebetween.

A gate electrode 543 of the transistor is formed in an element formation region between element isolation regions 544 formed in a semiconductor substrate 548, and contacts 541 and 542 are connected by an upper wiring layer 545.

In the conventional case shown in FIGS. 54 and 55, the first wiring layer 5
A contact 541 from the substrate 45 to the lower electrode 540 of the ferroelectric capacitor and contacts 542a and 542b from the first wiring layer 545 to the transistor are formed in separate contact holes.

In order to prevent the contact 542a from coming into contact with the lower electrode 540 of the ferroelectric capacitor due to misalignment of the mask at the time of manufacturing, the contact 54
A margin D is provided between 2a and the capacitor lower electrode 540.

In FIG. 55, on a semiconductor substrate 548, a gate 543 of a switching MOS transistor of a ferroelectric memory cell is formed. These transistors are covered with a planarized first interlayer insulating film 547 such as BPSG. Further, the first interlayer insulating layer 5
47, a thin silicon nitride film layer 551 and a thin silicon oxide film layer 552 are formed, and a lower electrode 540, a ferroelectric film (not shown) and an upper electrode 546 are further formed thereon.
a and 546b are sequentially formed to form a ferroelectric capacitor.

This ferroelectric capacitor is, for example, d-TE
Flattened second interlayer insulating film 5 made of OS or the like
Further, a first wiring layer 545 made of, for example, Al is formed on the second interlayer insulating film 549. A first-stage contact 542b is formed to penetrate the first interlayer insulating film 547.

The contact 542b is connected to the source / drain region 553 or the gate electrode 543 of the switching transistor, and the inside of the contact hole is filled with a refractory metal such as tungsten.

A second-stage contact 542a is formed so as to simultaneously penetrate the thin silicon nitride film layer 551, the thin silicon oxide film layer 552, and the second interlayer insulating film 549.

These contacts are classified into the following three types depending on the connection destination. That is, (1) a second-stage contact 542a formed so as to be directly connected to the above-described first-stage contact 542b, and (2) a second-stage contact 542a formed to be connected to the lower electrode 540 of the ferroelectric capacitor. (3) contacts (not shown) formed to connect to the upper electrodes 546a and 546b of the ferroelectric capacitor. The second-stage contact 542a is formed of a buried metal such as aluminum.

FIG. 55 shows (1) and (2) of these three contacts. In the prior art, these two contacts 541, 542a, 542b are formed in separate contact holes. A first wiring layer 545 is formed over the second interlayer insulating film 549 so as to connect to these contacts. The upper surfaces of the second interlayer insulating film 549 and the first wiring layer 545 are covered with a third interlayer insulating film 550 whose surface is flattened, and a passivation film 560 is formed above the third interlayer insulating film 550.

As described above, in the prior art, the contact 542a formed so as to be directly connected to the first-stage contact 542b and the contact 54 formed so as to be connected to the lower electrode 540 of the ferroelectric capacitor.
1 are formed in separate contact holes.

Further, a margin D is provided between the contact 542a and the lower electrode 540 of the ferroelectric capacitor. These contacts 542a and the margin D around them are
This is an obstacle to reducing the size of the memory cell, which is a problem.

As described above, in the conventional structure, the first wiring layer 5
45, a contact 541 from the lower electrode 540 of the ferroelectric capacitor, and contacts 542a, 5 from the first wiring layer 545 to the source / drain region 553 of the transistor.
Since 42b was formed in another contact hole,
The memory cell was getting bigger.

[0016]

SUMMARY OF THE INVENTION Therefore, the present invention
By reducing the distance between the electrode of the ferroelectric capacitor, the contact connected to the electrode, and the source / drain region of the transistor formed on the semiconductor substrate in the lateral direction of the semiconductor substrate, the semiconductor of the ferroelectric memory cell is reduced. It is an object of the present invention to provide a semiconductor memory device having a configuration in which the area occupied on a substrate can be reduced and the device can be further miniaturized, and a method for manufacturing the same.

[0017]

A semiconductor memory device according to the present invention comprises a plurality of transistors formed on a semiconductor substrate and a plurality of ferroelectric capacitors formed on each of the transistors. A ferroelectric memory cell, a first contact connected to a lower electrode or an upper electrode of the ferroelectric capacitor, and a second contact connected to a predetermined region of the semiconductor substrate are mutually thicker than the semiconductor substrate. And a contact hole formed so as to be connected and connected in the vertical direction.

In this configuration, for example, a contact from the first wiring layer to the lower electrode of the ferroelectric capacitor and a contact from the first wiring layer to the source / drain region of the transistor are formed in the same contact hole. With the technology, two contacts can be reduced to one, and the area of the memory cell can be reduced.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a circuit diagram of a chain type FRAM to which the present invention is applied. In FIG. 1, a plurality (eight in this case) of transistors Tr1-Tr in a memory cell block MC1
8 are connected in series. Here, the transistor Tr
1 is connected to the drain region D2 of the adjacent transistor Tr2, and a ferroelectric capacitor C is connected between the source region S1 and the drain region D1 of the transistor Tr1.
1 are connected in parallel. Similarly, the transistor Tr2
, A ferroelectric capacitor C2 is connected in parallel between the source region S2 and the drain region D2. Hereinafter, similarly, each drain region of the eight transistors Tr1 to Tr8 connected in series is connected to the source region of the adjacent transistor. In this way, the current paths of the plurality of transistors are connected in series, and the ferroelectric capacitors C1 to C8 are connected in parallel to each transistor, and the chain type FRA
An M cell block MC1 is configured.

The word lines WL1 to WL8 are connected to the gates of all the transistors. One end of the transistor circuit block MC1 having this chain configuration is connected to the bit line BL1, and the other end is connected to the power line PL.

A plurality of chain type FRs having the same configuration
AM cell blocks MC2... Are commonly connected to word lines WL1 to WL8 corresponding to bit lines BL2.

FIG. 2 is a diagram showing a unit memory cell structure of a chain type FRAM according to an embodiment of the present invention constructed corresponding to the circuit shown in FIG. 1. In this case, the ferroelectric memory shown in FIG. The portion where three transistors Tr1, Tr2, Tr3 are formed in the cell block MC1 is shown. 2 (a) is a plan view, and FIG. 2 (b) is a line AB in FIG. 2 (a).
It is sectional drawing cut | disconnected and shown along a line.

The ferroelectric memory cell of FIG. 2 is formed on one conductivity type, for example, an n-type semiconductor substrate 10. Semiconductor substrate 1
0 is the surface region of the element isolation layers 10A0, 10A1, 10A.
The source / drain regions 10A1, 10A2, 10A3 of the transistors Tr1, Tr2, Tr3 of the chain type FRAM cell block MC1 are formed in the element formation region in the direction of the chain arrangement, and are adjacent to each other. Shows source / drain regions 10B1 and 10B of another chain type FRAM cell block MC2.
2,... Are formed. These source / drain regions 10
A1, 10A2, 10A3 and 10B1, 10B2, ...
Are formed at a predetermined interval corresponding to the channel length, and the word lines WL1, WL2, W
Gate electrodes 11-1, 11-2, 11-3 as L3
Are disposed in the formation regions of the transistors Tr1, Tr2, Tr3, respectively.

On the upper layers of the gate electrodes 11-1, 11-2, 11-3 of the transistors Tr1, Tr2, Tr3, ferroelectric capacitors C1, C2 are further interposed via an interlayer insulating film 12.
2, C3 is formed. That is, the transistor Tr
1, Tr2,... Formed on the inter-layer insulating film 12 which has been subjected to the CMP process, with the lower electrode 1 interposed therebetween with the ferroelectric film 14 therebetween.
Three and two upper electrodes 15a and 15b are formed, and a lower electrode contact 13c, an upper electrode contact 15c,
15c is formed. At the same time, the lower electrode 13- is also provided in the region above the gate electrode 11-3 adjacent in the chain arrangement direction.
1. A ferroelectric film 14-1 and an upper electrode 15a-1 are sequentially formed.

Further, each of the upper electrodes 15a, 15b, 15
Wirings 15w, 15w are formed in a-1.

The lower electrode 13 has two upper electrodes 15a, 1
5b, and similarly used for the lower electrode 13-1.
Is commonly used for two upper electrodes 15a-1 (only one is shown in the figure). In the lower electrode 13, the contact 13c corresponds to the node N1 in the circuit of FIG. 1, and the contact 15c is connected to the ferroelectric capacitors C1, C, respectively.
2 correspond to the nodes N2 and N3 of FIG.

As will be described later in detail with reference to FIGS. 3 and 4, the contact 13c is connected to the lower electrode 13 and the source / drain region 10A1 via a single contact hole. This contact 13c is connected to the transistor T of FIG.
r1 and Tr2, which correspond to a common connection node N4. The source region S1 of the transistor Tr1 and the transistor Tr
2 is commonly connected to the drain region D2. Therefore, since the region 10A1 is commonly used as a source region and a drain region, it is referred to as a source drain region here.

The upper electrode contact 15c on the ferroelectric capacitor C2 side is connected to the source / drain region 10A1 adjacent to the source / drain region 10A1 via a wiring 15w as a bridge wiring between the adjacent ferroelectric capacitor C3.
A2 is connected to a contact 18 formed to connect to the transistor T2, as shown in FIG.
In this configuration, a ferroelectric capacitor C2 is connected in parallel with r2.

The contact 15c on the other ferroelectric capacitor C1 side is similarly formed with the contact 18 formed in the adjacent source / drain region 10A0 via the wiring 15w.
And a ferroelectric capacitor C1 is connected in parallel with the transistor Tr1 as shown in FIG.

As described above, another ferroelectric capacitor C3 connected in parallel to the transistor Tr3 is provided above the gate electrode 11-3 (WL3) of the transistor Tr3.
To form another lower electrode 13-1, a ferroelectric film 14
-1, the upper electrode 15a-1 is formed. The lower electrode 13-1 is connected to the transistors Tr1 and T2 with respect to the lower electrode 13 formed above the transistors Tr1 and Tr2.
The source / drain regions 10 along the direction in which
It is arranged at a predetermined interval above A2.

As described above, a similar chain FRAM cell block MC2 is formed in an adjacent element formation region formed in parallel with the element formation region in which the source / drain regions 10A1 and 10A2 are formed. .
Here, lower electrode 13-2, 1 constituting a ferroelectric capacitor is connected to chain FRAM cell block MC1.
3-3 is formed so as to be shifted so that the center thereof is located at the center of two adjacent lower electrodes. That is, another lower electrode 13-2 is disposed so as to face the gap E formed between the adjacent lower electrodes 13 and 13-1, and this lower electrode 1
3-2 at the same distance E from the other lower electrode 13-.
3 are arranged.

The gap E between the lower electrodes 13-2 and 13-3 is just opposite to the lower electrode 13, and the arrangement pattern of the lower electrodes is formed in a staggered pattern as a whole.

Hereinafter, the internal structure of the chain type FRAM cell shown in FIG. 2 will be described.

FIG. 3 shows the chain type FRAM described with reference to FIG.
FIG. 4 is a plan view showing a portion of the lower electrode 13 of the cell. FIG. 4 shows a cross-sectional structure taken along line CD of FIG. 3 and 4 show a capacitor lower electrode 13, a contact 32 to the capacitor lower electrode 13, a base transistor T
It is a figure which shows the structure of the contact 33 of r1, Tr2 to the common source-drain diffused layer 10A1, and the contact hole 13ch etc. in which these contacts 32 and 33 are formed commonly.

The source / drain diffusion layer 10A1 is formed in an element formation region separated from other elements by two element isolation regions 10S1 and 10S2.

As shown in FIG. 4, in this embodiment,
A contact 32 from the first wiring layer 13w to the common lower electrode 13 of the ferroelectric capacitors C1 and C2;
The feature is that a contact 33 from 3w to the common source / drain region 10A1 of the transistors Tr1 and Tr2 is formed in the same contact hole 13ch by metal filling.

That is, of the contacts 13c formed in the contact hole 13ch, the upper half contact 32 functions as a contact to the common lower electrode 13 of the ferroelectric capacitors C1 and C2, and the remaining lower half is the first wiring It functions as a contact 33 from the layer 13w to the common source / drain region 10A1 of the transistors Tr1 and Tr2.

The cross section of the device manufactured according to the present embodiment will be described in more detail. In FIG.
The transistors Tr1 and Tr2 that operate as charge / discharge switches of the ferroelectric capacitor are connected to the source / drain region 1
It is formed in association with 0A1. This transistor formation portion is covered with a planarized first interlayer insulating film 12 such as BPSG. The contact 33 is formed by etching a contact hole in the first interlayer insulating film 12 together with the barrier metal 33b, and filling the contact hole with a metal such as tungsten.

Although not shown in FIG. 2B for simplicity of explanation, the surface of the first interlayer insulating layer 12 has a thin silicon nitride film layer 42 and a thin silicon oxide film layer 43. Are formed thereon, and a lower electrode 13, a ferroelectric film 14, and upper electrodes 15a and 15b are sequentially formed thereon to form a ferroelectric capacitor.

This ferroelectric capacitor is, for example, d-TE
Planarized second interlayer insulating film 2 made of OSS or the like
The first wiring layer 13w such as aluminum is filled on the second interlayer insulating film 22 via a protective film 30a such as a barrier metal.

The contact hole 33h is connected to the drain / source region 10A1 of the switching transistor via the barrier metal 30b. The inside of the contact hole 33h is filled with a refractory metal such as tungsten to form a contact 33. I have.

A second-stage contact hole 32h is formed so as to simultaneously penetrate the thin silicon nitride film layer 42, the thin silicon oxide film layer 43, and the second interlayer insulating film 22.

Although not specifically shown, in the case of this device, a contact formed so as to penetrate the thin silicon nitride film layer 42, the thin silicon oxide film layer 43, and the first and second interlayer insulating films 12 and 22. There are three types of holes depending on the connection destination. That is, (1) the first-stage contact holes 18h and 33 formed so as to be directly connected to the source / drain region 10A1 of the transistor.
h, (2) Second-stage contact hole 32 formed to be connected to lower electrode 13 of the ferroelectric capacitor
h, (3) Upper electrodes 15a, 15 of ferroelectric capacitor
contact hole 1 formed to connect to
5 channels.

This second-stage contact hole 32h is
For example, it is embedded with a metal such as aluminum.

The feature of the present invention is that, of the contacts in the memory cell, the contact hole 32h formed to connect to the lower electrode 13 of the ferroelectric capacitor is formed in the source / drain region 10A1. Is formed directly above the lower electrode 13 so as to be in contact with the end of the lower electrode 13, thereby being directly connected to the first-stage contact hole 33h.

Here, the first-stage contact hole 33h
The contact holes 18h other than the contact holes 32h used for connecting the lower electrode 13 of the capacitor and the diffusion layer 10A1 of the underlying transistor among the contact holes formed so as to be directly connected to , Which will be described later.

The first wiring layer 1 is formed on the second interlayer insulating film 22 so as to be connected to the contact hole 32h.
A wiring groove for 3w is formed, and a wiring layer 13w is formed. The upper surface of the first wiring layer 13w is covered with a third interlayer insulating film layer 23 whose surface is flattened, and a passivation film 24 is further formed thereon.

As described above, the contact hole 32h is formed so as to be in contact with a part and the side surface of the upper surface of the lower electrode 13, and the conductive material is filled to form the contact 32. The contact 32 is formed below the contact 32. Contact hole 33h is formed and filled with a conductive material to form the contact 33. Therefore, the lower electrode 13 is formed by substantially one contact 13c without being laterally separated.
And the source / drain region 10A1 can be connected at one time, and a remarkable effect can be obtained for miniaturization of the ferroelectric memory cell.

Next, steps of manufacturing a ferroelectric memory cell having the structure shown in FIGS. 2 and 3 will be described in order with reference to the sectional views and plan views shown in FIGS. The cross-sectional view shown below is different from FIG.
It is shown cut along D '.

First, as shown in FIG. 5, an element isolation region 10S1 is formed on a semiconductor substrate of one conductivity type, that is, a silicon substrate 10.
Is formed to form an element formation region. In this element formation region, source / drain regions 10A1 and 10A2 of the transistor, which is one of the elements constituting the ferroelectric memory cell, are formed as diffusion layers.

After that, the gate electrode 11-2 of the memory cell transistor and the gate electrode (not shown) of the transistor for another device are formed on the silicon substrate 10 by the same process as the ordinary CMOS type DRAM. A first interlayer insulating film 12 such as a BPSG film is formed thereon by LP-CVD, and the surface is planarized by CMP.

Thereafter, patterning by lithography is performed, and the formed first interlayer insulating film 12 is selectively etched by RIE, so that the source and drain regions 10A1 of the silicon substrate 10 and the gate electrode (not shown) are formed. A contact hole 33h to be connected is formed.

Simultaneously with the formation of the contact hole 33h, a contact hole 18h connected to the source / drain region 10A2 of the adjacent transistor Tr2 is also formed. (See FIG. 2) These contact holes 33h,
A protective film 30b such as a barrier metal on the entire inner surface of 18h;
After the formation of 18b, tungsten is buried using a blanket-tungsten burying method to form contacts 33 and 18, respectively.

Next, as shown in FIG. 6, a thin silicon nitride film layer 42 is formed on the interlayer insulating film 12 by the LP-CVD method. The silicon nitride film layer 42 prevents oxidation of the contact plug material (for example, W) of the contacts 33 and 17 due to annealing in an oxygen atmosphere performed later in a ferroelectric capacitor forming step, and also performs transistor characteristics by the annealing. Has a role to prevent fluctuations.

Next, an LP-
CVD method or plasma CVD method or normal pressure CVD
A thin silicon oxide film layer 43 is formed by the method. next,
On the silicon oxide film 43, a TiN, Ti, Pt conductive film is sequentially deposited by sputtering as the capacitor lower electrode 13,
A PZT film is formed as a ferroelectric film 14 for a capacitor insulating film, and a Pt conductive film is sputter-deposited as a capacitor upper electrode 15.

Then, as shown in FIG. 7, patterning is performed by the RIE method in the order of the capacitor upper electrode 15, the ferroelectric capacitor insulating film 14, and the capacitor lower electrode 13, so that the pattern is formed immediately above the gate electrode 11-2. The ferroelectric capacitor C2 is formed. At this time, needless to say, another ferroelectric capacitor C1 is also formed at the same time.

At this stage, if necessary, annealing may be performed in an oxygen atmosphere at about 500 degrees Celsius to take measures to recover the characteristics of the ferroelectric film 14.

Next, in FIG. 8, a second interlayer insulating film 22 is formed by plasma CVD. The second interlayer insulating film 22 is deposited sufficiently thick with respect to the thickness of the ferroelectric capacitor having a laminated structure of three layers of films 13, 14, and 15, and the surface is planarized by CMP.

Thereafter, as shown in FIG. 9, patterning by lithography is performed, and the interlayer insulating film 22, the thin silicon oxide film layer 43, and the thin silicon nitride film layer 42 are simultaneously penetrated by the RIE method, and Is formed immediately above the first-stage contact hole 18h. At the same time, a contact hole 32h penetrating through the second interlayer insulating film 22 and connecting to the common lower electrode 13 of the ferroelectric capacitors C1 and C2, and a ferroelectric capacitor penetrating through the second interlayer insulating film 22 A contact hole 35h connected to the upper electrode 15b is formed.

Here, the contact hole 32h makes contact with a part of the upper surface and the side surface of the lower electrode 13 of the ferroelectric capacitor via the bent portion 32A formed on the side thereof, and at the same time as the first stage. It is also connected to the silicon substrate 10 through the contact hole 33h. This is a particularly different configuration of the present invention from the prior art.

In forming the contact holes in the step shown in FIG. 9, at least the first-stage contact holes 18h
And a contact hole 32h connected to the lower electrode 13 of the ferroelectric capacitor.
Are simultaneously formed. R of contact hole for this
The IE method is performed under such conditions that a contact hole 36h connected to the first-stage contact hole 18h can be formed properly.

In this RIE method, the silicon oxide film is etched, but the material constituting the electrodes 13, 15a, 15b of the ferroelectric capacitor, such as platinum, iridium, or SRO, is not etched. is necessary. If the contact holes 32h and 36h are etched using the RIE method satisfying such conditions, the upper contact hole 32h of the contact 13c over the end of the capacitor lower electrode 13 as shown in the plan view of FIG. , FIG. 4 or FIG.

That is, in the portion of the contact hole 32h formed above the capacitor lower electrode 13 above the bent portion 32A, the etching does not proceed when the etching of the contact hole 32h reaches the capacitor lower electrode 13. , A bent portion 32A is formed. As a result, a contact hole is formed so as to be connected to a part of the upper surface of the capacitor lower electrode 13 and the side surface.

On the other hand, the portion of the contact hole 32h protruding downward from the end of the capacitor lower electrode 13 is etched to the surface of the lower contact 33 already connected to the silicon substrate 10, and It is formed as a contact 32 that connects to 10. In this case, the barrier metal 30a is formed on the inner surface of the contact hole 32h.

Thereafter, by sputtering aluminum at a high temperature, aluminum is reflowed to fill the contact holes 32h and 36h, and at the same time, aluminum films for the wirings 13w and 15w are deposited. Then, this is patterned and then processed by the RIE method to form first layer wirings 13w and 15w. FIG. 9 shows a cross section of the process so far.

Next, in FIG. 10, d-TEOS is deposited on the first wiring 15w by a plasma CVD method,
After the interlayer insulating film 23 is formed, planarization is performed by CMP, and after patterning by lithography, RI
A contact hole 37h penetrating through the third interlayer insulating film 23 is formed by using the E method. Then, at the same time as filling the contact holes 37h by the aluminum reflow sputtering method, an aluminum film for wiring is deposited. Then, this is patterned and processed by the RIE method to form the second layer wiring 38.

Thereafter, in the case of a device having a two-layer wiring structure, a top passivation insulating film 24 is deposited and a pad portion is opened. Thus, a final shape as shown in FIG. 10 is obtained. In the case of a device having a multi-layer wiring structure, a wiring layer and an interlayer insulating layer are sequentially formed by repeating the above-described method, a top passivation insulating film is finally deposited, and a pad portion is opened to complete the device. .

In the case of a chain FRAM manufactured using the above-described method, of the contacts in the FRAM memory cell shown in FIG. 10, the contacts are formed so as to be connected to the lower electrode 13 of the ferroelectric capacitor. The bent contact portion 32 extends from the end of the lower electrode 13.
A is formed as the first contact 3
3 also serves as a contact formed so as to be directly connected.

Therefore, in the conventional chain FRAM device, it is possible to eliminate the margin between the capacitor lower electrode 13 and the contact 32, which is a factor of increasing the size of the memory cell, and to reduce the size of the memory cell. .

In this embodiment, the first wiring layer 1
5w to silicon substrate 10 (transistor diffusion layer 10A)
1) Or the contact connected to the gate electrode of the transistor is formed in two parts, the first-stage contact 18 and the second-stage contact 36. The aim is to reduce the aspect ratio of such contacts and to reduce the burden of RIE and aluminum embedding.

However, in order to simplify the process, such a contact may be formed at a time after the formation of the second insulating film 22.

(Second Embodiment) Hereinafter, a second embodiment will be described.

FIG. 11 schematically shows a planar structure of another chain FRAM manufactured by applying the technique of the present invention.
The plan view shown in FIG. 11 shows a configuration corresponding to the plan view of FIG. 3, and similarly to the case of FIG. 3, the upper contact hole 32h of the contact 13c connected to the lower electrode 13 of the ferroelectric capacitor and the diffusion layer of the transistor. The contact hole 33h connected to 10A1 is the same contact hole 31
h, and the contact 13
It is characteristic that there is no wiring on c. In this embodiment, as in the first embodiment, the contact hole 31h functions as a contact hole 32h to the lower electrode 13 of the ferroelectric capacitor, and as a contact hole 33h from the first wiring layer to the transistor. Also works.

Hereinafter, a cross-sectional structure of a device manufactured according to the present embodiment will be described. In FIG. 12, above the transistor formation region 10A1, for example, BP
A transistor is formed in the first interlayer insulating film 12 such as SG in the same manner as in FIG.

On the surface of the first interlayer insulating layer 12, a thin silicon nitride film layer 42 and a thin silicon oxide film layer 4 are formed.
3 is formed thereon, and further thereon a lower electrode described later,
A ferroelectric film and an upper electrode are sequentially formed to form a ferroelectric capacitor.

This capacitor is covered with a planarized second interlayer insulating film 22 made of, for example, d-TEOS or the like, and a first wiring such as aluminum is formed on the second interlayer insulating film 22. A layer (not shown) has been formed.

Then, a first-stage contact hole 33h is formed so as to penetrate the first interlayer insulating film 12. This contact hole 33h is connected to the drain source region 10A1 of the switching transistor, and the inside of the contact hole 33h is filled with a refractory metal such as tungsten to form a lower contact 33.

Further, a second-stage contact hole 32h is formed so as to simultaneously penetrate the thin silicon nitride film layer 42, the thin silicon oxide film layer 43, and the second interlayer insulating film 22. Here, the feature when the present invention is used is that, similarly to the embodiment of FIG. 4, a contact hole formed to connect to the lower electrode 13 of the ferroelectric capacitor among the contacts in the memory cell. 32h is formed so as to protrude from the end of the lower electrode 13, whereby 1
The point is that it is formed so as to communicate directly with the third-stage contact hole 33h. The contact hole 32h is buried with aluminum or the like to form the contact 32.
Immediately above, a thin insulating film 41 is deposited, and a first wiring layer to be described later is formed in the contact hole 32h.
Even if it is on top, it is devised to be insulated. Here, of the second-stage contact holes formed so as to be directly connected to the first-stage contact holes, a contact hole 32h used for connecting the lower electrode 13 of the capacitor and the diffusion layer 10A1 of the underlying transistor is used. The other contact holes 36 are formed by a conventional forming method.

The upper surface of the silicon oxide film 41 is covered with a third interlayer insulating film 23 whose surface is flattened, and a passivation film 24 is formed above the third interlayer insulating film 23.

Next, a method of manufacturing the semiconductor memory device according to the second embodiment will be described with reference to FIGS. This cross-sectional view is also cut along the line corresponding to the line DD ′ in FIG. 2 as in the description of the above-described embodiment, and the corresponding components are denoted by the same reference numerals. is there.

First, the process from forming the second interlayer insulating film 12 on the capacitor by plasma CVD to flattening the surface by CMP is the same as that of the first embodiment. The cross section at this time is the same as FIG.

In this embodiment, thereafter, patterning by lithography is performed, and the thin silicon nitride film layer 42, the thin silicon oxide film layer 43, and the second
Contact hole 18 penetrating through the interlayer insulating film 22 at the same time and connecting to the first-stage contact hole 18h in the base.
h, and a contact hole 32h penetrating through the second interlayer insulating film 22 and connecting to the lower electrode 13 of the capacitor is simultaneously formed.

The contact hole thus formed is 32h in the figure. However, the first-stage contact hole 33
At this time, only the contact hole 32h used for connecting the lower electrode 13 of the capacitor and the diffusion layer 10A1 of the base transistor among the contact holes connected to the capacitor h. The contact hole 32 at this time
The method of forming h is the same as that of FIG. However, instead of forming all the contacts at the same time, the lower electrode 13 of the capacitor and the diffusion layer 10A1 of the underlying transistor are not formed.
This embodiment is different from the first embodiment in that only the contact hole 32h used for the purpose of connecting the first and second layers is formed first.

Next, aluminum is sputtered at a high temperature to reflow the aluminum to fill the above-mentioned contact hole 32h, and further to remove the portion on the oxide film by CMP or the like to leave aluminum only inside the contact hole 32h. . Then, a silicon oxide film 41 of about 100 nm is deposited thereon. FIG. 13 is a cross-sectional view at this time.

Next, as shown in FIG. 14, patterning by lithography is performed, and a thin silicon nitride film layer 42, a thin silicon oxide film layer 43 and a second
A contact hole 36h penetrating through the interlayer insulating film 22 and the silicon oxide film 41 at the same time and connecting to the underlying first-stage contact hole 18h, and the second interlayer insulating film 2
2 and a contact hole 35h penetrating through the silicon oxide film 41 and connecting to the upper electrode 15b of the capacitor.

Thereafter, by sputtering aluminum at a high temperature, aluminum is reflowed to fill the contact holes 36h and 35h, and at the same time, an aluminum film for wiring is deposited. Then, this is patterned and processed by the RIE method to form the first layer wiring 15w.

Next, as shown in FIG.
After depositing d-TEOS on w by plasma CVD and forming the third interlayer insulating film layer 23, planarization is performed by CMP, and after patterning by lithography,
A contact hole 37h penetrating through the third interlayer insulating film 23 is formed by using the RIE method.

Then, at the same time as the contact hole 37h is buried by the aluminum reflow sputtering method, an aluminum film for wiring is deposited. Then, this is patterned and processed by the RIE method to form the second layer wiring 3.
8 is formed.

Thereafter, in the case of a device having a two-layer wiring structure, a top passivation insulating film 24 is deposited and a pad portion is opened. Thus, the final shape as shown in FIG. 15 is obtained.

In the case of a device having a multi-layer wiring structure, a wiring layer and an insulating layer are formed by repeating the above-described method, and finally a top passivation insulating film 24 is deposited and a pad portion is opened.

In the case of a chain FRAM manufactured by using the method described above, a contact hole 32h formed to be connected to the lower electrode 13 of the ferroelectric capacitor among the contacts in the memory cell. , Which protrude from the end of the lower electrode 13, thereby also serving as a contact hole formed so as to be directly connected to the first-stage contact hole 33.

Therefore, in the conventional chain FRAM device, it is possible to eliminate the margin between the capacitor lower electrode and the contact hole, which was a factor of increasing the size of the memory cell, and to reduce the size of the memory cell.

The effects so far are as described in the first embodiment. However, in the second embodiment, as shown in FIG. 16, the lower electrode 13 of the capacitor and the diffusion layer An independent wiring layer 57 is provided immediately above the contact hole 32 used for the purpose of connecting
Can be provided.

The wiring layer 57 is the same wiring layer as the first wiring layer 15w, but is indicated here by different symbols for the sake of explanation. In the case of the first embodiment, the wiring layer 57 is connected to the contact 32 and cannot be used as an independent wiring layer. However, in the case of the second embodiment, the contact 32 is formed of a silicon oxide film. Since it is completely insulated by 41, it can be used as an independent wiring layer.

As a result, the use efficiency of the wiring layer in the cell array can be increased, the cell size can be reduced,
The total number of wiring layers can be reduced.

As described above, according to the first and second embodiments, the contact connected to the lower electrode of the ferroelectric capacitor and the contact connected to the diffusion layer of the transistor are formed by a single contact. Since the contact holes are formed by metal filling, the area of the semiconductor memory device can be significantly reduced.

(Third Embodiment) FIGS. 17 to 3
Referring to FIG. 1, another embodiment of the present invention will be described in detail.

FIG. 17 schematically shows a planar structure of an FRAM cell manufactured by using the technique of the present invention. This FIG.
Are the upper electrodes 15a and 15b of the capacitors and the contacts 15ac and 15c to the upper electrodes 15a and 15b of the capacitors.
FIG. 19 is a diagram showing a relationship between bc and a contact 34 (FIG. 18) to the diffusion layer 10A1 of the base transistor.

In the plan view shown in FIG. 17, the first wiring layer 15
It is characteristic that the contact from w to the upper electrode 15a of the ferroelectric capacitor and the contact from the first wiring layer 15w to the diffusion layer of the transistor are formed as the same contact 15ac. That is, the contact 15a
Half of c is the upper electrode 15a of the ferroelectric capacitor.
To the first wiring layer 1
5w functions as a contact to the transistor.

Further, in the ferroelectric capacitor of the present embodiment, the upper electrode 15a in the portion close to the contact 15ac is formed so as to protrude outside the lower electrode 13. Thus, even with the above contact pattern, the lower electrode 13 and the contact 15ac
Do not contact and conduct.

Hereinafter, a cross-sectional structure of a device manufactured according to the present embodiment will be described.

In FIG. 18, a gate 11 of a switching MOS transistor of a memory cell is provided on a semiconductor substrate 10.
-2 is formed. These transistors are covered with a planarized first interlayer insulating film 12 such as BPSG.

On the surface of the first interlayer insulating layer 12, a thin silicon nitride film layer 42 and a thin silicon oxide film layer 43 are formed, on which a lower electrode 13, a ferroelectric film 14 and an upper Electrodes 15a are sequentially formed to form a ferroelectric capacitor.

This capacitor is covered with a planarized second interlayer insulating film layer 22 made of, for example, d-TEOS or the like, and a first interlayer insulating film 22 made of, for example, aluminum is formed on the second interlayer insulating film 22. The wiring layer 15w is formed.

A first-stage contact hole 34h is formed so as to penetrate the first interlayer insulating film 12 described above. The contact hole 34h is formed so as to reach the drain source region 10A1 of the switching transistor, and the inside of the contact hole 34h is filled with a high melting point metal such as tungsten via a barrier metal 34b.

A second-stage contact hole 44h is formed so as to simultaneously penetrate the thin silicon nitride film layer 42, the thin silicon oxide film layer 43, and the second interlayer insulating film 22. Although not particularly shown, in the case of this device, the contact hole formed so as to penetrate the thin silicon nitride film layer 42, the thin silicon oxide film layer 43, and the second interlayer insulating film 22 depends on the connection destination. There are three types. That is, (1) the contact hole 44h formed so as to be directly connected to the first-stage contact hole 34h described above, and (2) the contact hole 44h is formed so as to be connected to the upper electrode 15a of the ferroelectric capacitor. The contact hole 15ac is (3) a contact hole 13ch formed to be connected to the lower electrode 13 of the ferroelectric capacitor.

The second-stage contact holes are filled with a metal such as aluminum.

Here, when the present invention is applied, the third
The feature of the embodiment is that, of the contacts in the memory cell, a contact hole 15ac formed so as to be connected to the upper electrode 15a of the ferroelectric capacitor is formed so as to protrude from an end of the upper electrode 15a, This is that the contact hole also serves as a contact hole formed so as to be directly connected to the first-stage contact hole 34h.

The upper electrode 15a near the contact hole 15ac is formed such that its end is outside the end of the lower electrode 13. For this reason, since the upper electrode 15a forms an eave with respect to the lower electrode 13, even if the contact hole 15ac protrudes from the end of the upper electrode 15a as described above, the contact hole 15ac and the ferroelectric substance are formed. The lower electrode 13 of the capacitor does not come into contact with the lower electrode.

The purpose of connecting the upper electrode 15b of the capacitor and the diffusion layer 10A2 of the underlying transistor among the contacts formed so as to be directly connected to the first-stage contact in the first interlayer insulating film 12. 17, for example, a contact 13c1 connected to the lower electrode 13 of FIG.
The contact 13c2 connected to the diffusion layer 10A1 of the underlying transistor via 3w is formed by a conventional forming method.

The first wiring layer 15 is formed on the second interlayer insulating film 22 so as to connect to these contact holes.
w is formed. The upper surface of the first wiring layer 15w is covered with a third interlayer insulating film 23 whose surface is flattened, and a passivation film 24 is formed thereon.

With the above configuration, the upper electrode of the ferroelectric capacitor and the diffusion layer of the underlying transistor can be connected with a single contact, so that, for example, a chain type FRAM can be further miniaturized. .

Next, the manufacturing steps will be described in order with reference to the sectional views and plan views shown in FIGS. Although this embodiment will be described below as a cross-sectional view taken along line GH in FIG. 2, for example, the upper electrode 15a is
FIG. 4 is a cross-sectional view taken along the right direction in FIG.
3-2 from contact 13c to source / drain region 10
The cross-sectional view up to the contact 18 to B2 is a cross-sectional view taken along the line G′-H and viewed to the left in the drawing.

First, as shown in FIG.
After the gate electrode 11-2 of the memory cell transistor is formed on the silicon substrate 10 by the same process as that of the S-type DRAM, the BPSG is formed thereon by LP-CVD, for example.
A first interlayer insulating film 12 such as a film is formed, and the surface is planarized by CMP.

Thereafter, patterning is performed by lithography, the first interlayer insulating film 12 is selectively etched by RIE, and a contact hole 34h connected to the silicon substrate 10 and the gate electrode is formed.

Further, the contact hole 34h is filled with tungsten by using a blanket-tungsten filling method to form the first contact 34.

Next, referring to FIG. 20, a thin silicon nitride film layer 42 is formed on the interlayer insulating film 12 by the LP-CVD method. The silicon nitride film layer 42 prevents oxidation of the contact plug material 34 (for example, W) due to annealing in an oxygen atmosphere which is performed later in a ferroelectric film capacitor forming process, and also prevents variation in transistor characteristics due to the annealing. Has a role.

Next, an LP-
CVD method or plasma CVD method or normal pressure CVD
A thin silicon oxide film layer 43 is formed by the method.

Next, in FIG. 21, TiN, T is formed on the silicon oxide film 43 as the capacitor lower electrode 13.
i,. After Pt is sequentially deposited by sputtering, a PZT film is further deposited as a ferroelectric film 14 for a capacitor insulating film. At this time, the Pt film thickness is, for example, about 100 nm.
The PZT film thickness is set to about 150 nm.

Thereafter, annealing is performed in an oxygen atmosphere at 600 to 750 degrees Celsius to crystallize the PZT film.

Further, Pt is deposited by sputtering as the capacitor upper electrode 15a. The Pt film thickness at this time is about 20 n
m.

Next, patterning by lithography is performed and processed by RIE to form a ferroelectric capacitor. At this time, if the ferroelectric film 14 is damaged and changes its original characteristics, it can be recovered by annealing in an oxygen atmosphere at about 500 degrees Celsius.

Next, in FIG. 22, after forming the second interlayer insulating film 22, the silicon oxide film 3 is formed by plasma CVD.
9 is deposited. The second interlayer insulating film 22 is composed of a lower electrode 13, a ferroelectric film 14, and an upper electrode 15 constituting a capacitor.
Deposit sufficiently thick relative to the total thickness of a, and planarize the surface by CMP. At this time, the CMP is performed so that the thickness of the oxide film 39 on the capacitor upper electrode 15 becomes about 100 nm.

Next, patterning by lithography is performed, and the silicon oxide film on the capacitor, that is, the second interlayer insulating film 22 is etched by RIE. The etching at this time is performed under such a condition that the oxide film on the capacitor upper electrode 15a is not removed or removed. For example,
In the case of this embodiment mode, the etching is performed under such a condition that an oxide film of about 100 nm is etched.

The pattern of the portion to be etched is:
The edge of the etching pattern is located outside the edge of the capacitor lower electrode 13 in a portion where a contact hole to be connected to the upper electrode 15a is to be formed later.

Next, after depositing Pt again by the sputtering method, Pt in portions other than the concave portions of the silicon oxide film 22 formed by etching the silicon oxide film 22 is removed by CMP. This completes the formation of the upper electrode 15a of the capacitor.

By using the above-described capacitor forming process, it is possible to form a structure in which the end of the upper electrode 15a near the contact hole connected to the upper electrode 15a is outside the end of the lower electrode 13. it can. Such a structure becomes important when a contact hole is formed later.

Next, in the step of FIG.
A silicon oxide film 39 is deposited to a thickness of about 100 nm by the VD method. The purpose of the oxide film 39 is to form the upper electrode 15a and the first wiring layer 15w to be formed later on the upper electrode 15a.
And to insulate it. Therefore, there is no plan to form the first wiring layer 15w immediately above the upper electrode 15a, and the upper electrode 15a can be formed without depositing the silicon oxide film 39.
If the insulation between the silicon oxide film 39 and the first wiring layer 15w can be ensured, the step of depositing the silicon oxide film 39 can be omitted.

Next, in FIG. 23, patterning by lithography is performed, and the silicon oxide film 39, the second interlayer insulating film 22, the thin silicon oxide film layer 43, and the thin silicon nitride film layer 42 are simultaneously formed by RIE. A contact hole 36h that penetrates and connects to the first-stage contact 34 under the base, a contact hole 35 that penetrates the second interlayer insulating film 22 and connects to the lower electrode 13 of the capacitor, and a silicon oxide film 39 Then, a contact hole 15ah connected to the upper electrode 15a of the capacitor is formed.

Here, the contact hole 15ah is connected not only to the upper electrode 15a of the capacitor but also to the silicon substrate 10 via the first-stage contact. This is the difference between the present invention and the prior art.

In the contact formation at this time, a contact hole 36h connected to at least the first-stage contact 34 and a contact hole 15ah connected to the capacitor upper electrode 15a are formed simultaneously. The contact hole RIE is performed under such conditions that a contact hole 36h connected to the first-stage contact hole 34 can be formed properly.

This RIE must be such that the silicon oxide film 39 is etched, but the capacitor electrode material such as platinum, iridium and SRO is not etched. If the contact hole is etched using RIE satisfying such conditions, the capacitor upper electrode 15 as shown in the plan view of FIG.
The contact hole 15ah on the end of “a” has a sectional structure as shown in FIG. 18 or FIG.

That is, the part of the contact hole formed on the capacitor upper electrode 15a is etched by the contact hole 15ah.
When it reaches a, the etching of the oxide film 39 ceases to proceed, and is formed as a contact hole 15ah connected to the capacitor upper electrode 15a.

On the other hand, contact hole 15ah
Of the portions protruding from the end of the capacitor upper electrode 15a, the etching proceeds to the silicon substrate 10,
Contact hole 15a connected to silicon substrate 10
h.

What is important in the formation of the above-described contact hole is that the upper electrode 15
This is a point that the end of “a” is located outside the end of the lower electrode 13. Therefore, the portion of the contact hole 15ah that protrudes from the upper electrode 15a can reach the first-stage contact 34 of the base without contacting the capacitor lower electrode 13.

In the case of a capacitor formed by the conventional technique, since the RIE processing of the capacitor is performed in the order of the upper electrode, the ferroelectric material, and the lower electrode, in principle, the edge of the upper electrode is located outside the edge of the lower electrode. Never be. For this reason,
When a contact hole that partially protrudes from the upper electrode as described above is formed in the capacitor formed in the conventional capacitor processing step, the part of the contact hole that protrudes from the upper electrode must be a lower electrode. Contact with Thus, in the present invention, not only the method of forming the contact hole but also the method of forming the capacitor are devised.

Thereafter, aluminum is sputtered at a high temperature so that aluminum is reflowed to fill the contact hole 15ah and, at the same time, an aluminum film for wiring is deposited. Then, after patterning this, it is processed by RIE, and the contact 15
The ac and the first layer wiring 15w connected thereto are formed.

Next, referring to FIG.
After depositing d-TEOS on the w and 13w by the plasma CVD method and forming the third interlayer insulating film layer 23, the CM
After planarization by P and patterning by lithography, a contact hole 37h penetrating through the third interlayer insulating film 23 is formed by RIE.

Then, at the same time as filling the contact holes 37h by aluminum reflow sputtering, an aluminum film for wiring is deposited. Then, this is patterned and processed by the RIE method to form the second layer wiring 38. Thereafter, in the case of a device having a two-layer wiring structure, a top passivation insulating film 24 is deposited, and a pad portion is opened. Thus, a final structure as shown in FIG. 24 is obtained.

In the case of a device having a multi-layer wiring structure, a wiring layer and an insulating layer are formed by repeating the above-described method, and finally a top passivation insulating film is deposited and a pad portion is opened.

In the case of the FRAM manufactured by using the method described above, of the contacts in the memory cell,
A contact hole formed to connect to the upper electrode of the ferroelectric capacitor is formed so as to protrude from an end of the upper electrode, thereby forming a contact directly connected to the first-stage contact hole. Also serves as a hall.

Therefore, in the conventional FRAM, the margin between the capacitor upper electrode and the contact hole to the substrate or the margin between the capacitor lower electrode and the contact hole to the substrate, which is a factor of increasing the size of the memory cell, is eliminated. And the size of the memory cell can be reduced.

In the present embodiment, the first wiring layer 1
5w is a contact hole connecting to the silicon substrate 10 (transistor diffusion layer) or the gate electrode of the transistor.
h and 36h.

This aims to reduce the aspect ratio of the contact hole and reduce the burden of the RIE method and the embedding of aluminum. However, in order to simplify the process, the contact holes 34h, 3h
6h may be formed at once after the formation of the second interlayer insulating film 22.

(Fourth Embodiment) Hereinafter, a fourth embodiment will be described with reference to FIGS.

FIG. 25 schematically shows a planar structure of an FRAM manufactured by using the technique of the present invention. In the plan view shown in FIG. 25, the contact hole connected to the upper electrode 15a of the ferroelectric capacitor and the contact hole connected to the source / drain region of the transistor are formed as the same contact hole 15ac. The feature is that there is no wiring above.

In this embodiment, as in the third embodiment, for example, half of the contact holes 15ac function as contact holes to the upper electrode 15a of the ferroelectric capacitor, and the other half corresponds to the first hole. Wiring layer 15
It functions as a contact hole from w to the source / drain region of the transistor.

Hereinafter, a cross-sectional structure of a device manufactured according to the present embodiment will be described.

26, a gate (not shown) of a switching MOS transistor of a memory cell is formed on a semiconductor substrate 10. These transistors are made of, for example, a flattened first interlayer insulating material such as BPSG. Membrane 12
Covered with.

On the surface of the first interlayer insulating layer 12, a thin silicon nitride film layer 42 and a thin silicon oxide film layer 43 are formed, on which a lower electrode 13, a ferroelectric film 14 and an upper The electrodes 15a are sequentially formed to form a ferroelectric capacitor.

This capacitor is covered with a planarized second interlayer insulating film layer 22 made of, for example, d-TEOS or the like, and a first wiring such as aluminum is formed on the second insulating film 22. A layer (not shown) has been formed.

Then, a first-stage contact hole 34h is formed so as to penetrate the first interlayer insulating film 12 described above. The contact hole 34h is connected to the drain source region 10A1 of the switching transistor, and the inside of the contact hole 34h is filled with a refractory metal such as tungsten.

A second-stage contact hole 15ah is formed so as to simultaneously penetrate the thin silicon nitride film layer 42, the thin silicon oxide film layer 43, and the second interlayer insulating film 22.

The feature of the present invention is that, of the contacts in the memory cell, the contact hole 15ah formed so as to be connected to the upper electrode 15a of the ferroelectric capacitor is connected to the upper electrode 15a. This is formed so as to protrude from the end, and also serves as a contact hole formed so as to be directly connected to the first-stage contact hole 34h.

The contact hole 15ah is buried with aluminum or the like, and a thin insulating film 39 is deposited immediately above the contact hole 15ah, and a first wiring layer 15w described later is formed in the contact hole 15ah. Even if it is on top, it is devised to be insulated.

Here, the first-stage contact hole 34h
Contact holes other than the contact hole 15ac used for connecting the upper electrode 15a of the capacitor and the diffusion layer 10A1 of the base transistor among contact holes formed so as to be directly connected to the third embodiment are described in the third embodiment. As described above, it is formed by a conventional forming method.

The upper surface of the silicon oxide film 39 is covered with the third insulating film layer 23 whose surface is flattened, and the passivation film 24 is formed thereon.

Next, a method of manufacturing the semiconductor memory device of this embodiment will be described in detail with reference to FIGS.

First, in FIG. 27, the process is the same as that of the third embodiment up to the point where the second interlayer insulating film 22 is partially etched to bury the Pt upper electrode 15a. However, in the case of the present embodiment, overetching of CMP (Ov
The surface of the Pt upper electrode 15a is adjusted to be about 50 nm lower than the surface of the interlayer film 22 by adjusting the time. FIG. 27 shows a cross section at this time.

According to the method of the present embodiment, as shown in FIG.
By using the E method, a contact hole 15ah that penetrates through the second insulating film 22, the thin silicon oxide film layer 43, and the thin silicon nitride film layer 42 at the same time and is connected to the underlying first-stage contact hole 34h is formed.

However, the first-stage contact hole 34h
At this time, only the contact hole 15ah used for connecting the lower electrode 13 of the capacitor and the diffusion layer 10A1 of the base transistor is formed. Contact hole 15 at this time
The method of forming ah is the same as that of the third embodiment.

However, the present embodiment is different from the first embodiment in that not all contacts are formed at the same time, but only a contact hole 15ah used for connecting the upper electrode 15a of the capacitor and the diffusion layer 10A1 of the base transistor is formed first. The form is different from the third embodiment.

Next, in FIG. 28, aluminum is reflowed by sputtering aluminum at a high temperature to bury the above-mentioned contact hole 15ah, and a portion on the oxide film is further cut off by CMP or the like to remove the inside of the contact hole 15ah. Aluminum is left only on the upper electrode 15a.

First, in the step of forming the Pt upper electrode 15a, the upper electrode 15a is buried so that the surface thereof is slightly lower than the surface of the interlayer film 22. Aluminum remains in the recess formed by the upper electrode 15a and the interlayer film 22. Therefore, sufficient conduction can be provided between the aluminum filling the contact hole 15ah and the upper electrode 15a. Then, a silicon oxide film 39 of about 100 nm is deposited thereon.

Next, in FIG. 29, patterning by lithography is performed, and the thin silicon nitride film layer 42, the thin silicon oxide film layer 43, the second insulating film 22, and the silicon oxide film 39 are simultaneously penetrated by RIE. Then, a contact hole 36h connected to the first-stage contact hole 34h on the base and a contact hole 35h penetrating through the second insulating film 22 and the silicon oxide film 39 and connected to the lower electrode 13 of the capacitor are formed.

Thereafter, by sputtering aluminum at a high temperature, aluminum is reflowed to fill the above-mentioned contact holes 35h and 36h, and at the same time, an aluminum film for wiring is deposited. Then, this is patterned and then processed by the RIE method to form first layer wirings 13w and 15w.

Next, in FIG. 30, the first wiring layer 13
After depositing d-TEOS on the w and 15w by plasma CVD and forming the third insulating film layer 23, planarization is performed by CMP, patterning by lithography is performed, and then the third is performed by RIE. A contact hole 37h penetrating through the insulating film 23 is formed.

At the same time as filling the contact holes 37h by aluminum reflow sputtering, an aluminum film for wiring is deposited. Then, this is patterned and processed by the RIE method to form the second layer wiring 38.

Thereafter, in FIG. 30, in the case of a device having a two-layer wiring structure, the top passivation insulating film 2 is formed.
4 is deposited and a pad portion is opened. Thus, a final structure as shown in FIG. 30 is obtained.

In the case of a device having a multi-layer wiring structure, a wiring layer and an insulating layer are formed by repeating the above-described method, and finally, a top passivation insulating film 19 is deposited and a pad portion is opened. . The resulting final structure is shown in FIG.

In the case of the FRAM manufactured by using the method described above, of the contacts in the memory cell,
A contact hole 15ah formed so as to be connected to the upper electrode 15a of the ferroelectric capacitor is formed so as to protrude from an end of the lower electrode 13, thereby being formed so as to be directly connected to the first-stage contact hole 34h. Also serves as a contact hole.

Therefore, in the conventional FRAM, a margin between the capacitor upper electrode or lower electrode and the contact hole formed so as to be directly connected to the first-stage contact hole, which is a factor for increasing the size of the memory cell, is provided. It can be eliminated, and the size of the memory cell can be reduced.

The effects so far are as seen in the third embodiment, but in the fourth embodiment, the effects are further improved as shown in FIG.
As shown in (5), an independent wiring layer 57 can be provided directly above the contact hole 15ac used for connecting the upper electrode 15a of the capacitor and the diffusion layer 10A1 of the underlying transistor. The wiring layer 57 is the same wiring layer as the first wiring layer 15w, but is shown here with different symbols for explanation.

The wiring layer 57 cannot be used as an independent wiring layer because it is connected to the contact hole 15ac in the case of the third embodiment. However, in the case of the fourth embodiment, the wiring layer 57 cannot be used. Since 15ac is completely insulated by the silicon oxide film 39, it can be used as an independent wiring layer.

As a result, the use efficiency of the wiring layer in the cell array can be increased, the cell size can be reduced,
The total number of wiring layers can be reduced.

(Fifth Embodiment) FIGS. 32A and 32B show a fifth embodiment, in which FIG. 32A is a plan view, and FIGS. 32B and 32C are cross sections cut along two different cutting lines. FIG.

The difference from the embodiment of FIG. 2 is that the lower electrode 13 has a pattern having a U-shaped cut portion 60 at a portion where the upper electrodes 15a and 15b are not provided. Further, the lower electrode contact 13c is brought into contact with one side surface of the lower electrode 13 at the position of the most receded portion 60a of the cut portion 60, and the single contact 1
3c is arranged so as to be connected to the source / drain region 10A1 immediately below.

The contact 18 connected to the other source / drain region is connected to the lower electrode 13 adjacent to the lower electrode 13.
-1 and is arranged so as not to contact any of the lower electrodes. Also, the upper electrodes 15a, 15b
The upper electrode contacts 15c are respectively disposed on the upper side.

The upper electrode 15b on the lower electrode 13 and the upper electrode 15a-1 on the adjacent lower electrode 13-1 are connected to the wiring pattern 15 via the contacts 15c and 15c-1.
w, and further connected to the source / drain region 10A2 via the contact 18.

The remaining structure is substantially the same as that of the embodiment of FIG. 2, and the same reference numerals as those in FIG. 2 denote the same parts, and a description thereof will be omitted.

With the pattern and arrangement of the electrodes and contacts shown in FIG. 32, the same layout as the COP structure can be obtained inside the cell layout where the capacitor area occupies most of the cell area, which can greatly contribute to the realization of miniaturization. Configuration.

For example, the lower electrode 13 is formed so as to be displaced upward by a small distance S from the source / drain region 10A1 shown by the dotted line in FIG. This is because the lower electrode contact 13c is connected to the gate electrodes 11-1, 11-2, 1 used as word lines.
In order to reduce the width in order to miniaturize the arrangement direction of 1-3, to secure a certain contact area, and to have a certain margin against misalignment in a direction orthogonal to the gate electrode arrangement direction. This is because the lower electrode contact 13c is arranged as close to the center of the source / drain region 10A1 as possible, irrespective of factors such as the rectangular shape.

In this embodiment, the area of the rectangular lower electrode contact 13c is designed to be substantially equal to the area of the substantially square source / drain contact 18.

The fifth embodiment will now be described with reference to FIGS.
The manufacturing process of the embodiment will be described.

First, as shown in FIG. 33, element isolation layers 10S0, 10S1, and 10S2 are formed in the N-type semiconductor substrate 10 at predetermined intervals in the direction of the cutting line CD in FIG.
Between element isolation layers 10S0, 10S1, and 10S1,
An element formation region is formed during 10S2.

In this element formation region, P-type impurities are diffused to form source / drain regions 10A1 and 10B1.

Subsequently, the source / drain regions 10A1 and 10A2 formed in the direction along the cutting line AB in FIG.
34A along the position corresponding to the channel region between
As shown in the figure, a plurality of gate electrodes 11-1, 11-2, 1
1-3 are formed, and the whole is covered with an interlayer insulating film 12, and FIG.
4A and 4B, the surface is flattened by CMP.

Next, an aluminum film and a ferroelectric film are entirely deposited on the interlayer insulating film 12, and as shown in FIGS. 35A and 35B, the transistors Tr1 and Tr2 are formed by etching after resist exposure. A rectangular lower electrode 1 at a predetermined position
3 is formed at the position where the transistor Tr3 is to be formed. At the same time, the ferroelectric films 14 and 14-1 are also formed by patterning.

Subsequently, as shown in FIG.
5a, 15b and 15a-1 are formed. This upper electrode 1
When forming 5a, 15b, 15a-1, for example, FIG.
As shown in FIG. 6A, a resist R is buried to the same height as the surface of the ferroelectric film 14, an aluminum film is deposited on the entire surface in this state, and the gate electrodes 11-1 and 11-1 are etched by etching.
The upper electrode 15 is located at a position corresponding to each of 11-2 and 11-3.
a, 15b, and 15a-1 are cut out.

Next, as shown in FIG. 37, the lower electrodes 13 and 13-1, the ferroelectric films 14 and 14-
1. The entire upper electrodes 15a, 15b, 15a-1 are covered with an interlayer insulating film 22, and the surface thereof is planarized by CMP.

Thus, the source / drain region 10
A1, 10A2, 10B1, gate electrodes 11-1, 11
−2, 11-3, lower electrode 13, 13-1, upper electrode 1
After processing the layers 5a, 15a-1 and 15b to form an interlayer film 22 on the ferroelectric capacitor and flattening the same, as shown in FIG. 38, the upper electrode contact hole 15c is formed in the interlayer film 22.
h, 15ch-1 are opened by RIE using a predetermined mask.

Upper electrode contact holes 15ch, 15ch
-1 is formed substantially at the center of each of the upper electrodes 15a, 15b, 15a-1. These positional relationships are determined by other lower electrodes, for example, two upper electrodes 15a,
The same applies to the lower electrode 23-1 which is formed offset by the distance between 15b.

Next, as shown in FIG. 39C, source / drain contact holes 13ch, 18h reaching the source / drain regions 10A1, 10A2, 10B1,... And wiring grooves 15wh are opened. At this time, the already opened electrode contact holes 15ch and 15ch-1 of the ferroelectric capacitor of FIG. 39B are covered with the photoresist used to open the source / drain contact holes 13ch and 18h. Not affected.

As shown in FIG. 39C, in the etching of the contact hole 13ch of the lower electrode 13, the interlayer insulating film 22 and the high dielectric film 14 are removed, but the lower electrode 13 remains. In the subsequent etching of the interlayer insulating film 12, the lower electrode 13 serves as a mask, and the width under the lower electrode 13 becomes narrower. In this portion, part of the surface and part of the side surface of the lower electrode 13 are exposed in the contact hole 13ch.
It will be exposed as A.

In a step subsequent to FIG. 39, although not shown, a wiring groove such as a wiring 15w is formed above the contacts 15c, 15c-1, 18 connected to the electrodes 13, 15a, 15b of the capacitor.

Finally, as shown in FIGS. 40 (a), (b) and (c), a thick aluminum film is formed using contact holes 13ch, 15ch and 15ch by using, for example, reflow aluminum.
The contacts 13c, 15c, 15c-1, and 18 are formed by completely depositing and embedding in the channels ch-1 and 18h.

Next, aluminum is filled in a wiring groove formed in a later step of FIG. 39, and wiring 15w is formed so as to be connected to a contact.

Finally, the surface is processed by the CMP method to complete the chain type ferroelectric memory cell structure of the embodiment shown in FIG. 32 as shown in FIG.

As described above, since the contact is formed after the formation of the capacitor, the oxidation process at around 700 degrees Celsius in the capacitor process does not adversely affect the device. In particular, as shown in FIG. 39, the formation of a contact hole in the source / drain region of the transistor depends on the capacitor electrode 1
Since this step is performed in a step subsequent to the step of forming contact holes in 3, 15a, and 15b, the time during which the source / drain regions are exposed is short, and deterioration of transistor characteristics is small.

(Sixth Embodiment) FIG. 41 is a diagram showing a sixth embodiment, in which a wiring 15w is connected to a dual damascene (Du
al Damascene). Thus, the height of the contact plug of the contact 13c on the lower electrode 13 side matches the height of the wiring 15w. When the dual damascene method is used, there is no limitation on the thickness of the metal film to be deposited, so that it is easy to bury the metal in a deep contact. Except for the difference in this point, the configuration in FIG. 41 is the same as that in FIG. 40, and further description will be omitted.

(Seventh Embodiment) FIG. 42 shows a seventh embodiment, which is formed by a dual damascene method as in FIG. In this embodiment, the lower electrode 13 is in contact with the contact 13c only through the contact portion 13B formed on the side.

Generally, in order to remove the ferroelectric thin film 14, as in the example of FIG.
1 tends to overetch. When this over-etching occurs, the contact 13c causes a contact failure.

Therefore, in order to prevent contact failure, the contact portion 13B formed only on the side surface of the lower electrode 13
The ferroelectric thin film 14 may not be removed through a contact.

(Eighth Embodiment) FIG. 43 shows an eighth embodiment. In this case, the lower electrode is the first and second lower electrodes 13A, 1A at the central contact 13c.
3B.

The lower electrode contact 13c has projections 13c-1 and 13c-2 formed on the upper portion thereof, and the first and second projections 13c-1 and 13c-2 are formed on the lower electrode contact 13c.
Are arranged so as to overlap both of the lower electrodes 13A and 13B. The lower electrode contact 13c is the lower electrode 13A
And 13B, and the protrusions 13c-1, 13c-2.
, And the lower end reaches the source / drain region 10A1. The remaining configuration is shown in FIG.
0 is the same as in the embodiment.

In this configuration, lower electrode contact 13c
Projecting portions 13c-1 and 13c-2 and the lower electrode 13
If the overlapping portion with A and 13B is set to a margin, the contact area to the source / drain region 10A1 does not decrease due to misalignment.

(Ninth Embodiment) FIG. 44 shows a ninth embodiment. The embodiment of FIG. 44 corresponds to the embodiment of FIG. 42. In the etching for forming the lower electrode contact 13c, the ferroelectric films 14A and 14B are left without being etched. 13
c of the lower electrode 13A,
13B, it does not overlap with the high dielectric films 14A, 14B.

(Tenth Embodiment) FIG. 45 shows that, in the embodiment of FIG. 32, plug contacts 70, 71, 71 are inserted between respective contacts 13c, 18 and source / drain regions 10A1, 10A2, 10B1. This is an example.

That is, the contacts 13c, 15c, 1
8 is a source / drain region 10A1, 10A2, 10B
1, not on the plug contacts 70, 71, 72. In this method, in particular, the contacts 13c, 18
In this case, the contact opening and metal filling can be easily performed, and the contact yield can be increased. The other structure is the same as that of the embodiment of FIG.

FIGS. 46 to 49 are process sectional views corresponding to the embodiment of FIG.

FIG. 46 shows a state in which contact plugs 70, 71, 72 have already been formed in second interlayer insulating film 22. Before the step in FIG. 46, there is a step similar to the step shown in FIGS. 33 to 37, for example. In the step of forming the contact plugs 70, 71, and 72, in the step shown in FIG. 34, before depositing the interlayer insulating film 12, the contact plugs 70, 71, and 72 are deposited on the deposited resist by using lithography. This can be performed by etching a contact hole at a position to be formed and filling the contact metal.

Thereafter, there are steps shown in FIG. 35 to FIG. 37, but these steps are the same as the steps already described, so that further description will be omitted.

Next, in FIG. 47, a contact hole 1 is formed in the second interlayer insulating film 22 by a usual lithography method.
5ch and 15ch-1 are formed. At this time, a contact hole reaching the contact plugs 70-72 is not formed, and is protected from the influence of the etching by the interlayer insulating film 22.

Subsequently, in the step of FIG. 48, contact holes 13c reaching contact plugs 70-72 are formed.
h, 18h to the second interlayer insulating film 22, the first interlayer insulating film 12
Open through.

At this time, as shown in FIG. 48C, after the high dielectric film 14 is etched during the etching of the contact hole 13ch reaching the contact plug 70, the etching is performed on the surface of the lower electrode 13. Stop. Subsequent etching proceeds using the lower electrode 13 as a mask, and as a result, a part of the surface and a part of the side surface of the lower electrode 13 are exposed in the contact hole 13ch.

Next, in the step of FIG. 49, all contact holes are filled with metal to form contacts. At this time, the wiring layer 15w is formed while being connected to the contact on which the wiring layer 15w is formed.
48 is performed after the step of FIG. 48, which has already been described.

(Eleventh to Fourteenth Embodiments) The eleventh to fourteenth embodiments will be described below with reference to FIGS.

In the embodiment of FIG. 49, lower electrode contact 13c is formed lower by wiring layer 15w,
Although buried in the insulating layer 22, in the embodiment of FIG. 50, the lower electrode contact 13c has the same height as the wiring layer 15w. Other configurations are the same as those in FIG.

In the embodiment shown in FIG. 51, the lower electrode contact 13c is formed so as to contact only on the side surface 13B of the lower electrode. Other configurations are the same as those in FIG.

The embodiment of FIG. 52 is a modification of the embodiment of FIG. 43, except that the lower half of each contact is formed as a contact plug 70-72, respectively.
Is the same as

The embodiment of FIG. 53 is a modification of the embodiment of FIG. 52 and corresponds to the embodiment of FIG. 44, except that contact plugs 70-72 are formed below each contact. This is the same as the embodiment of FIG.

[0222]

As described in detail above, according to the present invention,
Since the contact hole connected to the lower electrode or the upper electrode of the ferroelectric capacitor constituting the ferroelectric memory and the contact hole connected to the transistor are formed as the same contact hole, two contacts which were required in the prior art are required. And the area of the memory cell can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a memory block of a chain type FRAM to which the present invention is applied.

FIG. 2A is a plan view showing a configuration of an FRAM memory cell according to an embodiment of the present invention, and FIG. 2B is a sectional view thereof.

FIG. 3 is a plan view showing a lower electrode contact of FIG. 2;

FIG. 4 is a sectional view taken along line CD of FIG. 3;

FIG. 5 is a process chart for manufacturing the memory cell configuration shown along the line DD ′ in FIG. 2;

FIG. 6 is a process chart for manufacturing the memory cell configuration shown along the line DD ′ in FIG. 2;

FIG. 7 is a process chart for manufacturing the memory cell configuration shown along the line DD ′ in FIG. 2;

FIG. 8 is a process chart for manufacturing the memory cell configuration shown along the line DD ′ in FIG. 2;

FIG. 9 is a process chart for manufacturing the memory cell configuration shown along the line DD ′ of FIG. 2;

FIG. 10 is a process chart for manufacturing the memory cell configuration shown along the line DD ′ in FIG. 2;

FIG. 11 is a plan view showing a lower electrode contact of FIG. 2;

FIG. 12 is a sectional view taken along line CD of FIG. 11;

FIG. 13 is a process chart for manufacturing another embodiment of the memory cell configuration shown along the line DD ′ of FIG. 2;

FIG. 14 is a process chart for manufacturing another embodiment of the memory cell configuration shown along the line DD ′ in FIG. 2;

FIG. 15 is a process chart for manufacturing another embodiment of the memory cell configuration shown along the line DD ′ in FIG. 2;

FIG. 16 is a process chart for manufacturing another embodiment of the memory cell configuration shown along the line DD ′ in FIG. 2;

FIG. 17 is a plan view showing a memory cell configuration according to another embodiment of the present invention.

FIG. 18 is a sectional view taken along line EF in FIG. 17;

FIG. 19 is a process chart for manufacturing another embodiment of the memory cell configuration shown along the line GH in FIG. 2;

FIG. 20 is a process chart for manufacturing another embodiment of the memory cell configuration shown along the line GH in FIG. 2;

FIG. 21 is a process chart for manufacturing another embodiment of the memory cell configuration shown along the line GH in FIG. 2;

FIG. 22 is a process chart for manufacturing another embodiment of the memory cell configuration shown along the line GH in FIG. 2;

FIG. 23 is a process chart for manufacturing another embodiment of the memory cell configuration shown along the line GH in FIG. 2;

FIG. 24 is a process chart for manufacturing another embodiment of the memory cell configuration shown along the line GH in FIG. 2;

FIG. 25 is a plan view showing a memory cell configuration according to still another embodiment of the present invention.

FIG. 26 is a sectional view taken along line AB in FIG. 25;

FIG. 27 is a process chart for manufacturing the embodiment of the memory cell configuration shown in FIG. 25 along the line GH in FIG. 2;

FIG. 28 is a process chart for manufacturing the embodiment of the memory cell configuration shown in FIG. 25 along the line GH in FIG. 2;

FIG. 29 is a process chart for manufacturing the embodiment of the memory cell configuration shown in FIG. 25 along the line GH in FIG. 2;

30 is a view showing a step of manufacturing the embodiment of the memory cell configuration shown in FIG. 25 along the line GH in FIG. 2;

FIG. 31 is a process chart for manufacturing the embodiment of the memory cell configuration shown in FIG. 25 along the line GH in FIG. 2;

32A is a plan view showing a memory cell configuration according to still another embodiment of the present invention, FIG. 32B is a cross-sectional view taken along line AB, and FIG. 32C is a sectional view taken along line CD. FIG.

FIG. 33 is a manufacturing step diagram of the embodiment in FIG. 32;

FIG. 34 is a manufacturing step diagram of the embodiment in FIG. 32;

FIG. 35 is a manufacturing step diagram of the embodiment in FIG. 32;

FIG. 36 is a manufacturing process diagram of the embodiment in FIG. 32.

FIG. 37 is a manufacturing step diagram of the embodiment in FIG. 32.

FIG. 38 is a manufacturing process diagram of the embodiment in FIG. 32;

FIG. 39 is a manufacturing process diagram of the embodiment in FIG. 32;

FIG. 40 is a manufacturing process diagram of the embodiment in FIG. 32.

FIG. 41 is a diagram showing a configuration of still another embodiment of the present invention.

FIG. 42 is a diagram showing a configuration of still another embodiment of the present invention.

FIG. 43 is a diagram showing a configuration of still another embodiment of the present invention.

FIG. 44 is a diagram showing a configuration of still another embodiment of the present invention.

FIG. 45 is a diagram showing a configuration of still another embodiment of the present invention.

46 is a view showing the manufacturing process of the FRAM in the embodiment shown in FIG. 45;

FIG. 47 is a view showing the manufacturing process of the FRAM in the embodiment shown in FIG. 45;

FIG. 48 is a manufacturing process diagram of the FRAM according to the embodiment of FIG. 45;

FIG. 49 is a view showing the manufacturing process of the FRAM according to the embodiment shown in FIG. 45;

FIG. 50 is a diagram showing a configuration of still another embodiment of the present invention.

FIG. 51 is a diagram showing a configuration of still another embodiment of the present invention.

FIG. 52 is a view showing a configuration of still another embodiment of the present invention.

FIG. 53 is a diagram showing a configuration of still another embodiment of the present invention.

FIG. 54 is a plan view showing a memory cell configuration of a conventional FRAM.

FIG. 55 is a sectional view taken along the line AB in FIG. 54;

[Explanation of symbols]

10: silicon substrate, 10A1, 10A2, 10B1: source / drain regions of transistors. 10S1, 10S2: element isolation region, 11-1, 11-2, 11-3: gate electrode, 13: capacitor lower electrode, 13c: contact hole connected to the lower electrode, 14: capacitor ferroelectric film, 15a, 15b ... Capacitor upper electrode 15w First wiring layer 18 Contact hole connected to transistor diffusion layer 22 Second interlayer insulating film 23 Third interlayer insulating film 24 Top passivation film 33 Tungsten 35, upper electrode contact; 36, a contact directly connected to the source / drain region of the transistor; 42, a silicon nitride film; 43, a silicon oxide film.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F083 AD21 FR01 FR02 GA09 JA15 JA36 JA38 JA39 JA40 JA43 KA05 KA15 KA19 MA05 MA16 MA18 MA19 PR33

Claims (21)

[Claims] A plurality of transistors formed on a semiconductor substrate; a plurality of ferroelectric capacitors formed on each of the transistors; and a ferroelectric capacitor formed by connecting the transistors and the ferroelectric capacitors in parallel. Connection means for forming a body memory cell, wherein the connection means comprises a first contact portion connected to a lower electrode of the ferroelectric capacitor and a second contact portion connected to the semiconductor substrate. A semiconductor memory device having a single contact hole formed in a state of being connected to each other. 2. The semiconductor memory device according to claim 1, wherein said contact hole is provided in a region where said ferroelectric memory cell is formed. 3. The semiconductor memory device according to claim 1, wherein the first contact portion connected to the lower electrode is connected only to a side surface of the lower electrode. 4. A plurality of transistors formed on a semiconductor substrate; a plurality of ferroelectric capacitors formed on each of the transistors; a source / drain region of the transistor; and upper and lower portions of the ferroelectric capacitor. Connecting means for connecting electrodes respectively, wherein the connecting means is connected to a first contact portion connected to a lower electrode of the ferroelectric capacitor and a second contact portion connected to the semiconductor substrate. A semiconductor memory device including a single contact hole formed in a formed state. 5. The semiconductor memory device according to claim 1, wherein there is no wiring directly connected to said contact hole immediately above said contact hole. 6. A first contact portion connected to a lower electrode of the ferroelectric capacitor and a second contact portion connected to the semiconductor substrate are integrally formed of the same conductive material. Any one of claims 1 to 5
13. The semiconductor memory device according to item 9. 7. The semiconductor according to claim 4, wherein the first contact portion connected to the lower electrode is connected only to a side surface of the lower electrode. Storage device. 8. A step of forming a plurality of transistors on a semiconductor substrate, a step of forming a ferroelectric capacitor on each of the transistors, and a step of forming a first contact hole connected to the semiconductor substrate. Forming a second contact hole connected to the lower electrode of the ferroelectric capacitor immediately above the first contact hole; and filling the first and second contact holes with a conductive material in common. Forming a single contact by using the method. 9. The processing of the first and second contact holes is performed under such a condition that the etching rate of the capacitor lower electrode is lower than the etching rate of the interlayer insulating film in which the respective contact holes are formed. 9. The method of manufacturing a semiconductor memory device according to claim 8, wherein: 10. A ferroelectric memory cell comprising: a plurality of transistors formed on a semiconductor substrate; and a ferroelectric capacitor respectively formed on an upper layer of the transistor; A single contact hole formed by connecting a first contact portion connected to the upper electrode and a second contact portion connected to the semiconductor substrate to each other. Semiconductor storage device. 11. An end of an upper electrode of a ferroelectric capacitor protruding forward of an end of a lower electrode at a position connected to the contact hole.
0. The semiconductor memory device according to item 0. 12. The method according to claim 10, wherein a wiring directly connected to the contact hole does not exist immediately above the contact hole.
13. The semiconductor memory device according to item 9. 13. The method according to claim 13, wherein a first contact connected to an upper electrode of the ferroelectric capacitor and a second contact connected to the semiconductor substrate are integrally formed of the same conductive material. The semiconductor memory device according to claim 10. 14. A step of forming a plurality of transistors on a semiconductor substrate, a step of forming a ferroelectric capacitor on each of the transistors, and a step of forming a first contact hole connected to the semiconductor substrate. Forming a second contact hole directly above the first contact hole and connected to the upper electrode of the ferroelectric capacitor; and filling the first and second contact holes with a common conductive material. Forming a single contact by using a method for manufacturing a semiconductor memory device. 15. The step of forming a ferroelectric capacitor, the step of forming an insulating film covering an upper part of the ferroelectric film;
Forming a groove for exposing the surface of the ferroelectric film by partially etching the insulating film; and embedding a conductor for an upper electrode in the groove formed by the etching. The method of manufacturing a semiconductor memory device according to claim 14. 16. A plurality of transistors formed on a semiconductor substrate; a ferroelectric capacitor formed on each of the transistors; and a ferroelectric capacitor in one of two source / drain regions serving as current paths of the transistors. Connecting means for connecting a lower electrode of the body capacitor and connecting the upper electrode to the other electrode, the connecting means being in contact with the lower electrode on at least a side surface of the lower electrode and one of the transistors below. A semiconductor memory device having a lower electrode contact connected to a source / drain region. 17. The device according to claim 16, wherein the lower electrode has a region having a pattern size in which a portion contacting the lower electrode contact is smaller than a region where the upper electrode is formed. Semiconductor storage device. 18. The lower electrode is provided for each of the ferroelectric capacitors corresponding to and adjacent to the upper electrode, and the lower electrode contact is simultaneously contacted with both of the two adjacent lower electrodes. 18. The semiconductor memory device according to claim 16, wherein the semiconductor memory device is arranged in a semiconductor device. 19. A step of forming a transistor on a semiconductor substrate; a step of depositing a first interlayer insulating film on the formed transistor and flattening; and a step of forming a lower electrode of a ferroelectric capacitor after flattening. Conductive film,
A step of sequentially depositing a ferroelectric film and a conductive film for an upper electrode; and a step of forming the lower electrode conductive film on a lower electrode having a pattern narrowed between two correspondingly formed upper electrodes. Forming a plurality of upper electrodes by dividing the upper electrode conductive film for each ferroelectric capacitor, depositing a second interlayer insulating film, and forming an upper electrode contact on the second interlayer insulating film. Forming a first source / drain contact hole to expose a first source / drain region so as to contact a side surface of the thinned portion of the lower electrode, Opening a second source / drain contact hole for connecting to the source / drain region; and forming the upper electrode contact hole and the first and second source / drain contact holes. A step of filling a conductive material into the Kutohoru method of manufacturing a semiconductor memory device characterized by comprising a step of forming a wiring by processing the conductive material. 20. A step of forming a transistor on a semiconductor substrate, a step of depositing a first interlayer insulating film on the transistor and flattening the same, and a step of forming a conductive layer connected to a source / drain region of the transistor after the flattening. Forming a plug of a material, depositing a second interlayer insulating film, depositing a conductive film for a lower electrode, a ferroelectric film, and a conductive film for an upper electrode of the ferroelectric capacitor; Forming the conductive film for the lower electrode on the lower electrode in a pattern narrowed between the upper electrodes formed correspondingly; and dividing the conductive film for the upper electrode into ferroelectric capacitors. A step of forming a plurality of upper electrodes; a step of depositing a third interlayer insulating film; a step of opening an upper electrode contact hole in the third interlayer insulating film; A first contact hole is opened so as to be in contact with the side surface of the portion to be exposed, and at least an upper surface of the plug is exposed, and at the same time, an upper electrode is connected to the first contact hole to connect an upper electrode to the source / drain region. A step of opening a second contact hole; a step of filling a conductive material in the upper electrode contact hole and the first and second contact holes; a step of processing the conductive material to form a wiring; A method for manufacturing a semiconductor memory device, comprising: 21. A step of forming a transistor on a semiconductor substrate, a step of depositing a first interlayer insulating film on the transistor and planarizing the same, and a plug made of a conductive material in a source / drain region of the transistor after the planarization. Forming a second interlayer insulating film; depositing a conductive film for a lower electrode, a ferroelectric film, and a conductive film for an upper electrode of a ferroelectric capacitor; Forming a plurality of upper electrodes by dividing the conductive film for each ferroelectric capacitor corresponding to the upper electrode, and forming a plurality of upper electrodes by dividing the conductive film for the upper electrode for each ferroelectric capacitor, Depositing a third interlayer insulating film; opening an upper electrode contact hole in the third interlayer insulating film; at least each side of the two adjacent divided lower electrodes A first contact hole is opened so as to simultaneously contact the surface, and at least the upper surface of the plug is exposed, and at the same time, a first electrode is communicated directly above the first contact hole for connecting an upper electrode to the source / drain region. A step of opening a second contact hole; a step of filling the upper electrode contact hole and the first and second contact holes with a conductive material; and a step of forming a wiring by processing the conductive material family. And a method for manufacturing a semiconductor memory device.