JP2993039B2 - Active layer stacked device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active layer laminated device, and more particularly, to a structure of an electrode wiring of an active layer laminated device.

[Conventional technology]

Conventionally, formation of electrodes on upper and lower transistors of an SOI (semiconductor-on-insulator) structure element having an active layer two-layer structure has been performed as follows. FIG. 2 is a schematic cross-sectional view of an active layer laminated device manufactured by a conventional technique.

First, a lower transistor including a drain 5, a source 7, and a gate 6 made of polycrystalline silicon is formed on the surface of a silicon substrate 1 which is a semiconductor substrate on which an element isolation oxide film 2 is formed. One silicon oxide film 3 is formed. Next, a silicon film is formed on the first silicon oxide film 3, and an upper transistor including a drain 5a, a source 7a, and a gate 6a made of polycrystalline silicon is formed on the silicon film and the silicon film. A second silicon oxide film 4 is formed on the entire surface.

Next, contact holes are formed in the second and first silicon oxide films 4 and 3 at predetermined positions on the gate 6, drain 5 and source 7 of the lower transistor by an exposure process using a photoresist and a dry etching process. Then, tungsten is buried in the contact hole by CVD to form a columnar electrode 8. Thereafter, a tungsten film is further deposited, and a pedestal electrode 11 surrounding the contact hole and connected to the columnar electrode 8 is formed by an exposure step using a photoresist and a dry etching step of tungsten.

Finally, a third silicon oxide film 9 is deposited on the entire surface, and the third silicon oxide film 9 on the pedestal electrode 11 and the gates 6a, After forming contact holes in the third and second silicon oxide films 9 and 4 at predetermined positions on the drain 5a and the source 7a, aluminum is deposited and patterned to form a wiring 10 between elements. I was

In FIG. 2, only contact holes for the drains 5 and 5a are shown for the contact holes for the lower and upper transistors for easy understanding.

[Problems to be solved by the invention]

However, in the above-mentioned conventional active layer laminated device,
Gate 6, drain 5, and source 7 of lower layer transistor
Between the silicon 10 and the wiring 10 made of aluminum at a predetermined position of the silicon, the columnar electrode 8, the columnar electrode 8, and the pedestal electrode.
11, and three interfaces of the pedestal electrode 11 and the wiring 10 exist,
In addition, since the contact area of the three interfaces is small, the contact characteristics between the wiring 6 made of silicon and aluminum at predetermined positions of the gate 6, the drain 5, and the source 7 of the lower transistor are determined by the interface of these three interfaces. It depends on the state accumulated in the state, and in particular, the contact resistance becomes a high value, and in addition, the contact resistance becomes easily scattered.

Further, since the depth of the contact hole with respect to the upper transistor is only as large as the thicknesses of the third and second silicon oxide films 9 and 4, disconnection of the wiring 10 made of aluminum in the contact hole is seen from the aspect ratio aspect. There is a problem that it is easy to occur.

[Means for solving the problem]

An active layer stacked device of the present invention includes: a lower transistor formed on a surface of a semiconductor substrate; a first insulating film formed on the entire surface of the semiconductor substrate including the lower transistor; and a first insulating film formed on a surface of the first insulating film. An upper-layer transistor, a second insulating film formed on the entire surface of a first insulating film including the upper-layer transistor, and a first insulating film formed on second and first insulating films on predetermined positions of the lower-layer transistor. A columnar electrode made of a first metal buried in the first contact hole and having a protrusion at a predetermined height above the first contact hole; and a predetermined position of the upper transistor A second contact hole formed in the upper second insulating film, and a protruding portion of the columnar electrode connected to the predetermined position of the lower transistor, and There have been constituted by the containing and made of a second metal connected to a predetermined position wiring structure of the upper layer transistors.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a schematic sectional view for explaining one embodiment of the present invention. Hereinafter, description will be made in the order of manufacturing steps.

First, after an element isolation oxide film 2 is formed on a silicon substrate 1 which is a semiconductor substrate, a gate 6 made of polycrystalline silicon is formed via a gate oxide film. To form a lower transistor. Next, a first silicon oxide film 3, which is a first insulating film, is formed on the entire surface. Subsequently, a polycrystalline silicon film is formed on the first silicon oxide film 3, and the polycrystalline silicon film is converted into a single-crystal silicon film by a method such as laser annealing, and then a gate oxide film is formed thereon. Forming a gate 6a made of polycrystalline silicon through
Next, an impurity is introduced into the silicon film to form a drain 5a and a source 7a, thereby forming an upper transistor. Next, the entire surface is covered with a second silicon oxide film 4 which is a second insulating film.

Next, a second contact hole is formed in the second silicon oxide film 4 at a predetermined position on the gate 6a, the drain 5a, and the source 7a of the upper transistor by an exposure process using a photoresist and a dry etching process. Then, a third silicon oxide film (not shown) is deposited on the entire surface by a CVD method. Since the third silicon oxide film only needs to have a sufficient thickness to cover the second contact hole when a columnar electrode is formed in a later step, the third silicon oxide film used in the prior art is sufficient. It may be thinner than the film thickness.

Next, by an exposure process using a photoresist and a dry etching process, the second and first silicon oxide films 4 and 3 and the third silicon oxide film 3 at predetermined positions on the gate 6, the drain 5 and the source 7 of the lower transistor are formed. After forming a first contact hole in the oxide film, using a mixed gas of WF ₆ and SiH ₄ at a mixing ratio of 1: 1 using H ₂ as a carrier gas, the first metal in an environment at a temperature of 300 ° C. CVD growth of tungsten. Under this condition, tungsten is deposited only on the silicon surface and not on the silicon oxide film. As a result, the columnar electrode 8a made of tungsten is formed only in the first contact hole.

In FIG. 1, for the sake of easy understanding, the contact holes for the lower and upper transistors are only shown for the drains 5 and 5a.

Next, the third silicon oxide film deposited on the entire surface is removed by dry etching. As a result, a part of the side surface and the upper surface of the columnar electrode 8a are exposed to form a projection of the columnar electrode 8a having a height corresponding to the thickness of the third silicon oxide film, and the second contact hole is formed. Since the third silicon oxide film that has been covered is also removed at the same time, a structure in which the silicon at the predetermined positions of the gate 6a, the drain 5a, and the source 7a of the upper transistor is exposed is formed.

Finally, aluminum as the second metal is deposited, and the columnar electrode 8a and the gate 6a,
Aluminum is patterned so as to fill a mask margin between the drain 5a and the source 7a and the second contact hole formed at the predetermined position, thereby forming a wiring 10 between elements.

As described above, according to the present embodiment, between the gate 6, the drain 5, and the source 7 in the lower layer transistor, the silicon and the columnar electrode 8 a, and the columnar Since only two interfaces between the electrode 8a and the wiring 10 exist and no interface between the "columnar electrode 8 and the pedestal electrode 11" exists in the conventional device, the influence of the interface state on the contact characteristics is reduced as compared with the related art. In addition, the connection between the wiring 10 and the columnar electrode 8a is performed by
8a, the contact area between the wiring 10 and the columnar electrode 8a is larger than in the past, and the wiring 10 and the columnar electrode 8a are larger.
The effect on the contact characteristics by the interface with 8a is very small. As a result, the contact characteristics of the interface between the silicon at the predetermined position of the gate 6, the drain 5, and the source 7 of the lower transistor and the columnar electrode 8a are affected by the interface state, and the contact The stability of the characteristics is improved, and in particular, the value of the contact resistance is low and the variation is reduced.

Further, according to the present embodiment, since the third silicon oxide film does not exist at the stage when the wiring 10 is formed, the depth of the second contact hole becomes shallow, and the second contact hole for the upper transistor is formed. The aspect ratio of the wiring 10 is improved, and the disconnection of the wiring 10 here is reduced.

Further, in this embodiment, the number of photolithography steps for forming the electrode wiring is reduced twice as compared with the related art.

In this embodiment, a silicon film is used as a semiconductor film, which is a constituent material of the upper transistor, a silicon oxide film is used as the first and second insulating films, a silicon substrate is used as a semiconductor substrate, and a second metal is used. Aluminum was used as the wiring material, and tungsten was used as the material for the columnar electrode, which was the first metal. However, other types of semiconductor films, other types of insulating films, other types of semiconductor substrates, and other types of semiconductor films were used. Wiring materials and other types of metals may be used.

〔The invention's effect〕

As described above, according to the present invention, each electrode to the upper layer and the lower transistor of the SOI structure element having the active layer two-layer structure is formed using a contact hole having a depth smaller than that of the conventional transistor for the upper layer transistor, The lower transistor is formed by interposing a columnar electrode whose upper end protrudes from the surface of the second insulating film covering the upper transistor.

As a result, between the silicon at the position of the first contact hole provided in the lower-layer transistor and the wiring made of aluminum as the second metal, the structure made of silicon and tungsten as the first metal is formed. There is only the pillared electrode and the two interfaces between the pillared electrode and the wiring, and the interface between the pillared electrode and the pedestal electrode, which existed in the conventional device, does not exist. I do. In addition, since the connection between the wiring and the columnar electrode is formed by the protrusion of the wiring and the columnar electrode,
The contact area between the wiring and the columnar electrode becomes larger than before, and the influence on the contact characteristics due to the interface between the wiring and the columnar electrode becomes very small. Therefore, the contact characteristics are affected by the interface state of the interface between the silicon and the columnar electrode, and the stability of the contact characteristics is improved as compared with the related art. In particular, the contact resistance value is low and the variation is reduced. You.

In addition, at the stage when the wiring made of aluminum, which is the second metal, is formed, the third element existing in the conventional element was formed.
Since the silicon oxide film does not exist, the depth of the second contact hole is reduced, the aspect ratio of the wiring in the second contact hole with respect to the upper transistor is improved, and the disconnection of the wiring is reduced.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of one embodiment of the present invention, and FIG. 2 is a schematic sectional view of a conventional active layer laminated device. 1, a silicon substrate, 2, an element isolation oxide film, 3, a first silicon oxide film, 4, a second silicon oxide film, 5,
5a …… Drain, 6,6a …… Gate, 7,7a …… Source, 8,
8a ... pillar-shaped electrode, 9 ... third silicon oxide film, 10 ...
Wiring, 11 ... pedestal electrode.

Continuation of the front page (51) Int.Cl. ⁶ identification code FI H01L 29/786 (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 27/00 301 H01L 21/285 H01L 21/768 H01L 21 / 8234 H01L 27/088 H01L 29/786

Claims (1)

(57) [Claims] A lower transistor formed on a surface of the semiconductor substrate; a first insulating film formed on the entire surface of the semiconductor substrate including the lower transistor; and a first insulating film formed on a surface of the first insulating film. An upper transistor, a second insulating film formed on the entire surface of the first insulating film including the upper transistor, and a second insulating film formed on a predetermined position of the lower transistor. A first contact hole, and a columnar electrode made of a first metal buried in the first contact hole and having a protrusion having a predetermined height formed above the first contact hole; A second contact hole formed in the second insulating film on a predetermined position of the upper transistor; and the predetermined position of the lower transistor in the protrusion of the columnar electrode. And a wiring made of a second metal connected to the predetermined position of the upper transistor in the second contact hole.