JP2000269328A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to control the depth of a wiring groove with good accuracy without using an etching stopper, such as a silicon nitride film, and to contrive to enhance the quality of a buried wiring. SOLUTION: A first interlayer insulating film 12, which is a layer 20 with the silicon-rich uppermost surface, is deposited on a conductor film 11, and a second interlayer insulating film 13 is deposited on this film 12. After that, the films 12 and 13 are etched and a through hole 15 is formed in the film 12. Then the plasma impedance during etching is monitored to detect the silicon- rich layer 20, whereby etching is made to stop and a wiring groove 17 is formed in the film 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buried wiring technique which is one of methods for forming a multilayer wiring of a semiconductor device, and more particularly to a semiconductor device for forming a buried wiring groove in an interlayer insulating film and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, multi-layer wiring has been used in accordance with high integration and high density of semiconductor devices.

FIGS. 12 to 17 show a method of manufacturing a conventional embedded wiring.

As shown in FIG. 12, first, an interlayer insulating film 12 is deposited on a conductor 11 such as an aluminum wiring. This interlayer insulating film 12 may be deposited on a diffusion layer on a substrate or on polysilicon. Next, the interlayer insulating film 1
2 is coated with a first resist layer 14. Thereafter, the resist layer 14 is patterned by exposure and development so as to correspond to through holes described later.

Next, the interlayer insulating film 12 is etched using the patterned resist layer 14 as a mask,
As shown in FIG. 13, a through hole 15 exposing the underlying conductor 11 is formed. After that, the resist layer 14 is removed.

Next, a second resist layer 16 is applied on the interlayer insulating film 12. Thereafter, as shown in FIG. 14, the resist layer 16 is patterned by exposure and development so as to correspond to a wiring groove described later.

Next, using the patterned resist layer 16 as a mask, the interlayer insulating film 12 is etched to a certain depth, and as shown in FIG.
7 is formed. After that, the resist layer 16 is removed.

Next, as shown in FIG. 16, aluminum is formed on the through holes 15, the wiring grooves 17, and the interlayer insulating film 12.
Alternatively, a wiring material 18 such as copper is deposited. After the wiring material 18 is deposited, it may be embedded in the through hole 15 and the wiring groove 17 by reflowing by heat treatment or the like.

After that, the wiring material 18 is
And the interlayer insulating film 1 is left only in the wiring groove 17.
The wiring material 18 on the substrate 2 is removed by etching or polishing, and as shown in FIG. 17, an embedded wiring 18a having a dual damascene structure is formed.

[0010]

In the above-mentioned conventional method of manufacturing a buried wiring, the formation of the wiring groove 17 involves etching the interlayer insulating film 12 to a desired depth by controlling the etching time. Therefore, the interlayer insulating film 1
Variations occur in the depth of the wiring groove 17 due to a change in the film quality of No. 2 or a change in the etching rate. as a result,
There has been a problem that electrical characteristics such as wiring resistance or interlayer capacitance fluctuate, and device characteristics deteriorate.

In order to avoid the above problem, there is a method of inserting a silicon nitride film into an interlayer insulating film and using the silicon nitride film as a stopper at the time of etching for forming a wiring groove.

However, in this case, there is a problem in that the presence of the silicon nitride film having a high relative dielectric constant causes an increase in the interlayer capacitance with the lower wiring, thereby deteriorating the device characteristics such as a reduction in the operation speed of the device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to control the depth of a wiring groove accurately without using an etching stopper such as a silicon nitride film and to embed the wiring groove. It is an object of the present invention to provide a semiconductor device capable of improving the quality of wiring and a method for manufacturing the same.

[0014]

The present invention uses the following means to achieve the above object.

A semiconductor device according to the present invention includes a conductor, an insulating film provided on the conductor, a connection hole formed in the insulating film and exposing the conductor, and a connecting hole formed in the insulating film. A wiring groove communicating with the connection hole; and a silicon-rich layer provided in the insulating film around a bottom of the wiring groove.

A semiconductor device according to the present invention includes: a conductor; a first insulating film provided on the conductor; a connection hole formed in the first insulating film to expose the conductor; A second insulating film provided on the first insulating film;
A wiring groove formed in the insulating film and communicating with the connection hole, and a silicon-rich layer provided at an interface between the first insulating film and the second insulating film.

According to the method of manufacturing a semiconductor device of the present invention, a step of depositing a first insulating film on a conductor to be a silicon-rich layer having a composition of a film surface containing more silicon than a layer under the film is provided; Depositing a second insulating film on the insulating film, forming a connection hole exposing the conductor in the first and second insulating films, etching the second insulating film, By monitoring the plasma impedance during this etching, the silicon-rich layer of the first insulating film is detected and the etching is stopped, thereby forming a wiring groove communicating with the connection hole.

Further, the first insulating film is deposited to a thickness not less than the depth of the connection hole, and the second insulating film is deposited to a thickness not more than the depth of the wiring groove. In the forming step, the wiring trench may be formed by performing just etching until the silicon-rich layer of the first insulating film is detected, and further over-etching to a layer below the silicon-rich layer.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing only the conductor of the embedded wiring of the present invention. As shown in FIG. 1, a wiring 18a is formed on conductor 11 via an interlayer insulating film (not shown).
The wiring 18a is made of a conductor 11 made of a wiring material embedded in a through hole 15 formed in the interlayer insulating film.
It is connected to the.

Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described with reference to a cross section taken along line 10-10 of FIG.

First, as shown in FIG. 2, a first interlayer insulating film 12 is deposited on a conductor 11 such as each wiring layer in a multi-layered wiring by a thickness in consideration of a depth of a through hole described later. . The first interlayer insulating film 12 is made of, for example, plasma C
This is a silicon oxide film deposited by VD (Chemical Vapor Deposition). The CVD is performed so that the outermost surface of the first interlayer insulating film 12 becomes the silicon-rich layer 20 containing more silicon than the lower layer when the plasma discharge is stopped. The device is controlled.

Thereafter, as shown in FIG. 3, a second interlayer insulating film 13 is deposited on the first interlayer insulating film 12 to a depth of a buried wiring groove to be described later.

Next, a first resist layer 14 is applied on the second interlayer insulating film 13, and as shown in FIG. 4, the first resist layer 14 is exposed to light and developed so as to correspond to a through hole described later. Is patterned.

Next, using the patterned first resist layer 14 as a mask, the first and second interlayer insulating films 1 are formed.
2 and 13 are etched to form a through hole 15 exposing the underlying conductor 11 as shown in FIG.
After that, the first resist layer 14 is removed.

Next, a second resist layer 16 is applied on the second interlayer insulating film 13. Thereafter, as shown in FIG. 6, the resist layer 16 is patterned by exposure and development so as to correspond to a wiring groove described later.

The second interlayer insulating film 13 is plasma-etched using the patterned resist layer 16 as a mask. At this time, for example, by monitoring the current or voltage output from the high-frequency power supply of the plasma etching apparatus and measuring the plasma impedance during etching, as shown in FIG. 11, the first interlayer insulating film 12 and the second The plasma impedance of the silicon-rich layer 20 at the interface with the film 13 decreases. Therefore, by monitoring the plasma impedance, the silicon rich layer 20 is detected, and the etching is stopped. After that, the resist layer 16 is removed, and a buried wiring groove 17 is formed as shown in FIG.

FIG. 8 shows the silicon rich layer 20 shown in FIG.
The enlarged view of the periphery is shown. As shown in FIG. 8, the etching of the wiring groove 17 is just etched until the silicon-rich layer 20 is detected.
Over-etched to the lower layer. After the formation of the wiring groove 17, the silicon-rich layer 20 is left in the first interlayer insulating film 12 around the bottom of the wiring groove 17, for example.

Thereafter, as shown in FIG. 9, a wiring material 18 such as aluminum or copper is deposited on the through holes 15, the wiring grooves 17, and the second interlayer insulating film 13. After the wiring material 18 is deposited, it may be embedded in the through hole 15 and the wiring groove 17 by reflowing by heat treatment or the like.

After that, the wiring material 18 is
The wiring material 18 on the second interlayer insulating film 13 is removed by etching or polishing so as to remain only in the wiring groove 17. As a result, as shown in FIG. 10, a buried interconnect 18a having a dual damascene structure is formed.

According to the above embodiment, in forming the wiring groove 17, by detecting a sudden change in plasma impedance, the silicon-rich portion at the interface between the first interlayer insulating film 12 and the second interlayer insulating film 13 is detected. Layer 20 can be detected. Therefore, since the etching can be stopped at a desired depth, the depth of the wiring groove 17 can be accurately controlled.

The present invention is not limited to the above embodiment. For example, the conductor 11 may be not only an aluminum wiring but also a diffusion layer on a substrate or polysilicon.

In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0034]

As described above, according to the present invention, it is possible to control the depth of the wiring groove with high precision without using an etching stopper such as a silicon nitride film, thereby improving the quality of the embedded wiring. And a method for manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device according to the present invention.

FIG. 2 is a sectional view of a manufacturing process of the semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the present invention.

FIG. 5 is a sectional view of a manufacturing step of a semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view of a manufacturing step of the semiconductor device according to the present invention.

FIG. 7 is a sectional view of a manufacturing step of the semiconductor device according to the present invention.

FIG. 8 is an enlarged view of the silicon-rich layer shown in FIG.

FIG. 9 is a sectional view of a manufacturing step of the semiconductor device according to the present invention.

FIG. 10 is a sectional view of a manufacturing step of a semiconductor device according to the present invention.

FIG. 11 is a diagram showing a variation in plasma impedance during etching of a wiring groove.

FIG. 12 is a sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 13 is a sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 14 is a sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 15 is a sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 16 is a cross-sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

FIG. 17 is a sectional view of a manufacturing process of a semiconductor device according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Conductor, 12 ... 1st interlayer insulating film, 13 ... 2nd interlayer insulating film, 14 ... 1st resist layer, 15 ... Through hole, 16 ... 2nd resist layer, 17 ... Wiring groove, 18 ... wiring material, 18a ... wiring, 20 ... silicon-rich layer.

Claims (4)

[Claims] A conductor, an insulating film provided on the conductor, a connection hole formed in the insulation film to expose the conductor, and a connection hole formed in the insulation film. A wiring groove communicating with the wiring groove, and a silicon-rich layer provided in the insulating film around a bottom of the wiring groove. 2. A conductor, a first insulating film provided on the conductor, a connection hole formed in the first insulating film to expose the conductor, and a first insulating film. A second insulating film provided on the film, a wiring groove formed in the second insulating film and communicating with the connection hole, and an interface between the first insulating film and the second insulating film And a silicon-rich layer provided on the semiconductor device. 3. A step of depositing a first insulating film on a conductor to be a silicon-rich layer having a film surface composition containing more silicon than a layer below the conductor, and a second insulating film on the first insulating film. Depositing a film, forming a connection hole exposing the conductor in the first and second insulating films, etching the second insulating film, and monitoring plasma impedance during the etching. Forming a wiring groove communicating with the connection hole by detecting the silicon-rich layer of the first insulating film and stopping the etching. 4. The method according to claim 1, wherein the first insulating film is deposited to a thickness not less than the depth of the connection hole, and the second insulating film is deposited to a thickness not more than the depth of the wiring groove. Forming a wiring groove by performing just etching until the silicon-rich layer of the first insulating film is detected, and further over-etching to a layer below the silicon-rich layer. 4. The method for manufacturing a semiconductor device according to item 3.