TW516182B - Manufacturing method of dual damascene structure - Google Patents

Abstract

A manufacturing method of dual damascene structure is provided. First, a first etch stop layer, a first dielectric layer, a second etch stop layer, a second dielectric layer and a hard mask layer are sequentially formed. Then, a contact hole is formed in the mask layer, second dielectric layer, second etch stop layer and first dielectric layer till exposing the first etch stop layer surface that corresponds to the conductive region. Second, a sacrificial protection layer is used to completely fill the contact hole. Then the etching recipe with etch selectivity between the mask layer and sacrificial protection layer smaller than one is chosen to selectively etch the mask layer and sacrificial protection layer till etching the sacrificial protection layer to a predetermined depth. Finally, the etching recipe with etch selectivity ratio between the mask layer and sacrificial protection layer larger than one is chosen to selectively etch the mask layer, second dielectric layer and sacrificial protection layer till exposing the second etch stop layer to form a trench. The sacrificial protection layer is removed to construct a dual damascene structure. An I-line photo resistor is used as the sacrificial layer, which can eliminate the conventional void issue, exactly prevent punch-through of the bottom etch stop layer and thus increase product yield.

Description

516182

The present invention is related to semiconductor integrated circuits (ICs) ^ Μ ^ ^ manufacturing technology of semiconductor circuits, and in particular, it is related to the manufacturing method of dual damascene, Ganding y layer (b. U〇m stop iaya) can not be / can be etched through the underlying etch stop «,-a _., Y} The punch-through problem is connected: a hole is formed in the process of forming a sacrificial protective layer. Enough: Accumulation: The accumulation degree of = is increased, so that the chip surface cannot provide the required internal wiring. To meet the shrinkage of M0S component size = the wiring needs *, two or more layers of metal Layer design, which means that the integrated circuit must be used, especially some functions.

: Ϊ Ϊ product's mouth, such as a microprocessor, even requires four to five layers of metal two 'ί: ί Ϊ to form the connection between the various components within the microprocessor. -Generally, the production of interconnects is opened after the main body of the discussion is completed. This process can be regarded as an independent semiconductor process. In order to prevent the short circuit between the first & metal M wire and the second metal wire directly, the metal inner wires must be separated by an insulating layer (ie, an inner metal) and an electrical layer (IMD). The conventional way to connect the upper and lower metal inner wires is to use plugs, such as tungsten plugs and aluminum plugs.

First, the known metal interconnection process mainly uses the lithography process and etching technology to define the contact channel, and then forms a barrier layer on the surface of the contact channel to increase the metal layer and the inner metal of the trench. Adhesion between the dielectric layers; after that, tungsten is filled into the trench by tungsten etch-back, and then a titanium nitride layer for isolation is deposited on the surface of the structure formed above, and finally a deposit is made. The copper alloy is on its surface, and then it is defined by reactive ion etching. It is composed of tungsten plugs and is used for connection.

516182 V. Description of the invention (2) Double-ditch connection channel for metal interconnection. However, the conventional metal interconnection process of c 'has been unsuitable; disadvantages. ：: =) the width of the line = the semiconducting element whose outer line width is less than 0.25 // IIΠ, 2 the copper with better conductivity is used as the material guide of the metal interconnect, and the body is ===== -10 ... Materials must be provided = low. Japan can reduce the RC-delay effect of this microelectronic component to the lowest. Refer to Figure 1, which is a cross-section of a dual damascene structure formed by conventional technology. This structure is filled with copper metal and flattened with copper metal. Into copper metal interconnects. 7 The step of forming the above-mentioned FIG. 1 is to sequentially form an etch stop layer on the semiconductor substrate formed with the conductive region, such as an interconnect, and the dielectric layer, the etch stop layer, and the dielectric layer. The electric layer 20 and the anti-reflection shielding layer 22, and then the conventional anti-reflection shielding layer 22, the dielectric layer 20, the etch stop layer 18, and the dielectric layer 16 are selectively etched by using conventional lithography technology until the above-mentioned money stop layer is exposed. 14 to form a contact hole 24. Next, the above-mentioned contact hole 24 is filled with a spin coating method, for example, a polymer such as poly (arylene ether) polymer. A specific example is PAE-2 manufactured by Schumacher. Or FLARE, HOSP, LOSP and other organic polymer materials manufactured by A1Ued Signal Company are used as the sacrificial protection layer 26 in the subsequent etching step to prevent the above-mentioned bottom etching stop layer 14 from being damaged. Page 6 516182 V. Description of the invention (3) However, the size of the contact hole 24 has gradually been reduced to below 0.3 m, and the above-mentioned conventional organic material used as the sacrificial protective layer 26 has a viscosity and a uniform filling degree. With good characteristics, it is easy to produce organic raw materials such as 枓, === voids 30, which will greatly affect the protection effect of the sacrificial protection layer 26 in the process of trench etching. Problem of the present invention

Fabrication method, using Bu 1-Photoresistive material as S hole II: It has excellent trench filling ability, can eliminate the conventional, and indeed prevents the bottom layer from stopping the layer of money to pass through, increasing production. According to the above object, the present invention provides a method of a dual damascene structure, which is suitable for a semiconductor substrate having a conductive region. The steps include sequentially forming a first etched layer and a five-layered layer on the semiconductor substrate: a second etch stop layer, a second dielectric layer. Electrical layer and one hard: cover two; contact holes in the hard mask layer, the second dielectric layer, the second etch stop layer and the first dielectric layer until the first etch stop layer is exposed. 1 用 = : The above contact hole is filled with i_line photoresist material; then, to make the second: the hard mask layer and the i-be photoresist material are selectively etched into the hard mask layer and the substrate by selective etching than the photoresist material. Hne uses the above-mentioned second dielectric layer and the above-mentioned hard mask layer with: two = photo m engraving selection ratio is greater than one, selectively engraving the above-mentioned hard-shielding second dielectric layer and the above-mentioned photo resist Material until the above-mentioned scratched neodymium stop layer is exposed to form a trench, Constituting the dual damascene structure. 0503-6497TW; TSMC200-l-ii55; dennis.ptd page 7 5 Description of the invention (4) The steps of manufacturing the photoresistive material in the dual-mosaic structure. Secondly, it includes removing the contact hole, the etching stop layer is a silicon nitride or silicon oxynitride layer, an etching stop layer and a second etch, and a dielectric layer is silicon dioxide. Alas. In addition, the first dielectric layer and the second dielectric layer are a hard masking layer formed on an oxynitride stone or an organic bottom anti-reflection layer, for example, light = two pairs == production method The engraving of the trench-based layer is performed simultaneously. * Upward photoresist layer and removal of the aforementioned sacrificial protection

Understand that the above-mentioned objectives, features, and advantages of the present invention can be more obvious. Yi Si will give a preferred embodiment with the accompanying drawings, which will be described in detail as follows. The drawings are briefly explained. The first picture is conventional. A schematic cross-sectional view of a dual damascene structure used to fill copper interconnects. Figures 2a to 2f are schematic cross-sectional views of the manufacturing process of the dual-silver embedded structure according to the embodiment of the present invention. Figures 3a to 3f are schematic cross-sectional views of the manufacturing process of a dual mosaic structure according to another embodiment of the present invention.

[Symbol description] 100 ~ semiconductor (silicon) substrate; 102 ~ conducting area; 104, 108 ~ etch stop layer; 106, 110 ~ intermetal dielectric layer;

0503-6497TWF; TSMC2001-0155; dennis.ptd p. 8 516182

11 2 ~ anti-reflection shielding layer; 11 3 ~ contact hole; 11 4, 11 4 a ~ sacrificial protection layer; 11 6 ~ photoresist pattern for trench remaining; 1 2 0 ~ trench. EXAMPLES The first embodiment of the present invention will be described in more detail using the process chart of the dual mosaic structure shown in Figs. 2a to 2f. Baixian, please refer to FIG. 2a. The step of forming the cross-sectional view is to form a first etch stop layer 104 on a semiconductor substrate 100 having a conductive region 102 (such as a copper interconnect). , The first dielectric layer 106, the second etch stop layer 108, the second dielectric layer 丨 丨 0, the hard mask layer 丨 丨 2, and then the conventional lithography technique and selective etching of the hard mask are used. The cap layer 112, the second dielectric layer 110, the second etch stop layer 108, and the first dielectric layer 106 are exposed until the first etch stop layer 104 is exposed to form a contact hole 3. For example, a positive photoresist is first coated on the hard mask layer 112, and the positive photoresist layer is exposed and developed through a photomask at the position of the contact hole to form a photoresist mask. Next, using the photoresist mask as a mask, the hard mask is etched, 112, the second dielectric layer 110, the second etch stop layer 108, and the third dielectric layer 106 until the first etch stop layer is exposed. Up to 104, a contact hole 113 is formed at the relative position of the conductive region. Next ’is filled with i-Une photoresist material 114 into the contact hole 113 by spin coating, and then pre-baked at an appropriate temperature.

V. Description of the invention (6) Baking is used as a sacrificial protective layer for subsequent etching steps to avoid damage to the above-mentioned first etch stop layer 104. ^ The dielectric layers 106 and 11 are, for example, silicon dioxide layers or other low dielectric constant material layers formed by chemical vapor deposition. The first and second etch stop layers 104 and 108 and the hard mask layer 112 are formed by Composed of silicon nitride or oxynitride. Due to the low viscosity of i-line photoresist materials and other material characteristics, it is suitable for contact holes with extremely small size (for example, less than 0.3 m). • Next, please refer to Figure 2b, etching back the above 1-1 / ne photoresist material 11 4 to leave the entire contact hole 丨 3 as a sacrificial protective layer 114a. The method uses the operating conditions of pressure 100 mt rr / power 50 0 W / oxygen flow rate 20 sccm / nitrogen flow rate 10 sccm. Then, please refer to Figure 2c and apply lithography to apply deep UV (deep UV ) Photoresist material, exposure, development, baking and other steps to form a photoresist pattern 1 6 for trench etching. Secondly, please refer to the engraving mask, and then use the etched rate of the resist material 11 4 a and the etch rate of 11 2 to selectively etch 114 a until i is above. Next, please refer to the 2d diagram of the second dielectric etching selection ratio greater than one, and use the photoresist pattern 116 as an etching method to select the hard mask layer 112 and the I-nne light selection ratio less than one. That is, the hard mask layer I is engraved with the hard mask layer 112 of the photoresist material 114a and the i-line photoresist material 1 ine photoresist material 11 4 a. Figure 2e, and then use the above-mentioned hard mask layer 丨 12 layer 110 and the 1-1 ine photoresist material η 4a etching method, that is, the photoresist material 11 4a is etched 516182 5. Description of the invention (7) rate 'Large than the above-mentioned hard mask layer 112 and the second dielectric layer 110 are etched; the optional hard mask layer 丨 丨 2, the second dielectric layer 丨 丨 and the above i-1 ine photoresist material 114a until the second etch stop layer 108 is exposed to form a trench 1220, which forms a dual damascene structure with the contact hole 丨 3. Through the above-mentioned two-stage etching selection ratios, the i-1 ine photoresist 114 is etched with a strong etching formula, and the i-line photoresist 114 is etched first. Next, the hard mask layer 112 and the second dielectric layer are etched with a strong etch resistance until the second stop layer is exposed, thereby preventing incomplete etching during the etching process. (Burr), which causes errors in subsequent processes, which leads to RC open circuit. Next, please refer to FIG. 2f, and remove both the photoresist pattern 116, the hard mask layer Η, and the i-line photoresist material by dry and wet methods. The later results also include the steps of removing the first etch stop layer 104 to expose the surface 102 of the conductive region ', and filling metal such as copper to form interconnects, which are not described here. The second embodiment of the present invention will be described in more detail below using the process cross-sectional views of the dual mosaic structure shown in Figs. 3a to 3f. First, please refer to FIG. 3a. The step of forming the cross-sectional view is to form an etch stop layer 104 and a dielectric layer on the semiconductor substrate 100 on which a conductive region 202 (such as a copper interconnect) is formed. Electrical layer 206, a hard mask layer 212, and then using conventional lithography techniques and selective etching of the hard mask layer 212 and the dielectric layer 206 until the etching stop layer 204 is exposed to form a contact Hole 2 1 3. For example, first, apply two layers on the hard mask layer 2 丨 2.

516182 V. Description of the invention (8)-Layer positive photoresist 'Through a photomask, the positive photoresist layer is exposed and developed at the position where a contact hole is to be formed to form a photoresist mask. Then "use the photoresist mask as a shield, and etch the hard mask layer 212 and the dielectric layer 206 until the above-mentioned stop layer 204 is exposed" to form a contact at the relative position of the conductive region. Hole 2 丨 3. Then, the above-mentioned contact hole 1 3 is filled with i 1 ine photoresist material 2 1 4 by a spin coating method, and then pre-baked at an appropriate temperature to be used as a sacrificial protective layer in a subsequent etching step. In order to prevent the above-mentioned etch stop layer 2 0 4 from being damaged. The dielectric layer 206 is, for example, a silicon dioxide layer or other low dielectric constant material layer formed by a chemical vapor deposition method. The etch stop layer 204 and the hard mask layer 2 1 2 are made of silicon nitride or Nitroxide composition. Due to the low viscosity and other material characteristics of photoresist materials, it is suitable for contact holes with extremely small size (for example, less than 0.3 // m). Next, referring to FIG. 3b, the above i 1 ine photoresist material 2 1 4 is etched back to leave the entire contact hole 2 1 3 as a sacrificial protective layer 214a. The above etch back method is used Operating conditions for pressure 100m rr / power 50 0W / oxygen flow i20sccm / nitrogen flow 41 ° sccm to perform 0. Then, please refer to Figure 3c and apply lithography to apply deep UV photoresist Material, exposure, development, baking and other steps to form a photoresist pattern 2 1 6 for trench etching. Next, referring to FIG. 3d, the photoresist pattern 216 is used as an etch mask '. Then, the hard mask layer 212 and the light are used.

516182 V. Description of the invention (9) The etching selection ratio of the resist material 2 1 4 a is less than one, that is, the etching rate of the hard mask layer 212 is lower than the etching rate of the photo resist material 214 & The hard mask layer 212 and the i-iine photoresist material $ 1 4 a are selectively etched until the i — 1ine photoresist material 2 1 4 a is etched to a predetermined depth. Next, please refer to FIG. 3e, and then use the etching selection ratio of the hard mask layer 212, the dielectric layer 20 6 and the 1-1 ine photoresist material 2 14a greater than one, that is, the photoresist material The etching rate of 214a is greater than the etching rate of the hard mask layer 212 and the dielectric layer 206; the hard mask layer 212, the dielectric layer 206, and the Hne light are selectively etched. The resist material 214a is exposed until the above-mentioned etch stop layer 204 is exposed, and a trench 22 is formed, which forms a dual damascene structure with the contact hole 213. Immediately after referring to Figure 3f, the dry and wet removal method pattern 216, the hard mask layer 212, and the photoresist material are used: after that, the etching stop layer 204 is removed to expose the copper and fill it with copper, etc. The step of forming a metal interconnect with ..., I, invented the use of Bu 11116 photoresist material as a sacrificial protective layer, good trench filling ability, can eliminate the conventional hole problem, indeed; the invention of sacrificial protective layer can be any;. In addition, this material is not limited to use of other organic organic materials. Although the present invention has been disclosed in the preferred embodiment as above, the present invention is again limited. Anyone who is familiar with this art, should not use it within the scope. Some changes can be made to the spirit of the present invention as the attached patent: Π :: protection of the invention page 13 0503.6497TWF; TSMC2001-0155; dennis.ptd

Claims (1)

516182 Suitable for semiconductor substrates with conductive areas 6. Patent application range for manufacturing dual-damascene structure 1. The semiconductor substrate includes the following steps: Dielectrics are formed on the semiconductor substrate as described above. Layer and a hard mask layer; θ forms a contact hole on the surface of the above-mentioned etching stop layer of the hard mask layer and corresponding conductive area; said F-way fills the entire sacrificial protection layer in the contact hole; The electrical layer and the etching selection ratio of the hard mask layer and the sacrificial protection layer are greater than one, and the hard mask layer, the dielectric layer, and the sacrificial protection layer are selectively etched until the dielectric layer is etched to a predetermined depth. In order to form a trench, the sacrificial protection layer in the contact hole is removed to form a dual damascene structure. s Select a ratio of the sacrificial protection layer to the hard mask layer to selectively etch the hard mask layer and the sacrificial protection layer until the sacrificial protection layer is etched to a predetermined depth; and The method of manufacturing a dual damascene structure according to item 1 in the scope, wherein the step of forming the contact hole includes: coating a layer of photoresist on the hard mask layer; and passing a photomask to the position where the contact hole is to be formed. The photoresist layer is exposed and developed to form a photoresist mask. Using the photoresist mask as a shield, the hard mask layer and the dielectric layer are etched until the etching stop layer is exposed to conduct the conductive film. A contact hole is formed at a relative position of the area; and the photoresist mask is removed. 0503-6497TWF; TSMC2001-0155; denn i s.p t d 6. The manufacturing steps of the dual mosaic structure described in Item Λ of the Patent Application Scope Method: ,, * The contact hole is filled with a sacrificial protective layer 'including the following • To: surface coating the sacrificial protective layer on the above hard mask layer And the contact hole is etched back to the sacrifice companion material. The edge-protection layer is sacrificed to form the photo-filling method for filling the contact hole. The double-mosaic junction described in item j of the patent application scope, wherein the above-mentioned stop layer is composed of oxynitride. Mind making method 5 Gan t t: t patent? The fabrication of the dual damascene structure described in item 1 above is made of silicon nitride. Law 6. The scope of patent application as claimed! The pair of items described above, wherein the above-mentioned dielectric layer is composed of a dioxide. ㈣1 operation method m 制作 Fabrication of the dual mosaic structure described in item 1 of the patent scope * Where the above-mentioned sacrificial protective layer is removed, the # square mask layer. Only 3 ^ cloud in addition to the above-mentioned 8. The dual-mosaic method described in item i of the scope of the patent application, wherein the sacrificial protective layer is a producer of i_line photoresist material 9. A method of manufacturing a dual-mosaic structure, The semiconductor substrate is suitable for a semiconductor substrate, and includes the following steps: a gate-protection region sequentially forms a first etch stop layer, a dielectric layer, a second etch stop layer, a second dielectric layer, and a hard layer on the semiconductor substrate; 'The masker forms a contact hole in the surface of the hard mask layer, the second dielectric layer, the first-etched /, the patent-application etch stop layer, and the first etch stop layer until the corresponding conductive area is exposed. The contact hole in the fifth t is filled with a sacrificial protection layer; a masking layer smaller than one ^ the masking layer and the above-mentioned sacrificial protection layer are selected by the ratio of the ratio 'up to i sacrificial = the hard mask layer and the sacrificial protection described above. A predetermined depth is engraved; and the protective layer etching selection ratio # 二 = s and the above-mentioned hard mask layer and the sacrificial mask layer, the formula "" is used to selectively engraving the above-mentioned hard mask etching stop; I, to 幵: point one sacrifice Protective layer until exposed above Secondly, a double damascene junction is formed; i. "" Slots "to remove the sacrificial protective layer in the contact hole 3. The double damascene & structure method as described in item 9 of the patent application scope, wherein the step of forming the above contact hole The fabricator including the "structure" coats a layer of photoresist on the hard mask layer; through a photomask, the light to be formed in the contact hole is developed and developed to form a photoresist mask; and the pre-resistance layer is exposed and used. The photoresist mask is used to shield the above-mentioned second dielectric layer, the above-mentioned second etch: Hai] the hard-shielding layer, and the first stop layer is exposed, so as to describe: the dielectric layer until a contact hole is formed And remove the photoresist mask at the relative position. Π. Double inlay as described in item 9 of the scope of patent application: in which the entire sacrificial protection layer is filled in the entire contact hole: 0503-6497TWF; TSMC2001-0155 dennis.ptd Sixteenth stomach Six, the scope of the patent application is comprehensive application of the sacrificial protective layer: and the above sacrificial protective layer is etched back on the hard mask layer and in the contact hole to block the material. x forms the light that fills the contact hole. 1 2 · If the patent application scope item g Method 'where the above-mentioned first and second etching second J, the structure of the production side 13. The composition of the scope of the application for the patent No. 9 is composed of fossils. Method, where the above first and first_ Fang Yi. If the patent application / the first stop layer is composed of nitride stone. Method, where the dual dielectric structure described in the first dielectric / and 1 above is made. Die layer and second dielectric layer It is a silicon dioxide construction method, 1i. The manufacturer of the dual mosaic structure as described in Maishen / Patent Scope Item 9; when the sacrificial protective layer is removed in the cover: the removal is performed at the same time as in the patent application scope No. 9, In the dual-damascene method, the sacrificial protection layer is a iine photoresist material. i Zuofang 17. · The production of a dual-mosaic structure, Tai Fen Tian Mu, Zeng; semiconductor semiconductor I of the field, including the following steps. 'Applicable to the formation of a contact hole with a conductive region layer in the hard-etched stop layer. And a first stop layer surface among the first dielectric layers; a first etch stop layer, an η "a, a first etch stop layer, a second dielectric layer, and A hard mask layer, a second dielectric layer, and a second etch until 0503-6497TWF; TSMC2001-0i55; dennis.ptd $ 17 page 516182 corresponding to the conductive area exposed Using the above-mentioned method, the # —dielectric layer, the hard mask layer, and the first F material etching selection ratio are greater than one, # s exposes Cheng Chengshang " 苐 一; | Electric layer and the above light Resistive materials, straight away! ·, 4 An etch stop layer to form a trench and remove the contact? [j 1 lne photoresist material to form a dual damascene structure. The female stated that the method of double inlaying described in item 17 of the patent scope, wherein the step of forming the contact hole includes inlaying, .... A photoresist is coated on the hard mask layer; a light mask is used to develop light at the position where a contact hole is to be formed to develop a photoresist mask; ... the resist layer is first exposed to the above-mentioned curtain. As a shield, the above-mentioned hard mask layer is used, and π is a dielectric layer until the exposure-contact hole is exposed; and 乂 u is formed at a position opposite to the upper conductive region to remove the photoresist mask. The manufacturing of the dual mosaic structure described in item 17 of the patent scope includes the following steps: 丨 What material, including comprehensive coating of i -1 i ne photoresist material on the above-mentioned hard M6182 VI. In the scope of patent application hole; and the photoresist material of i —! I I engraved above. Line ^ resist material 枓 to fill the above contact hole Method 2Qm Special ㈣ ㈣ ㈣ ㈣ 17 expected double-damascene structure, the above-mentioned first etch stop layer and gas as silicon or silicon oxynitride layer. The j 丨 τ stop layer is made of the double-insertion structure of the lobsterized square cattle 21 pot as described in item 17 of the scope of patent application2. The lambda / radio layer and the second dielectric layer are dioxin methods, where The above-mentioned hard mask is made by the ^ 17 / mentioned double inlay # structure; iine photoresist material is removed at the same time. 23. A method of making a double inlay structure is suitable for a semiconductor substrate with a semiconductor substrate, and The manufacturing method of the structure includes the following steps: sequentially forming a first etch stopper, an electric layer, a second etch stopper layer, a second dielectric layer, and a hard mask layer on the semiconductor substrate, and forming the hard mask layer on the semiconductor substrate; A layer of photoresist is applied on top; the photoresist layer is exposed at the position where the contact hole is to be formed to form a photoresist mask; ~ the above photoresist mask is used as a shield to etch the hard mask layer The second dielectric layer, the second etch stop layer, and the first dielectric layer are formed until a first contact stop layer is exposed, so as to form a contact hole at the relative position of the conductive region; / 0503-6497TWF; TSMC2001-0155 ; denn i sp td p.19 516182 2. The scope of the application for the patent removes the above photoresist mask curtain and uses the light on the hard mask layer in the entire contact hole; and the ratio is small: one way, selective feeding: the material is selected until the above photoresist material is used. The second dielectric layer and the "deep" depth; i-Hne photoresist material selection ratio greater than-= layer and the above-mentioned hard mask layer, the second dielectric 'type' selective etching on the second dielectric. 9 Hongdian said the above 1 — 1 1 ne photoresistive material + etching stop layer to form-trench; Weigh into double mosaic knots 0503-6497TWF; TSMC2001-0155; dennis.ptd page 20