JP2007088018A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can prevent the deterioration of the detrap retention characteristic of a nonvolatile memory element, and also to provide its manufacturing method. <P>SOLUTION: On an insulation film 14 wherein plugs 16 are formed, an interlayer insulation film 17 consisting of a silicon-rich oxide film and an interlayer insulation film 18 consisting of TEOS film are formed. Then, a trench 19 is so formed as to penetrate the interlayer insulation films 17 and 18, and an interconnection 20a is so formed as to be embedded in the trench 19. In other words, a first interconnection layer is a buried interconnection embedded in the interlayer insulation films 17 and 18. Moreover, the interlayer insulation film 17 formed in the same layer as the interconnections 20a-20c which constitute the first interconnection layer is a silicon-rich oxide film having a property of trapping dopants such as water and hydrogen. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a nonvolatile memory that needs to improve detrap retention characteristics and a technique effective when applied to the manufacturing thereof.

Japanese Patent Laying-Open No. 2005-26659 (Patent Document 1) describes the following technique. That is, a barrier film, an interlayer insulating film, and a metal hard mask film are sequentially formed on a semiconductor substrate provided with a bit line contact plug. Then, the metal hard mask film is patterned to form a metal hard mask film pattern that opens the bit line region corresponding to the bit line contact plug. Thereafter, the interlayer insulating film and the barrier film are etched by an etching process using the metal hard mask film pattern as an etching mask to form a bit line trench. Subsequently, after forming a bit line metal film so as to fill the bit line trench, a planarization process is performed to remove the bit line metal film and the metal hard mask film pattern on the interlayer insulating film. In this way, a bit line made of a bit line metal film, and a barrier film and an interlayer insulating film filling the bit line can be formed. Here, the barrier film has a role as an etching stopper when the bit line trench is formed in the interlayer insulating film.
Japanese Patent Laying-Open No. 2005-26659

  As a semiconductor memory device, there is a nonvolatile memory that keeps stored contents even when the power is turned off. Examples of the nonvolatile memory include EP (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), and flash memory. In the nonvolatile memory, for example, a nonvolatile memory element is formed on a semiconductor substrate, and multilayer wiring is formed on the nonvolatile memory element. As an example of the wiring over multiple layers, there is one in which the first wiring layer is formed of a tungsten film, and the second wiring layer and the third wiring layer are formed of an aluminum film.

  In the multilayer wiring structure, an interlayer insulating film is formed between wiring layers. However, when a wiring layer is formed on the interlayer insulating film, for example, a step is generated by the thickness of the wiring layer. Therefore, for example, a silicon oxide film (HDP-CVD) formed by a high-density plasma CVD method having excellent embedding characteristics is first used so as not to bury a step formed by the thickness of the first wiring layer on the first wiring layer. A film). Then, a silicon oxide film (referred to as TEOS film) using TEOS with good flatness as a raw material is formed on the HDP-CVD film. That is, the interlayer insulating film formed between the wiring layers has a two-layer structure of the HDP-CVD film and the TEOS film. This two-layer structure includes not only the interlayer insulating film between the first wiring layer and the second wiring layer, but also the interlayer insulating film between the second wiring layer and the third wiring layer and the interlayer on the third wiring layer. It is also used for insulating films.

However, the HDP-CVD film contains a large number of impurities such as water (H ₂ O) and hydrogen (H ₂ ), and the gate of the nonvolatile memory element is subjected to heat treatment or the like in which these impurities are applied to the semiconductor substrate. Penetration into the insulating film. Then, there is a problem in that the gate insulating film is damaged and the threshold voltage of the nonvolatile memory element fluctuates. That is, the detrapping / retention characteristics of the nonvolatile memory element deteriorate due to impurities present in the HDP-CVD film. Here, the deterioration of the detrapping retention characteristic means that the threshold value of the nonvolatile memory element changes. In particular, in a non-volatile memory, since the allowable range of threshold fluctuation is narrow, threshold fluctuation caused by impurities in the HDP-CVD film tends to cause malfunction.

  Therefore, in order to prevent the deterioration of the detrapping / retention characteristics of the nonvolatile memory element, a film for trapping impurities such as water and hydrogen is inserted between the nonvolatile memory element and the HDP-CVD film. Yes. That is, a silicon-rich oxide film (SiO, SiON, SiOC, etc.) having the property of trapping impurities such as water and hydrogen is inserted between the nonvolatile memory element and the HDP-CVD film, and the impurities are removed from the nonvolatile memory element. The gate insulating film is prevented from entering. Here, the silicon-rich oxide film refers to a film having a lower ratio of oxygen atoms to silicon atoms than a silicon oxide film having a ratio of oxygen atoms to silicon atoms of 1.9 to 2.0. Examples include a silicon oxide film, a silicon oxynitride (SiON) film, a carbon-containing silicon oxide (SiOC) film, and the like in which the ratio of oxygen atoms to is less than 1.9.

  As a method for inserting a silicon-rich oxide film between the nonvolatile memory element and the HDP-CVD film, first, it is conceivable to form a silicon-rich oxide film immediately after forming the first wiring layer. That is, it can be considered that a silicon-rich oxide film is formed between the first wiring layer and the HDP-CVD oxide film. However, since the distance between the wirings which are the first wiring layers is becoming narrower due to the miniaturization, the embedding margin between the wirings forming the first wiring layer is insufficient. That is, the space formed between the wirings is filled with the HDP-CVD film, but if a silicon-rich oxide film is formed on the wirings before the HDP-CVD film is formed, the space formed between the wirings is reduced. The aspect ratio becomes large, and there is a problem that even the HDP-CVD film cannot be embedded sufficiently. If the space formed between the wirings cannot be sufficiently filled, so-called “su” is generated in the interlayer insulating film. When “su” is generated in the interlayer insulating film, the metal film formed on the interlayer insulating film remains inside the “su”, causing a short circuit defect between the wirings. Therefore, when a silicon-rich oxide film is formed after the first wiring layer is formed, it is not possible to form a silicon-rich oxide film having a thickness sufficient to prevent deterioration of the detrapping / retention characteristics. There is a problem that it becomes difficult.

  Second, it is conceivable to form a silicon-rich oxide film directly under the first wiring layer. In this case, a silicon-rich oxide film is formed on the uppermost layer of the interlayer insulating film formed below the first wiring layer. However, a contact hole is formed in the interlayer insulating film formed immediately below the first wiring layer. Further, a first wiring layer is formed on the interlayer insulating film using an etching technique. Therefore, since the silicon-rich oxide film is scraped when the contact hole is formed and the first wiring layer is formed, it is necessary to make the silicon-rich oxide film thick in consideration of the amount of scraping of the silicon-rich oxide film. However, if a silicon-rich oxide film is formed thickly, it is difficult to etch the silicon-rich oxide film when forming a contact hole. Therefore, there is a possibility that the resist film serving as a mask is lost before the contact hole is completely formed. is there. Then, the problem which causes the shape defect of a contact hole generate | occur | produces. That is, when the silicon-rich oxide film is formed thick, the contact hole formation margin is insufficient.

  An object of the present invention is to provide a technique capable of preventing the deterioration of the detrapping / retention characteristics of a nonvolatile memory element without causing the above-described problems.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to the present invention is a semiconductor device having a semiconductor element and a plurality of wiring layers, wherein (a) a first interlayer insulating film and (b) a second interlayer insulating formed on the first interlayer insulating film. A film, (c) a groove penetrating the first interlayer insulating film and the second interlayer insulating film, and (d) a wiring embedded in the groove. The first interlayer insulating film is a film having a larger ratio of silicon atoms to oxygen atoms than a film containing oxygen atoms and silicon atoms constituting the second interlayer insulating film. is there.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having a semiconductor element and a plurality of wiring layers, comprising: (a) a step of forming a first interlayer insulating film; and (b) the first method. Forming a second interlayer insulating film on the interlayer insulating film; and (c) forming a groove penetrating the first interlayer insulating film and the second interlayer insulating film. And (d) a step of forming a conductor film on the second interlayer insulating film including the inside of the groove; and (e) removing the conductor film formed other than the groove so as to be embedded in the groove. And forming a wiring made of the conductor film. The first interlayer insulating film is a film having a larger ratio of silicon atoms to oxygen atoms than a film containing oxygen atoms and silicon atoms constituting the second interlayer insulating film. is there.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  A buried wiring is formed in the interlayer insulating film, and a part of the interlayer insulating film on which the buried wiring is formed is formed of a silicon-rich oxide film, so that the detrapping and retention characteristics of the nonvolatile memory element can be prevented from deteriorating without side effects. Can do.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  Embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment. In the semiconductor device according to the first embodiment, a nonvolatile memory element and a multilayer wiring are formed. In FIG. 1, an element isolation region 2 having, for example, an STI (Shallow Trench Isolation) structure is formed on the main surface of a semiconductor substrate 1 made of silicon single crystal, and a region separated by the element isolation region 2 is a memory. A cell formation region and a peripheral circuit formation region are formed. A p-type well 3 is formed in the memory cell formation region of the semiconductor substrate 1, and a p-type well 4 is formed in the peripheral circuit formation region formed outside the memory cell formation region.

  A nonvolatile memory element is formed on the p-type well 3 in the memory cell formation region. The nonvolatile memory element has a gate insulating film 5 on the p-type well 3, and has a floating gate electrode 6 that accumulates charges on the gate insulating film 5. The gate insulating film 5 is made of, for example, a silicon oxide film, and the floating gate electrode 6 is made of a polysilicon film. An ONO film 7 in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are stacked is formed on the floating gate electrode 6, and a control gate electrode 8 is formed on the ONO film 7. The control gate electrode 8 is made of, for example, a polysilicon film.

  An n-type semiconductor region 10 is formed in the p-type well 3 aligned with the control gate electrode 8. The n-type semiconductor region 10 becomes a source region or a drain region of the nonvolatile memory element. A plug 15 is formed on the n-type semiconductor region 10 serving as a source region, and is connected to a source line (not shown) via the plug 15. Further, a plug 16 is formed on the n-type semiconductor region 10 serving as the drain region, and is connected to the wiring 20a serving as the bit line via the plug 16.

  As described above, the nonvolatile memory element has a pair of n-type semiconductor regions 10 mainly serving as a source region and a drain region, and a channel formation region (p-type well 3) formed therebetween. The gate insulating film 5, the floating gate electrode 6, the ONO film 7, and the control gate electrode 8 are sequentially stacked on the channel formation region.

  Here, a write operation, a read operation, and an erase operation of the nonvolatile memory element will be briefly described. First, the write operation will be described. In order to write data to the nonvolatile memory element, a voltage of, for example, 9V is applied to the control gate electrode 8 of the nonvolatile memory element, and a voltage of, for example, 4V is applied to the drain region of the nonvolatile memory element. Then, a voltage of, for example, 3V is applied to the p-type well 3, and the source region of the nonvolatile memory element is maintained at, for example, 0V (ground potential). As a result, hot electrons are generated in a channel formed between the source region and the drain region. Since this hot electron has high energy, it is tunneled through the gate insulating film 5 formed on the channel and injected into the floating gate electrode 6. As a result, writing to the nonvolatile memory element is performed.

  Next, the reading operation will be described. In order to read data from the nonvolatile memory element, a voltage of, for example, 2.7 V is applied to the control gate electrode 8 of the nonvolatile memory element, and a voltage of, for example, 0.8 V is applied to the drain region of the nonvolatile memory element. . Then, the p-type well 3 and the source region of the nonvolatile memory element are maintained at 0V, for example. At this time, data (“1” or “0”) stored in the nonvolatile memory element is read depending on whether or not a current flows between the source region and the drain region of the nonvolatile memory element. When electrons are not injected into the floating gate electrode 6 of the non-volatile memory element, the threshold voltage of the non-volatile memory element becomes small, so that a current flows in the channel region between the source region and the drain region. For this reason, for example, since current flows, it is understood that data “0” is stored in the nonvolatile memory element. On the other hand, when electrons are injected into the floating gate electrode 6, the threshold voltage of the nonvolatile memory element increases, so that no current flows in the channel region. For this reason, for example, it can be seen that “1” data is stored in the nonvolatile memory element because no current flows. Thus, in the nonvolatile memory element, data is stored by utilizing the fact that the threshold voltage changes depending on whether or not electrons are injected into the floating gate electrode 6. Here, when impurities such as water and hydrogen enter the gate insulating film 5 of the nonvolatile memory element, a phenomenon occurs in which the threshold voltage of the nonvolatile memory element fluctuates. Then, there is a possibility that the threshold voltage increases due to the influence of impurities and current does not flow even though electrons are not injected into the floating gate electrode 6. Then, even though “0” is originally stored in the nonvolatile memory element, the threshold value rises and no current flows, so that “1” is stored in the nonvolatile memory element. There is a risk of malfunction. The phenomenon that the threshold voltage of the nonvolatile memory element fluctuates due to the influence of impurities such as water and hydrogen is expressed as degradation of the detrap retention characteristics. It can be seen that in the nonvolatile memory element, it is necessary to prevent the detrapping / retention characteristics from deteriorating, in particular, in order to prevent malfunction and improve reliability.

  Next, the erase operation will be described. In order to erase the data written in the nonvolatile memory element, a voltage of 10.5 V, for example, is applied to the control gate electrode 8 of the nonvolatile memory element, and the drain region of the p-type well 3 and the nonvolatile memory element is For example, a voltage of 10.5V is applied. Then, the source region of the nonvolatile memory element is maintained in a floating state (open state, open state). Then, due to a tunnel phenomenon, the electric charge injected into the floating gate electrode 6 moves to the channel region through the gate insulating film 5, and electrons are emitted. As a result, electrons injected into the floating gate electrode 6 are released, and the data “1” stored in the nonvolatile memory element can be erased.

  Next, a dummy electrode 9 formed in the same layer as the control gate electrode 8 is formed on the outer periphery of the memory cell formation region. The dummy electrode 9 is formed in order to reduce the influence of foreign matters generated when the nonvolatile memory element is formed, and to reduce the level difference between the memory cell formation region and the peripheral circuit formation region.

  An ONO film 7, a floating gate electrode 6, and a gate insulating film 5 are formed under the dummy electrode 9 as in the nonvolatile memory element, but do not function as a nonvolatile memory element.

  On the other hand, a p-type well 4 is formed in the peripheral circuit formation region, and a memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on the p-type well 4. The memory cell selection MISFET has a function of selecting a nonvolatile memory element to be operated from a plurality of nonvolatile memory elements formed in the memory cell formation region. The memory cell selecting MISFET has a gate insulating film 11 on the p-type well 4 and a gate electrode 12 formed in the same layer as the control gate electrode 8 on the gate insulating film 11. The gate insulating film 11 is made of, for example, a silicon oxide film, and the gate electrode 12 is made of, for example, a polysilicon film. In addition, an n-type semiconductor region 13 serving as a source region or a drain region is formed in the p-type well 4 in alignment with the gate electrode 12. Then, the plug 16 is electrically connected to the n-type semiconductor region 13 which becomes the source region or the drain region, and the plug 16 is electrically connected to the wirings 20b and 20c, respectively.

  Next, the structure of the wiring layer will be described. As shown in FIG. 1, an insulating film 14 made of, for example, a silicon oxide film is formed on the nonvolatile memory element and the memory cell selection MISFET, and a plug 15 and a plug 16 are formed on the insulating film 14. Yes. In the insulating film 14 on which the plug 16 is formed, wirings 20a to 20c that form the first wiring layer are formed. The wirings 20a to 20c are embedded wirings. That is, an interlayer insulating film (first interlayer insulating film) 17 and an interlayer insulating film (second interlayer insulating film) 18 are formed on the insulating film 14, and the interlayer insulating film 17 and the interlayer insulating film 18 include A groove 19 is formed therethrough. And wiring 20a-20c is formed so that this groove | channel 19 may be embedded.

  Here, the interlayer insulating film 17 is formed of a silicon-rich oxide film. A silicon-rich oxide film is a film having a lower ratio of oxygen atoms to silicon atoms than a silicon oxide film having a ratio of oxygen atoms to silicon atoms of 1.9 to 2.0. A silicon oxide film, a silicon oxynitride (SiON) film, a carbon-containing silicon oxide (SiOC) film, or the like having a ratio of less than 1.9. In other words, a silicon-rich oxide film is a film having a larger ratio of silicon atoms to oxygen atoms than a silicon oxide film having a ratio of oxygen atoms to silicon atoms of 1.9 to 2.0. it can.

  In this way, the interlayer insulating film 17 composed of a silicon-rich oxide film is formed under the interlayer insulating film 17 with impurities such as water and hydrogen contained in the HDP-CVD film 24 and the HDP-CVD film 27 described later. The gate insulating film 5 of the non-volatile memory element and the gate insulating film 11 of the memory cell selecting MISFET are not allowed to enter. That is, since the silicon-rich oxide film has a property of trapping (trapping) impurities such as water and hydrogen that damage the gate insulating films 5 and 11, impurities generated in the HDP-CVD films 24 and 27 are removed. It can be removed before reaching the gate insulating films 5 and 11. Therefore, it is possible to prevent the detrapping / retention characteristics of the nonvolatile memory element from being deteriorated. More specifically, impurities such as water and hydrogen can be prevented from entering the gate insulating films 5 and 11 and causing fluctuations in threshold voltage.

  An interlayer insulating film 18 is formed on the interlayer insulating film 17 formed of a silicon-rich oxide film. The interlayer insulating film 18 is formed from a TEOS film. The TEOS film is a normal silicon oxide film, and is a silicon oxide film in which the ratio of oxygen atoms to silicon atoms is 1.9 to 2.0. The TEOS film is a film having good surface flatness. From this, it can be seen that the interlayer insulating film 17 is composed of a film having a larger ratio of silicon atoms to oxygen atoms than the interlayer insulating film 18.

  One feature of the first embodiment is that the wirings 20 a to 20 c are formed so as to be embedded in the interlayer insulating film 17 and the interlayer insulating film 18 instead of forming the wirings 20 a to 20 c on the interlayer insulating film 18. is there. That is, one characteristic is that the wirings 20a to 20c formed on the insulating film 14 do not have a normal wiring structure, but are embedded wirings in which the interlayer insulating film 17 and the interlayer insulating film 18 are embedded. Thus, by using the wirings 20a to 20c constituting the first wiring layer as buried wirings, it is possible to solve the problem described in the problem while preventing the deterioration of the detrapping / retention characteristics due to the interlayer insulating film 17. is there.

  That is, as described in the problem, when the embedded wiring is not used, a wiring that is not the embedded wiring is formed on the insulating film 14 as one method. Then, after a silicon-rich oxide film is formed on the wiring, an HDP-CVD film is formed in order to fill a step due to the wiring. At this time, since the silicon-rich oxide film is formed between the wiring and the HDP-CVD film, it is possible to prevent the detrapping / retention characteristics of the nonvolatile memory element from deteriorating. However, by forming a silicon-rich oxide film, the aspect ratio in the space between the wirings constituting the first wiring layer is increased, and there is a problem that even the HDP-CVD film cannot be embedded sufficiently. On the other hand, in the first embodiment, the wirings 20a to 20c can be formed in the same layer as the interlayer insulating film 17 that is a silicon-rich oxide film by using the embedded wiring. Therefore, since the silicon-rich oxide film is formed, there is no problem of an increase in the aspect ratio in the space between the wirings constituting the first wiring layer. Furthermore, since the wirings 20a to 20c are formed so as to be embedded in the interlayer insulating film 17 and the interlayer insulating film 18, the surface of the interlayer insulating film 18 is flat. For this reason, it is not necessary to form an HDP-CVD film on the wirings 20a to 20c, and it is possible to obtain an effect that it is not necessary to provide an impurity source directly on the first wiring layer.

  As another method described in the problem, it is conceivable to form a silicon-rich oxide film immediately below the first wiring layer. However, this method has a problem of causing a defective shape of the contact hole formed immediately below the first wiring layer as described in the problem. This is because the silicon-rich oxide film formed immediately below the first wiring layer is scraped due to the formation of contact holes and the like, and is formed thick with an expectation of the scraping amount. However, according to the first embodiment, after the plug 16 is formed in the insulating film 14, the interlayer insulating film 17, which is a silicon-rich oxide film, is formed on the insulating film 14. Accordingly, the shape of the plug 16 formed in the insulating film 14 by the interlayer insulating film 17 is not caused. Further, an interlayer insulating film 18 made of a TEOS film is formed on the interlayer insulating film 17. For this reason, even when the trench 19 is formed in the interlayer insulating film 17 and the interlayer insulating film 18 by etching, the interlayer insulating film 17 made of a silicon-rich oxide film is always protected by the interlayer insulating film 18, so that chipping is expected. It is not necessary to form it thickly. In other words, according to the first embodiment, a silicon-rich oxide film may be formed with a minimum film thickness necessary to prevent deterioration of detrapping and retention characteristics. The minimum film thickness necessary for preventing the deterioration of the detrap retention characteristics is, for example, 100 nm or more and 300 nm or less. In order to prevent deterioration of the detrapping / retention characteristics, for example, in the case of a silicon-rich silicon oxide film, it is desirable to use a film having a ratio of oxygen atoms to silicon atoms of 1.5 or more and less than 1.9.

  As described above, in the first embodiment, the wirings 20a to 20c constituting the first wiring layer are formed so as to be embedded in the interlayer insulating film 17 and the interlayer insulating film 18 made of a silicon-rich oxide film. Deterioration of detrapping and retention characteristics of the nonvolatile memory element can be prevented without causing the problem described in the problem.

  The plug 15 and the plug 16 formed in the insulating film 14 are formed from a laminated film of a barrier metal film made of, for example, a titanium / titanium nitride film and a tungsten film. Similarly, the wirings 20a to 20c constituting the first wiring layer are also composed of a laminated film of a titanium / titanium nitride film and a tungsten film.

  Next, an interlayer insulating film 21 made of, for example, a TEOS film is formed on the interlayer insulating film 18 in which the wirings 20a to 20c are buried, and a plug 22 is formed in the interlayer insulating film 21. A wiring 23 serving as a second wiring layer is formed on the interlayer insulating film 21 on which the plug 22 is formed. Unlike the wirings 20a to 20c constituting the first wiring layer, the wiring 23 is formed with a structure that is not a buried wiring. Therefore, a step is generated on the interlayer insulating film 21 between the region where the wiring 23 is formed and the region where the wiring 23 is not formed. The wiring 23 is formed of, for example, a laminated film of a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film.

An HDP-CVD film 24 is formed on the interlayer insulating film 21 including the wiring 23 in order to bury the step due to the wiring 23. The HDP-CVD film 24 is a silicon oxide film formed by a high-density plasma CVD method having excellent embedding characteristics. The high density plasma CVD method is a plasma CVD method in which an ion density of a raw material is 10 ¹² to 10 ¹³ / cm ³ . Since the HDP-CVD film 24 formed by this high-density plasma CVD method is a film having excellent embedding characteristics for embedding a step, the step due to the wiring 23, that is, the space between the wirings 23 can be embedded well. On the other hand, since the HDP-CVD film contains a large amount of impurities such as water and hydrogen, the gate insulation in which impurities existing in the HDP-CVD film 24 are formed in the lower layer unless any countermeasure is taken. There is a problem that the film penetrates into the film 5 or the like and causes fluctuations in threshold voltage. However, in the first embodiment, a silicon-rich oxide film that captures impurities is formed in the first wiring layer between the HDP-CVD film 24 and the gate insulating film 5 of the nonvolatile memory element. Intrusion of impurities into the insulating film 5 can be prevented, and variation in threshold voltage due to impurities can be suppressed.

  An interlayer insulating film 25 made of, for example, a TEOS film having excellent flatness is formed on the HDP-CVD film 24, and a wiring 26 constituting a third wiring layer is formed on the interlayer insulating film 25. . Unlike the wirings 20a to 20c constituting the first wiring layer, the wiring 26 is formed with a structure that is not a buried wiring. That is, the wiring 26 has the same configuration as that of the wiring 23, and is formed of, for example, a laminated film of a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film.

  An HDP-CVD film 27 is formed on the interlayer insulating film 25 including the wiring 26 in order to bury a step due to the wiring 26, and an interlayer insulating film made of, for example, a TEOS film is formed on the HDP-CVD film 27. 28 is formed. In addition, since the structure of the layer beyond this layer is the same, it abbreviate | omits.

  Next, another effect of the semiconductor device according to the first embodiment will be described. FIG. 2 is a cross-sectional view showing a region corresponding to a part of FIG. In FIG. 2, an interlayer insulating film 17 made of a silicon-rich oxide film is formed on the insulating film 14, and an interlayer insulating film 18 made of a TEOS film is formed on the interlayer insulating film 17. A groove 19 is formed in the interlayer insulating film 17 and the interlayer insulating film 18, and wirings 20 a to 20 c are formed so as to be embedded in the groove 19.

  An interlayer insulating film 21 is formed on the interlayer insulating film 18 in which the wirings 20 a to 20 c are embedded, and a plug 22 is formed in the interlayer insulating film 21. Here, the plug 22 is originally formed so as to be included on the wiring 20a, but FIG. 2 shows a state in which a part of the plug 22 protrudes from the wiring 20a due to a positional shift. When the hole serving as the plug 22 is displaced from the wiring 20a in this way, the hole reaches the lower semiconductor substrate. As a result, the plug 22 causes a problem that the semiconductor substrate and the wiring are short-circuited.

  However, in the first embodiment, an interlayer insulating film 17 made of a silicon-rich oxide film is formed on the insulating film 14. Since the interlayer insulating film 21 and the interlayer insulating film 18 are formed of the same type of TEOS film, not only the interlayer insulating film 21 but also the interlayer insulating film 18 are etched when a positional shift occurs. However, the interlayer insulating film 17 formed below the interlayer insulating film 18 is formed of a silicon-rich oxide film. Since the TEOS film and the silicon-rich oxide film have different silicon contents, the degree of etching is different. That is, the interlayer insulating film 17 made of a silicon-rich oxide film serves as an etching stopper for the interlayer insulating film 18 made of a TEOS film. For this reason, even if the hole for forming the plug 22 is displaced, the etching stops at the interlayer insulating film 17. Therefore, the plug 22 does not connect the semiconductor substrate and the wiring, and a short circuit failure between the semiconductor substrate and the wiring can be prevented.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings. In the drawings shown below, the structure of the nonvolatile memory element shown in FIG. 1 is omitted, and the structure on the insulating film 14 will be described. That is, a process for manufacturing a wiring layer, which is a characteristic part of the present invention, will be described.

  First, as shown in FIG. 3, the plug 16 is formed in the insulating film 14. In order to form the plug 16 in the insulating film 14, after forming the insulating film 14, a contact hole is formed in the insulating film 14 using a photolithography technique and an etching technique. Then, a titanium / titanium nitride film and a tungsten film are formed on the insulating film 14 including the inside of the formed contact hole. Subsequently, the unnecessary titanium / titanium nitride film and tungsten film formed on the surface of the insulating film 14 are removed by using, for example, CMP (Chemical Mechanical Polishing). Thereby, the plug 16 in which the titanium / titanium nitride film and the tungsten film are embedded in the contact hole can be formed.

Next, as shown in FIG. 4, an interlayer insulating film 17 made of a silicon-rich oxide film is formed on the insulating film 14 on which the plug 16 is formed. The silicon-rich oxide film can be formed using a plasma CVD method. As the plasma CVD method used here, a plasma CVD method having an ion density lower than that of the high density plasma CVD method having an ion density of 10 ¹² to 10 ¹³ / cm ³ is used. According to this plasma CVD method, a film that does not contain impurities such as water and hydrogen can be formed as in the high-density plasma CVD method. As film forming conditions of the plasma CVD method used in this step, silane gas (SiH ₄ ), N ₂ O, or the like is used as a raw material, and the pressure is several Torr (133.32 Pa). This is a condition when the silicon-rich oxide film is a silicon-rich silicon oxide film. As the silicon-rich oxide film, it is desirable to form a film thickness of about 100 nm to 300 nm, which is a film thickness necessary for preventing the deterioration of the detrap / retention characteristics, but a film thickness larger than this may be formed.

Subsequently, an interlayer insulating film 18 made of a TEOS film is formed on the interlayer insulating film 17. As the TEOS film, a plasma CVD method having an ion density lower than that of the high-density plasma CVD method is used as in the case of forming a silicon-rich oxide film. Therefore, a TEOS film free from impurities such as water and hydrogen can be formed. As the film formation conditions of the plasma CVD method used in this step, TEOS (Tetra Ethyl Ortho Silicate), O ₂ , He, or the like is used as a raw material, and the pressure is several Torr (133.32 Pa).

  Next, as illustrated in FIG. 5, a trench 19 penetrating the interlayer insulating film 17 and the interlayer insulating film 18 is formed by using a photolithography technique and an etching technique. The surface of the plug 16 is exposed at the bottom of the groove 19. At this time, by utilizing the difference in silicon content between the TEOS film constituting the interlayer insulating film 18 and the silicon-rich oxide film constituting the interlayer insulating film 17, the silicon-rich oxide film etches the TEOS film. It can function as an etching stopper. For this reason, there is an advantage that the depth control of the groove 19 becomes easy.

  Subsequently, as shown in FIG. 6, a titanium / titanium nitride film 19 a is formed on the interlayer insulating film 18 including the inside of the trench 19. The titanium / titanium nitride film 19a has a function as a barrier metal film, and can be formed using, for example, a sputtering method. Thereafter, a tungsten film 19 b is formed so as to fill the trench 19. The tungsten film 19b can be formed using, for example, a CVD method.

  Next, as shown in FIG. 7, the unnecessary titanium / titanium nitride film 19a and the tungsten film 19b on the interlayer insulating film 18 are removed by, for example, a CMP method to form wirings 20a to 20c constituting the first wiring layer. Can be formed. That is, an embedded wiring in which the titanium / titanium nitride film 19a and the tungsten film 19b are embedded in the groove 19 can be formed.

  Subsequently, as shown in FIG. 8, an interlayer insulating film 21 made of, for example, a TEOS film is formed on the interlayer insulating film 18 including the wirings 20 a to 20 c embedded in the interlayer insulating film 17 and the interlayer insulating film 18. In the first embodiment, since the wirings 20a to 20c constituting the first wiring layer are embedded wirings, the surface thereof is flattened. Therefore, it is not necessary to form an HDP-CVD film on the interlayer insulating film 18 that causes deterioration of the detrap retention characteristics. That is, the interlayer insulating film 21 made of the TEOS film can be formed directly on the interlayer insulating film 18 without forming the HDP-CVD film. In the first embodiment, since the silicon-rich oxide film having the property of capturing water, hydrogen, etc. contained in the HDP-CVD film is formed, it is possible to prevent the detrapping / retention characteristics from deteriorating. Further, since it is not necessary to form an HDP-CVD film on the first wiring layer, it is possible to suppress the deterioration of the detrapping / retention characteristics of the nonvolatile memory element, and the reliability of the semiconductor device according to the first embodiment. Improvements can be made. As described above, by using the first wiring layer as the embedded wiring, an effect of not forming the HDP-CVD film directly on the first wiring layer can be obtained.

  Next, a hole 21a is formed in the interlayer insulating film 21 by using a photolithography technique and an etching technique. The wiring 20a is exposed at the bottom of the hole 21a. Here, as shown in FIG. 9, it is assumed that the position where the hole 21a is formed deviates from the place where it should originally be formed. The interlayer insulating film 21 is formed from a TEOS film, and the interlayer insulating film 18 is also formed from a TEOS film. For this reason, when the hole 21a is displaced, the interlayer insulating film 18 is also etched. However, the interlayer insulating film 17 formed below the interlayer insulating film 18 is formed of a silicon-rich oxide film having a silicon content different from that of the TEOS film. Therefore, the etching of the hole 21 a that has been displaced is stopped at the interlayer insulating film 17. That is, the silicon-rich oxide film is difficult to be etched under the conditions for etching the TEOS film, and thus functions as an etching stopper. As a result, even if the formation position of the hole 21a is deviated, the hole 21a does not reach the semiconductor substrate, and it is possible to prevent a short circuit between the wiring and the semiconductor substrate.

  In the following description, it is assumed that the hole 21a is not displaced. As shown in FIG. 10 subsequent to FIG. 8, a titanium / titanium nitride film and a tungsten film are laminated on the interlayer insulating film 21 including the hole 21a. Then, unnecessary titanium / titanium nitride film and tungsten film on the interlayer insulating film 21 are removed by, for example, the CMP method, while the plug 22 is formed by leaving the titanium / titanium nitride film and tungsten film in the hole 21a.

Subsequently, as shown in FIG. 11, a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film are sequentially stacked on the interlayer insulating film 21 on which the plug 22 is formed. Then, these laminated films are patterned using a photolithography technique and an etching technique. By this patterning, the wiring 23 constituting the second wiring layer is formed. The wiring 23 is not a buried wiring embedded in the interlayer insulating film 21 but has a normal wiring structure formed on the interlayer insulating film 21. For this reason, on the interlayer insulation film 21, the area | region in which the wiring 23 was formed becomes high, and the level | step difference is formed. In order to embed this step, an HDP-CVD film 24 having excellent step burying characteristics is formed on the interlayer insulating film 21 on which the wiring 23 is formed, as shown in FIG. The HDP-CVD film 24 is formed using a high-density plasma CVD method with an ion density of 10 ¹² to 10 ¹³ / cm ³ . As the film forming conditions, silane gas, O ₂ , Ar, or the like is used as a raw material, and the pressure is several mTorr (0.133 Pa). Although the HDP-CVD film 24 can satisfactorily fill the step due to the wiring 23, it contains a large amount of impurities such as water and hydrogen. However, in the first embodiment, since the silicon-rich oxide film that traps impurities is formed in the first wiring layer below the second wiring layer, the detrapping and retention characteristics of the nonvolatile memory element are deteriorated. Can be prevented.

  Next, an interlayer insulating film 25 made of, for example, a TEOS film is formed on the HDP-CVD film 24. Then, as shown in FIG. 13, a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film are sequentially stacked on the interlayer insulating film 25. Then, these laminated films are patterned using a photolithography technique and an etching technique. Thereby, the wiring 26 which comprises a 3rd wiring layer can be formed.

  Subsequently, as shown in FIG. 14, an HDP-CVD film 27 is formed on the interlayer insulating film 25 on which the wirings 26 are formed, and an interlayer insulating film 28 made of, for example, a TEOS film is formed on the HDP-CVD film 27. To do. Thereafter, a multilayer wiring structure is formed in the same manner. In this way, the semiconductor device according to the first embodiment can be manufactured.

(Embodiment 2)
In the first embodiment, the example in which the wiring configuring the first wiring layer is the embedded wiring has been described. However, in the second embodiment, the wiring configuring the first wiring layer and the second wiring layer is referred to as the embedded wiring. An example will be described.

  FIG. 15 is a sectional view showing a wiring structure of the semiconductor device according to the second embodiment. In FIG. 15, the configuration below the insulating film 14 is the same as that in FIG.

  In FIG. 15, an interlayer insulating film 17 and an interlayer insulating film 18 are stacked on the insulating film 14 on which the plug 16 is formed. Here, the interlayer insulating film 17 is formed of a silicon-rich oxide film, and the interlayer insulating film 18 is formed of a TEOS film. In the interlayer insulating film 17 and the interlayer insulating film 18, a groove 19 penetrating these films is formed, and wirings 20 a to 20 c are formed so as to be embedded in the groove 19. As described above, since the wirings 20a to 20c constituting the first wiring layer are formed of the embedded wiring as in the first embodiment, the same effect as in the first embodiment can be obtained. In the first embodiment, the wirings 20a to 20c are formed of a laminated film of a titanium / titanium nitride film and a tungsten film. However, as in the second embodiment, the wirings 20a to 20c are made of titanium / titanium nitride. You may make it form from the laminated film of a film | membrane and a copper film.

  A silicon nitride film 29 serving as a barrier insulating film is formed on the interlayer insulating film 18 in which the wirings 20a to 20c are embedded in order to prevent diffusion of copper constituting the wirings 20a to 20c. On the silicon nitride film 29, an interlayer insulating film 30 made of, for example, a TEOS film is formed.

  A groove 31 is formed in the interlayer insulating film 30, and the surface of the wiring 20 a is exposed at the bottom of the groove 31. A plug and a wiring 32 are formed in the groove 31 and are electrically connected to the wiring 20a formed in the lower layer. The wiring 32 constituting the second wiring layer is also formed as a buried wiring, and is buried in the groove 31 formed in the interlayer insulating film 30. The wiring 32 is formed of, for example, a laminated film of a titanium / titanium nitride film and a copper film.

  A silicon nitride film 33 for preventing diffusion of copper is formed on the interlayer insulating film 30 in which the wiring 32 is embedded. An interlayer insulating film 34 made of, for example, a TEOS film is formed on the silicon nitride film 33. Yes. On the interlayer insulating film 34, a wiring 35 constituting a third wiring layer is formed. The wiring 35 is formed not as a buried wiring but as a normal wiring, and is formed of, for example, a laminated film of a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film.

  Since the wiring 35 is not a buried wiring, there is a step between the region where the wiring 35 is formed on the interlayer insulating film 34 and the region where the wiring 35 is not formed. Therefore, an HDP-CVD film 36 is formed on the interlayer insulating film 34 on which the wiring 35 is formed in order to fill the step. On the HDP-CVD film 36, an interlayer insulating film 37 made of, for example, a TEOS film is formed.

  According to the second embodiment, not only the wirings 20a to 20c constituting the first wiring layer but also the wiring 32 constituting the second wiring layer are embedded wirings. Therefore, there is no step due to the wiring 32 constituting the second wiring layer, and the surface of the interlayer insulating film 30 in which the wiring 32 is embedded is flat. Therefore, it is not necessary to form an HDP-CVD film on the wiring 32 constituting the second wiring layer. In the first embodiment, since the second wiring layer and the third wiring layer were not buried wirings, it was necessary to form HDP-CVD films on the respective wiring layers. On the other hand, since the second wiring layer is also a buried wiring in the second embodiment, it is not necessary to form an HDP-CVD film on the second wiring layer. For this reason, in the second embodiment, it is only necessary to form the HDP-CVD film only on the third wiring layer that is not a buried wiring. That is, since the number of HDP-CVD films can be reduced as compared with the first embodiment, it is possible to further suppress the degradation of the detrap retention characteristics due to the impurities present in the HDP-CVD film. .

  The semiconductor device according to the second embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

  The steps from FIG. 3 to FIG. 7 are the same as those in the first embodiment. However, a laminated film of a titanium / titanium nitride film and a copper film is used as a material constituting the wirings 20a to 20c. Subsequently, as shown in FIG. 16, a silicon nitride film 29 is formed on the interlayer insulating film 18 in which the wirings 20a to 20c are embedded. The silicon nitride film 29 has a function of preventing copper constituting the wirings 20a to 20c from diffusing to the outside, and can be formed by, for example, a CVD method.

  Next, as shown in FIG. 17, since the interlayer insulating film 18 in which the wirings 20a to 20c are embedded is flat, it is not necessary to form an HDP-CVD film. For example, a TEOS film is formed on the silicon nitride film 29. An interlayer insulating film 30 is formed. Then, the trench 31 is formed in the interlayer insulating film 30 by using a photolithography technique and an etching technique.

  Subsequently, a titanium / titanium nitride film and a copper film are stacked on the interlayer insulating film 30 including the inside of the trench 31. Then, unnecessary titanium / titanium nitride films and copper films formed on the interlayer insulating film 30 are removed by CMP to embed the titanium / titanium nitride films and copper films only in the trenches 31. FIG. The plug and wiring 32 shown are formed. The wiring 32 becomes a wiring constituting the second wiring layer.

  Here, since the wiring 32 constituting the second wiring layer is a buried wiring, the surface of the interlayer insulating film 30 in which the wiring 32 is buried is flat. Therefore, it is not necessary to form an HDP-CVD film on the interlayer insulating film 30 in which the wiring 32 is embedded. As shown in FIG. 19, after forming the silicon nitride film 33, an interlayer insulating film 34 made of, for example, a TEOS film is formed. Form. Then, a titanium / titanium nitride film, an aluminum film, and a titanium / titanium nitride film are stacked on the interlayer insulating film 34. Then, these laminated films are patterned using a photolithography technique and an etching technique. By this patterning, the wiring 35 constituting the third wiring layer can be formed.

  Next, as shown in FIG. 15, an HDP-CVD film 36 is formed to fill the step due to the wiring 35, and an interlayer insulating film 37 made of, for example, a TEOS film is formed on the HDP-CVD film 36. The following steps are the same and will be omitted. In this manner, the semiconductor device according to the second embodiment can be formed.

  Also in the second embodiment, since the interlayer insulating film 17 made of a silicon-rich oxide film serves as an etching stopper when forming the groove 31, the gap between the wiring due to the penetration of the groove 31 and the semiconductor substrate is used. Can be easily prevented.

(Embodiment 3)
In the first embodiment, the example in which the interlayer insulating film 17 formed in the same layer as the wiring 20a constituting the first wiring layer is a silicon-rich oxide film has been described. In the third embodiment, an example in which a silicon-rich oxide film is divided into a plurality of layers will be described.

  FIG. 20 is a cross-sectional view showing the wiring structure of the semiconductor device according to the third embodiment. As shown in FIG. 20, in the third embodiment, silicon-rich oxide films are formed on the interlayer insulating film (first interlayer insulating film) 17a and the interlayer insulating film (third interlayer insulating film) 17b. That is, the interlayer insulating film 17a in the same layer as the wiring 20a constituting the first wiring layer is made a silicon-rich oxide film, and an interlayer insulating film 17b made of a silicon-rich oxide film is formed on the first wiring layer. ing. Also with this configuration, it is possible to prevent deterioration of the detrapping / retention characteristics of the nonvolatile memory element.

  Here, an interlayer insulating film 17b made of a silicon-rich oxide film is also formed on the first wiring layer. Since the first wiring layer is formed by the embedded wiring, the surface of the interlayer insulating film (second interlayer insulating film) 18 in which the first wiring layer is embedded is flat. That is, the surface of the interlayer insulating film 18 has no step due to the first wiring layer. Therefore, there is no problem even if the interlayer insulating film 17b is formed on the interlayer insulating film 18 in which the first wiring layer is embedded.

  The interlayer insulating films 17a and 17b are formed from a silicon-rich oxide film. On the other hand, the interlayer insulating film 18 is formed of a normal silicon oxide film, and is a silicon oxide film in which the ratio of oxygen atoms to silicon atoms is 1.9 to 2.0. Therefore, it can be seen that the interlayer insulating films 17 a and 17 b are composed of films having a larger ratio of silicon atoms to oxygen atoms than the interlayer insulating film 18.

  When the silicon-rich oxide film is divided into a plurality of layers as in the third embodiment, there are the following advantages. Along with the miniaturization of semiconductor devices, the wiring layer is becoming thinner. In this case, it is required to reduce the thickness of the interlayer insulating film 17a and the interlayer insulating film 18 in which the wiring 20a is embedded. Therefore, it is difficult to secure a film thickness sufficient to prevent the deterioration of the detrapping / retention characteristics only by the film thickness of the interlayer insulating film 17a made of a silicon-rich oxide film. At this time, in addition to the interlayer insulating film 17a, an interlayer insulating film 17b made of a silicon-rich oxide film is formed on the wiring 20a, thereby ensuring a film thickness sufficient to prevent the deterioration of the detrapping / retention characteristics. it can. That is, the reliability of the semiconductor device can be improved if the combined thickness of the interlayer insulating film 17a and the interlayer insulating film 17b is more than the minimum necessary to prevent the deterioration of the detrapping / retention characteristics. . According to the third embodiment, it is possible to reduce the thickness of the first wiring layer made of the embedded wiring and to prevent the deterioration of the detrapping / retention characteristics. For example, by setting the combined film thickness of the interlayer insulating film 17a and the interlayer insulating film 17b to 100 nm or more and 300 nm, it is possible to prevent the detrapping / retention characteristics from deteriorating.

  Next, the semiconductor device manufacturing method according to the third embodiment will be briefly described with respect to differences from the first embodiment. First, the steps from FIG. 3 to FIG. 7 are the same as those in the first embodiment. However, the interlayer insulating film 17 a shown in FIG. 20 is formed thinner than the interlayer insulating film 17. Thereby, the first wiring layer can be thinned.

  Subsequently, as shown in FIG. 20, an interlayer insulating film 17b made of a silicon-rich oxide film is formed on the interlayer insulating film 18 in which the wirings 20a to 20c are embedded. Similarly to the interlayer insulating film 17a, the interlayer insulating film 17b can be formed by a plasma CVD method having an ion concentration lower than that of the high-density plasma CVD method. The total thickness of the interlayer insulating film 17a and the interlayer insulating film 17b is, for example, 100 nm or more and 300 nm or less. Since the following steps are the same as those in the first embodiment, description thereof is omitted. In this way, the semiconductor device according to the third embodiment can be manufactured.

  In the third embodiment, the interlayer insulating film 17b made of a silicon-rich oxide film also serves as an etching stopper when the plug 22 is formed. Therefore, the wiring between the wiring due to the penetration of the plug 22 and the semiconductor substrate is used. Can be easily prevented.

(Embodiment 4)
In the first embodiment, the example in which the interlayer insulating film 17 formed in the same layer as the wiring 20a constituting the first wiring layer is formed of a silicon-rich oxide film has been described. In the fourth embodiment, an example in which a silicon-rich oxide film is formed on the first wiring layer that is a buried wiring will be described.

FIG. 21 is a cross-sectional view showing a wiring structure of the semiconductor device according to the fourth embodiment. As shown in FIG. 21, an interlayer insulating film (fourth interlayer insulating film) 18 made of, for example, a TEOS film is formed on the insulating film 14 on which the plug 16 is formed. A groove 19 is formed in the interlayer insulating film 18, and wirings 20 a to 20 c are formed so as to fill the groove 19.
An interlayer insulating film (fifth interlayer insulating film) 17 made of a silicon-rich oxide film is formed on the interlayer insulating film 18 in which the wirings 20a to 20c are embedded. By providing the interlayer insulating film 17, it is possible to prevent the deterioration of the detrapping / retention characteristics of the nonvolatile memory element. That is, in the first embodiment, the interlayer insulating film 17 is formed in the same layer as the wirings 20a to 20c. However, in the fourth embodiment, the interlayer insulating film 17 is formed on the interlayer insulating film 18 in which the wirings 20a to 20c are embedded. Forming. Even if formed in this manner, impurities contained in the HDP-CVD films 24 and 27 can be captured before reaching the nonvolatile memory element, so that the detrapping and retention characteristics can be prevented from deteriorating.

  Here, since the wirings 20a to 20c constituting the first wiring layer are formed by the embedded wiring, the surface of the interlayer insulating film 18 in which the first wiring layer is embedded is flat. That is, the surface of the interlayer insulating film 18 has no step due to the first wiring layer. Therefore, there is no problem even if the interlayer insulating film 17 is formed on the interlayer insulating film 18 in which the first wiring layer is embedded.

  The interlayer insulating film 17 is formed from a silicon-rich oxide film. On the other hand, the interlayer insulating film 18 is formed of a normal silicon oxide film, and is a silicon oxide film in which the ratio of oxygen atoms to silicon atoms is 1.9 to 2.0. Therefore, it can be seen that the interlayer insulating film 17 is composed of a film having a larger ratio of silicon atoms to oxygen atoms than the interlayer insulating film 18.

  Next, the semiconductor device manufacturing method according to the fourth embodiment will be briefly described with respect to differences from the first embodiment.

  In the fourth embodiment, as shown in FIG. 21, an interlayer insulating film 18 made of, for example, a TEOS film is formed on the insulating film 14 on which the plug 16 is formed. Then, after forming a groove 19 in the interlayer insulating film 18, wirings 20 a to 20 c are formed so as to be embedded in the groove 19. Thereafter, an interlayer insulating film 17 is formed on the interlayer insulating film 18 in which the wirings 20a to 20c are embedded. This interlayer insulating film 17 is formed from a silicon-rich oxide film. Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted. In this way, the semiconductor device according to the fourth embodiment can be manufactured.

  Also in the fourth embodiment, since the interlayer insulating film 17 made of a silicon-rich oxide film serves as an etching stopper when forming the plug 22, the gap between the wiring due to the penetration of the plug 22 and the semiconductor substrate is used. Can be easily prevented.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above-described embodiment, an example in which the present invention is applied to a semiconductor device in which a nonvolatile memory element is formed has been described. However, a threshold voltage variation caused by impurities entering a gate insulating film also occurs in a normal MISFET. Therefore, the present invention can be applied to a semiconductor device in which a normal MISFET is formed.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is sectional drawing which showed the structure of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which showed the mode when the position shift of a plug occurred. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device in the first embodiment. FIG. FIG. 4 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 3; FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 4; FIG. 6 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 5; FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 6; FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 7; It is sectional drawing which showed the mode when the position shift of a hole produced. FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 8; FIG. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 13; FIG. 6 is a cross-sectional view showing a wiring structure of a semiconductor device in a second embodiment. 11 is a cross-sectional view showing a manufacturing step of the semiconductor device in the second embodiment. FIG. FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 16; FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 17; FIG. 19 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 18; FIG. 6 is a cross-sectional view showing a wiring structure of a semiconductor device in a third embodiment. FIG. 6 is a cross-sectional view showing a wiring structure of a semiconductor device in a fourth embodiment.

Explanation of symbols

1 semiconductor substrate 2 element isolation region 3 p-type well 4 p-type well 5 gate insulating film 6 floating gate electrode 7 ONO film 8 control gate electrode 9 dummy electrode 10 n-type semiconductor region 11 gate insulating film 12 gate electrode 13 n-type semiconductor region 14 insulating film 15 plug 16 plug 17 interlayer insulating film 17a interlayer insulating film 17b interlayer insulating film 18 interlayer insulating film 19 groove 19a titanium / titanium nitride film 19b tungsten film 20a-20c wiring 21 interlayer insulating film 21a hole 22 plug 23 wiring 24 HDP -CVD film 25 Interlayer insulating film 26 Wiring 27 HDP-CVD film 28 Interlayer insulating film 29 Silicon nitride film 30 Interlayer insulating film 31 Groove 32 Wiring 33 Silicon nitride film 34 Interlayer insulating film 35 Wiring 36 HDP-CVD film 37 Interlayer insulating film

Claims (20)

A semiconductor device having a semiconductor element and a plurality of wiring layers,
(A) a first interlayer insulating film formed on the semiconductor element;
(B) a second interlayer insulating film formed on the first interlayer insulating film;
(C) a groove penetrating the first interlayer insulating film and the second interlayer insulating film;
(D) a wiring embedded in the groove;
The semiconductor device according to claim 1, wherein the first interlayer insulating film is a film having a larger ratio of silicon atoms to oxygen atoms than a film containing oxygen atoms and silicon atoms constituting the second interlayer insulating film.   2. The semiconductor device according to claim 1, wherein the first interlayer insulating film and the second interlayer insulating film are silicon oxide films.   3. The semiconductor device according to claim 2, wherein the first interlayer insulating film has a ratio of oxygen atoms to silicon atoms of 1.5 or more and less than 1.9.   3. The semiconductor device according to claim 2, wherein a thickness of the first interlayer insulating film is not less than 100 nm and not more than 300 nm.   3. The first interlayer insulating film is a silicon oxide film generated using silane gas as a raw material, and the second interlayer insulating film is a silicon oxide film generated using TEOS as a raw material. Semiconductor device.   The said 1st interlayer insulation film and the said 2nd interlayer insulation film are formed of the plasma chemical vapor deposition method whose ion density is lower than the high-density plasma chemical vapor deposition method. Semiconductor device. And a third interlayer insulating film formed on the second interlayer insulating film in which the wiring is embedded,
2. The third interlayer insulating film is a film having a larger ratio of silicon atoms to oxygen atoms than a film containing oxygen atoms and silicon atoms constituting the second interlayer insulating film. Semiconductor device.   8. The semiconductor device according to claim 7, wherein the first interlayer insulating film, the second interlayer insulating film, and the third interlayer insulating film are silicon oxide films.   9. The semiconductor device according to claim 8, wherein a total thickness of the first interlayer insulating film and the third interlayer insulating film is not less than 100 nm and not more than 300 nm.   The semiconductor device according to claim 1, wherein the semiconductor element is a nonvolatile memory element.   The semiconductor device according to claim 1, wherein the wiring is formed of a tungsten film or a copper film. A semiconductor device having a semiconductor element and a plurality of wiring layers,
(A) a fourth interlayer insulating film;
(B) a groove penetrating the fourth interlayer insulating film;
(C) a wiring embedded in the groove;
(D) a fifth interlayer insulating film formed on the fourth interlayer insulating film in which the wiring is embedded;
The semiconductor device according to claim 5, wherein the fifth interlayer insulating film is a film having a larger ratio of silicon atoms to oxygen atoms than a film containing oxygen atoms and silicon atoms constituting the fourth interlayer insulating film.   13. The semiconductor device according to claim 12, wherein the fourth interlayer insulating film and the fifth interlayer insulating film are silicon oxide films. A method of manufacturing a semiconductor device having a semiconductor element and a plurality of wiring layers,
(A) forming the semiconductor element on a semiconductor substrate;
(B) forming a first interlayer insulating film on the semiconductor element;
(C) forming a second interlayer insulating film on the first interlayer insulating film;
(D) forming a groove penetrating the first interlayer insulating film and the second interlayer insulating film;
(E) forming a conductor film on the second interlayer insulating film including the inside of the groove;
(F) removing the conductor film formed other than the groove, thereby forming a wiring made of the conductor film embedded in the groove;
The first interlayer insulating film is a film having a larger ratio of silicon atoms to oxygen atoms than a film containing oxygen atoms and silicon atoms constituting the second interlayer insulating film. Method.   15. The method of manufacturing a semiconductor device according to claim 14, wherein the first interlayer insulating film and the second interlayer insulating film are silicon oxide films.   16. The first interlayer insulating film is a silicon oxide film generated using silane gas as a raw material, and the second interlayer insulating film is a silicon oxide film generated using TEOS as a raw material. Semiconductor device manufacturing method.   15. The semiconductor device according to claim 14, wherein the first interlayer insulating film and the second interlayer insulating film are formed by a plasma chemical vapor deposition method having an ion density lower than that of the high density plasma chemical vapor deposition method. Manufacturing method. further,
(G) comprising a step of forming a third interlayer insulating film on the second interlayer insulating film in which the wiring is embedded;
15. The third interlayer insulating film is a film having a larger ratio of silicon atoms to oxygen atoms than a film containing oxygen atoms and silicon atoms constituting the second interlayer insulating film. Semiconductor device manufacturing method. A method of manufacturing a semiconductor device having a semiconductor element and a plurality of wiring layers,
(A) forming a fourth interlayer insulating film;
(B) forming a groove penetrating the fourth interlayer insulating film;
(C) forming a conductor film on the fourth interlayer insulating film including the inside of the groove;
(D) forming a wiring made of the conductor film embedded in the groove by removing the conductor film formed other than the groove;
(E) forming a fifth interlayer insulating film on the fourth interlayer insulating film in which the wiring is embedded, and
The fifth interlayer insulating film is a film having a larger ratio of silicon atoms to oxygen atoms than a film containing oxygen atoms and silicon atoms constituting the fourth interlayer insulating film. Method.   20. The method of manufacturing a semiconductor device according to claim 19, wherein the fourth interlayer insulating film and the fifth interlayer insulating film are silicon oxide films.

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