JP2001093979A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain high reliability of circuit devices by properly preventing diffusion of hydrogen, moisture or the like into circuit devices such as nonvolatile memory cells. SOLUTION: A memory cell 12 is formed on a semiconductor substrate 11, and a first wiring layer 14 is formed on the memory cell 12 via a first interlayer insulating film 13. A second wiring layer 16 is formed as an upper layer of the first wiring layer 14. A TEOS oxide film 15b having a flat surface is formed between the first wiring layer 14 and the second wiring layer 16 for offsetting the difference in levels of the first wiring layer 14 and a plasma oxide film 15a, which is packed more closely than in the TEOS oxide film 15b, is formed under it. A TEOS oxide film 17b having a flat surface is formed for offsetting the difference in levels of the second wiring layer 16, in such a way that it directly covers the top and sides of the second wiring layer 16 and a plasma oxide film 17c, which is packed more closely than in the TEOS oxide film 17b and is thicker than the plasma oxide film 15a, is formed on the oxide film 17b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of electrode wiring layers and a method of manufacturing the same, and more particularly to a nonvolatile semiconductor device having two or more electrode wiring layers. .

[0002]

2. Description of the Related Art A stacked nonvolatile semiconductor memory device having a floating gate and a control gate and storing data by accumulating electric charges in the floating gate will be described below as an example.

Conventionally, in this nonvolatile semiconductor memory device, a silicon nitride film (SiN film) and a plasma SiH4-based silicon oxide film (SiN4 There is a method using a two-layer film structure in which a plasma oxide film is formed. The plasma oxide film is made of silane (S
iH4) A film formed by plasma CVD using a gas. This method aims at blocking the diffusion of hydrogen with a plasma oxide film in order to prevent the hydrogen diffused from the silicon nitride film from causing deterioration of the write / erase characteristics of the nonvolatile memory cell.

On the other hand, in a device having a multilayer wiring structure, as miniaturization progresses, generally, TEOS (Tetraethyl Orthosilicate Gas: TEOS) is used as an insulating film between the wiring layers.
TE deposited by CVD using an organic oxysilane gas typified by Si (OC2H5) 4) gas as a source gas
An OS-based silicon oxide film (hereinafter referred to as a TEOS oxide film) is used.

[0005] However, this TEOS oxide film has a property of easily containing a large amount of water. Therefore, when applied to a nonvolatile memory device, it is known that moisture from the TEOS oxide film deteriorates the charge retention characteristics of the memory cell. As a countermeasure, in a nonvolatile memory device, a plasma oxide film is formed to a thickness of 100 nm under a TEOS oxide film.
A method of forming a thickness of about 200 nm is used.

FIG. 18 is a cross-sectional view of a semiconductor device using a technique of forming a plasma SiH4-based silicon oxide film under a TEOS-based silicon oxide film.

On a semiconductor substrate 101, a memory cell 102
Are formed. A typical example of the memory cell 102 is a stacked gate nonvolatile memory device. A first electrode wiring layer 104 is formed on an interlayer insulating film 103 formed so as to cover the memory cell 102, and a plasma oxide film 105a is entirely formed on the first electrode wiring layer 104 to a thickness of 100 nm.
The thickness is about 200 nm (the film thickness on the electrode wiring layer 104). On top of that, a TEOS oxide film 105b is deposited and planarized.

Further, a second electrode wiring layer 106 is formed on the TEOS oxide film 105b. On the second electrode wiring layer 106, a plasma oxide film 107a is deposited as a passivation film, and a silicon nitride film 107b is formed on the uppermost layer. The thickness of the plasma oxide film 107a formed on the electrode wiring layer 106 is 400 n
m to about 500 nm. By using the structure as shown in FIG. 18, the reliability of the nonvolatile memory cell is ensured.

[0009]

However, as the miniaturization of non-volatile semiconductor memory devices progresses, FIG.
It is becoming difficult to maintain the effect with the structure shown in FIG. That is, in order to prevent diffusion of hydrogen from the silicon nitride film 107b, the thickness of the plasma SiH4-based silicon oxide film 107a needs to be 200 nm or more. However, as the pitch of the second electrode wiring layer 106 becomes narrower as the miniaturization progresses, as shown in FIG. 19, the plasma oxide film 107a with poor deposition coverage is formed as shown in FIG.
Has a small thickness formed on the side surface of the electrode wiring layer 106. For this reason, the plasma oxide film 107a cannot sufficiently prevent the diffusion of hydrogen.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a semiconductor device and a semiconductor device capable of sufficiently preventing diffusion of hydrogen, moisture and the like into circuit elements and maintaining high reliability of the circuit elements. It is an object of the present invention to provide a manufacturing method thereof.

[0011]

To achieve the above object, a semiconductor device according to the present invention comprises a semiconductor substrate, a circuit element formed on the semiconductor substrate, and an insulating film formed on the circuit element via an insulating film. A first wiring layer formed, a second wiring layer formed on the first wiring layer, and between the first wiring layer and the second wiring layer; First
A first insulating film having a substantially flat surface in order to eliminate the step of the wiring layer, and a second insulating film formed under the first insulating film and having a denser structure than the first insulating film formed below the first insulating film. And an insulating film of
A third insulating film formed so as to directly cover an upper surface and a side surface of the second wiring layer and having a substantially flat surface for eliminating a step of the second wiring layer; And a fourth insulating film that is denser than the third insulating film and is thicker than the second insulating film.

According to another aspect of the present invention, there is provided a semiconductor device including a semiconductor substrate, a circuit element formed on the semiconductor substrate, and an interlayer insulating film formed on the circuit element. The first wiring layer is formed between a multilayer wiring layer composed of N layers and a first wiring layer and a second wiring layer.
A first insulating film having a substantially flat surface for eliminating a step in a wiring layer of the first layer, and a film denser than the first insulating film formed under the first insulating film The second consisting of
And a substantially flat surface formed so as to directly cover the upper surface and side surfaces of the (N-1) th wiring layer and to eliminate the steps of the (N-1) th wiring layer. A third insulating film; and a fourth insulating film formed on the third insulating film, denser than the third insulating film, and thicker than the second insulating film. It is characterized by doing.

In order to achieve the above object, a semiconductor device according to the present invention comprises a semiconductor substrate, a circuit element formed on the semiconductor substrate, and a semiconductor device formed on the circuit element via an insulating film. A first wiring layer, a second wiring layer formed above the first wiring layer, and the first wiring layer formed between the first wiring layer and the second wiring layer. A first insulating film having a substantially flat surface for eliminating a step in the layer, and a second insulating film denser than the first insulating film formed under the first insulating film; , And denser than the first insulating film formed on the first insulating film,
A third insulating film having a thickness greater than that of the second insulating film;
A fourth insulating film having a substantially flat surface for eliminating a step of the second wiring layer, which is formed so as to directly cover an upper surface and a side surface of the second wiring layer. It is characterized by.

According to another aspect of the present invention, there is provided a semiconductor device having a semiconductor substrate, a circuit element formed on the semiconductor substrate, and an interlayer insulating film formed on the circuit element. The first wiring layer is formed between a multilayer wiring layer composed of N layers and a first wiring layer and a second wiring layer.
A first insulating film having a substantially flat surface in order to eliminate a step in a wiring layer of the first layer, from a film denser than the first insulating film formed under the first insulating film; A second insulating film, and the first insulating film formed on the first insulating film.
A third insulating film denser than the second insulating film and having a greater thickness than the second insulating film, and formed so as to directly cover the upper surface and side surfaces of the (N-1) th wiring layer; A fourth insulating film having a substantially flat surface to eliminate a step in the (N-1) th wiring layer.

According to the invention described above, at least the lowermost layer of the interlayer insulating film between the electrode wiring layers is formed of a dense insulating film made of a plasma oxide film or the like, so that the nonvolatile memory cells and the like from the upper layer to the lower layer are formed. Can be prevented from diffusing into the circuit element region. In addition, as an interlayer insulating film,
An insulating film made of a TEOS film or the like and having a flattened surface is formed, and a dense film made of a plasma oxide film or the like is formed on the flattened insulating film so as to be thicker than the lowermost plasma oxide film. This can prevent hydrogen from the passivation film including the plasma nitride film from diffusing into the lower circuit element region. With these effects, it is possible to prevent the characteristics of the nonvolatile memory cell and the like from deteriorating, and to realize high reliability.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment] First, a first embodiment of the present invention will be described.
The semiconductor device according to the embodiment will be described. Here, the structure of a stacked gate nonvolatile memory having a floating gate and a control gate, which is a semiconductor device having three wiring layers, will be described as an example.

FIG. 1 is a sectional view showing the structure of the semiconductor device according to the first embodiment.

As shown in FIG. 1, a nonvolatile memory cell 12 is formed on a semiconductor substrate 11. This nonvolatile memory cell 12 is a memory cell having a stacked gate of a floating gate 12b and a control gate 12c on a gate insulating film 12a. A source or drain diffusion layer 12d is formed in the semiconductor substrate 11 on both sides of the floating gate 12b.

On such a structure, for example, a BPSG film is formed as the first interlayer insulating film 13. On the first interlayer insulating film 13, for example, an Al wiring is formed as a first wiring layer 14. First wiring layer 1
4 and the first interlayer insulating film 13, as a second interlayer insulating film 15, a plasma SiH 4 -based silicon oxide film (hereinafter, referred to as a plasma oxide film) 15 a,
Silicon oxide film (Tetraethyl Orthosilicate Gas: S
i (OC2H5) 4) (hereinafter referred to as TEOS oxide film) 1
5b and a plasma SiH4 based silicon oxide film 15c are formed.

Further, an Al wiring, for example, is formed as the second wiring layer 16 on the plasma oxide film 15c. On the second wiring layer 16 and the plasma oxide film 15
c, as a third interlayer insulating film 17, T
An EOS oxide film 17b and a plasma oxide film 17c are formed.

An Al wiring, for example, is formed as a third wiring layer 18 on the plasma oxide film 17c.
On the third wiring layer 18 and the plasma oxide film 17c,
As the passivation film 19, a TEOS oxide film 19a and a silicon nitride film (SiN film) 19b are formed in this order from the bottom.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described.

FIGS. 2 to 5 are cross-sectional views in respective steps showing a method for manufacturing the semiconductor device.

As shown in FIG. 2, first, the semiconductor substrate 11
Then, an ordinary stacked gate nonvolatile memory cell 12 is formed according to a well-known method. This nonvolatile memory cell 12
In this embodiment, a floating gate 12b and a control gate 12c are formed on a semiconductor substrate 11 with a gate insulating film 12a interposed therebetween, and a source and drain diffusion layer 12d is formed.

On the nonvolatile memory cell 12 and the semiconductor substrate 11, a first interlayer insulating film 13 such as B
A PSG film is deposited and its surface is planarized. continue,
A contact hole for taking an electrode is formed in the first interlayer insulating film 13 (not shown). Then, a wiring material film such as Al is formed on the first interlayer insulating film 13 to a thickness of 40 nm.
The first wiring layer 14 is formed by depositing 0 nm and patterning. As a specific Al wiring material film, Ti / Ti
A structure is used in which an Al-Cu film is stacked via an N barrier metal, and a TiN film is further stacked thereon. The same wiring material is used for the upper second and third wiring layers described later.

Next, a plasma oxide film 15a having a film thickness of 10 is formed on the first wiring layer 14 and the first interlayer insulating film 13.
Deposit about 0 to 200 nm. On this plasma oxide film 15a, a TEOS oxide film 15b is deposited. Here, the thickness of the plasma oxide film 15a is set to 100 nm to 200 nm.
The reason why the thickness is set to nm is that if the thickness is less than 100 nm, the effect of preventing diffusion of water or the like becomes insufficient, while if it exceeds 200 nm, the coatability deteriorates and voids are easily generated. Further, it is preferable that the plasma oxide film 15a is deposited on the side surface of the first wiring layer 14 by about 20 nm or more. Therefore, the side surface of the first wiring layer 14 also has
A plasma oxide film 15a having a thickness of about nm or more is formed.

More specifically, the plasma oxide film 15a has a surface reflecting the steps of the first wiring layer 14 by plasma CVD using a mixed gas containing at least a gas of SiH4 and N2O as a source gas. 150n film thickness
about m. The TEOS oxide film 15b is made of Si
(OC2H5) 4) Deposit about 1200 nm thick by CVD using + F2 source gas. This gives T
The EOS-based oxide film 15b is made of 5 × 10
It becomes a film taken in at a concentration of ²⁰ atoms / cm ³ or more.

Subsequently, for example, CMP (Chemical Mechanical)
The surface of the TEOS oxide film 15b is etched and flattened to a thickness of 450 nm by a cal polishing method. This is because, in a device having a multilayer wiring structure of two or more layers, the interlayer insulating film needs to be flat in consideration of the influence on the wiring layer formed as an upper layer. As the flattening method, other than the CMP method, other methods such as a method of applying a resist and performing etch back may be used.

When the pitch of the first wiring layer 14 is reduced with the miniaturization of the wiring, the covering shape of the interlayer insulating film formed thereon is deteriorated, and voids are easily generated. In the first embodiment, fluorine is set to 5 × 10 ²⁰ atoms /
TEOS oxide film 1 under the condition of containing at a high concentration of at least ³ cm ³
5b is formed when the fluorine concentration is 1 × 10 ²⁰ atoms /
This is because the step coverage of the film is superior to that of the TEOS oxide film of cm ³ or less. This is intended to improve shape deterioration due to miniaturization. Further, the preferable fluorine concentration in the TEOS oxide film 15b is:
At the time of film formation, it is about 1 × 10 ²¹ atoms / cm ³ .

The plasma oxide film 15a is a dense film having a lower gas permeability than the TEOS oxide film 15b, but cannot be stacked thickly because of poor step coverage. Therefore, the plasma oxide film 15
By depositing a TEOS oxide film 15b on top of a, the film thickness is increased and the surface is planarized. Further, since the plasma oxide film 15a has a high dielectric constant, the capacitance alone between the wirings becomes large, and this is disadvantageous in increasing the speed. From this point, it is effective to use a TEOS oxide film 15b having a low dielectric constant as an interlayer insulating film having upper and lower electrode wirings.

After flattening the TEOS oxide film 15b, annealing is performed, for example, at 300.degree. Subsequently, as shown in FIG. 2, a plasma oxide film 15c is deposited on the TEOS oxide film 15b under the same conditions as the plasma oxide film 15a to a thickness of about 500 nm. As described above, the plasma oxide film 15c has poor step coverage. However, since the base is flattened by the TEOS oxide film 15b, a sufficient film thickness for preventing hydrogen diffusion can be formed in this step without causing defects.

As described above, the second interlayer insulating film 15 having a three-layer structure in which the plasma oxide film 15a, the TEOS oxide film 15b, and the plasma oxide film 15c are stacked in order from the bottom.
To form

Thereafter, in order to make an electrical connection between the first wiring layer 14 and the second wiring layer 16 formed on the second interlayer insulating film 15, the second interlayer insulating film 15 is formed. Then, a via is opened to form a via plug. In the drawings, vias and via plugs are omitted. Subsequently, a wiring material film such as Al is deposited to a thickness of 600 nm on the second interlayer insulating film 15 and patterned to form a second wiring layer 16.

Next, as shown in FIG. 3, a TEOS oxide film 17b is deposited. Then, the TEOS oxide film 17b
Is flattened by, for example, a CMP method.
Anneal at 50 ° C. As shown in FIG. 4, this planarization removes irregularities on the surface of the TEOS oxide film 17b, and the TEOS oxide film 17b on the second wiring layer 16 has a thickness of 60%.
Flatten until it is about 0 nm. As the flattening method, other than the CMP method as described above, other methods such as a method of applying a resist and etching back may be used.

Subsequently, as shown in FIG. 5, a plasma oxide film 17c is deposited on the TEOS oxide film 17b under the same conditions as those of the plasma oxide film 15c to a thickness of about 500 nm. Thereafter, in order to make an electrical connection between the second wiring layer 16 and the third wiring layer 18, the TEOS oxide film 1 is formed.
7b, a via hole is formed in the multilayer insulating film composed of two layers of the plasma oxide film 17c to form a via plug. In the drawings, vias and via plugs are omitted.

Thereafter, as shown in FIG. 1, a wiring material film such as Al is formed on the plasma oxide film 17c to a thickness of 600 nm.
The third wiring layer 18 is formed by depositing and patterning. On the third wiring layer 18 and the plasma oxide film 17c
A TEOS oxide film 19a is deposited on the TEOS oxide film 19a to a thickness of about 300 nm.
b is deposited to a thickness of about 600 nm. In the subsequent steps, a semiconductor device is manufactured according to a commonly used manufacturing method such as selectively etching the TEOS oxide film 19a and the SiN film 19b to open a pad portion.

In the semiconductor device of this embodiment,
The second interlayer insulating film 15 between the first wiring layer 14 and the second wiring layer 16 is an insulating film having a three-layer structure of a plasma oxide film 15a, a TEOS oxide film 15b, and a plasma oxide film 15c. is there. Further, the third interlayer insulating film 17 between the second wiring layer 16 and the third wiring layer 18 is an insulating film having a two-layer structure of a TEOS oxide film 17b and a plasma oxide film 17c.

Of the second interlayer insulating film 15 having a three-layer structure, the lowermost plasma oxide film 15a prevents the diffusion of moisture from the upper layer, particularly from the TEOS oxide film 15b, into the nonvolatile memory cell. Has the function of preventing. In order to prevent the diffusion of moisture, the thickness of the plasma oxide film 15a needs to be about 100 nm to 200 nm.

The uppermost plasma oxide film 15c of the three-layer structure prevents diffusion of hydrogen from the upper layer, particularly from the silicon nitride film 19b constituting the passivation film 19, into the nonvolatile memory cell 12. It has the function of doing. To prevent the diffusion of hydrogen, the plasma oxide film 15
The thickness of c is desirably 200 nm or more, and is preferably set to a range of 600 nm or less in consideration of the subsequent steps.

The third interlayer insulating film 17 is an insulating film having a two-layer structure of a TEOS oxide film 17b and a plasma oxide film 17c. Below the TEOS oxide film 17b, an upper layer, in particular, a TEOS oxide film 17b No plasma silicon oxide film is formed to prevent diffusion of moisture from the substrate. However, in this embodiment, there is no problem because the lower plasma oxide films 15a and 15c can fulfill their functions instead. Further, the plasma oxide film 17c has a function of preventing hydrogen diffused from the silicon nitride film 19b, which is the passivation film 19, from diffusing into a layer under the silicon oxide film 19b.

As described above, the first wiring layer 14
The plasma oxide film 15a formed on the first and first interlayer insulating films 13 has a thickness of about 100 nm to 200 nm. FIG. 6 is a diagram showing the relationship between the thickness of the plasma oxide film and the amount of permeated water. As can be seen from FIG. 6, when the thickness of the plasma oxide film is set to about 100 nm to 200 nm, the moisture permeating through the plasma oxide film 15a can be sufficiently reduced.

The plasma oxide film 15c formed as the uppermost layer as the second interlayer insulating film 15 has a thickness of about 500 nm. FIG. 7 is a diagram showing the relationship between the thickness of the plasma oxide film and the amount of permeated hydrogen. As can be seen from FIG. 7, when the thickness of the plasma oxide film is set to about 500 nm, hydrogen permeating through the plasma silicon oxide film 15c can be sufficiently reduced.

As described above, according to the first embodiment, diffusion of moisture and hydrogen into the nonvolatile memory cell region can be sufficiently prevented, and a highly reliable nonvolatile memory device can be obtained. It becomes possible.

Although the first embodiment has been described by taking a two-layer gate type nonvolatile memory having a three-layer electrode wiring structure as an example, a device having an n-layer multi-layer electrode wiring structure of four or more layers can be used. Similar effects can be achieved. n
= 4, 5, 6, ..., n. That is, (n
-1) The insulating film between the electrode wiring layer of the layer and the electrode wiring layer of the nth layer has a two-layer structure of a TEOS-based silicon oxide film and a plasma-based silicon oxide film from below, and at least the first layer from the lower layer The insulating film between the second electrode wiring layer and the second electrode wiring layer is formed from below by a plasma silicon oxide film and TE.
OS-based silicon oxide film and plasma-based silicon oxide film
With the layer structure, the same effect as that of the first embodiment can be realized.

[Second Embodiment] Next, a second embodiment of the present invention will be described.
The semiconductor device according to the embodiment will be described. Here, a stacked gate nonvolatile memory having a floating gate and a control gate will be described as an example of a semiconductor device having three wiring layers. This semiconductor device is the same as the first embodiment except that the plasma silicon oxide film 15c of the second interlayer insulating film 15 in the first embodiment is omitted. .

FIG. 8 is a sectional view showing the structure of the semiconductor device according to the second embodiment.

As shown in FIG. 8, a nonvolatile memory cell 12 and a first interlayer insulating film 13 (for example, a BPSG film) are formed on a semiconductor substrate 11 as in the first embodiment. Further, a first wiring layer 14 (for example, an Al wiring) is formed on the first interlayer insulating film 13.

On the first wiring layer 14 and the first interlayer insulating film 13, as the second interlayer insulating film 15, a plasma SiH4-based silicon oxide film 15a and a TEOS-based silicon oxide film 15b are sequentially formed from the bottom. Have been.

Further, for example, an Al wiring is formed as a second wiring layer 16 on the TEOS oxide film 15b. On the second wiring layer 16 and the TEOS oxide film 15
b, as a third interlayer insulating film 17, T
An EOS-based silicon oxide film 17b and a plasma SiH4-based silicon oxide film 17c are formed.

On the plasma silicon oxide film 17c, for example, an Al wiring is formed as the third wiring layer 18. On the third wiring layer 18 and the plasma oxide film 17
On top of c, as a passivation film 19, T
EOS-based silicon oxide film 19a, silicon nitride film (Si
N film 19b is formed.

Next, a method of manufacturing the semiconductor device according to the second embodiment will be described.

FIGS. 9 to 13 are cross-sectional views in respective steps showing a method for manufacturing the semiconductor device.

As shown in FIG. 9, similarly to the first embodiment, first, a nonvolatile memory cell 12 and a first interlayer insulating film 13 (for example, a BPSG film) are formed on a semiconductor substrate 11, Further, a first wiring layer 14 (for example, an Al wiring) is formed on the first interlayer insulating film 13. Subsequently, on the first wiring layer 14 and the first interlayer insulating film 13,
A plasma oxide film 15a is deposited to a thickness of about 100 to 200 nm. Preferably, the thickness of this plasma oxide film 15a is set to about 150 nm. Further, a TEOS oxide film 15b having a film thickness of 1200 is formed on the plasma oxide film 15a.
Deposit about nm. The steps so far are the same as those in the first embodiment.

Next, for example, CMP (Chemical Mechanica)
l Polishing) to remove irregularities on the surface of the TEOS oxide film 15b and to remove the TEOS oxide film 1 on the first wiring layer 14.
Flatten until the film thickness of 5b becomes 600 nm.

The plasma oxide film 15a is a dense film having a lower gas permeability than the TEOS oxide film 15b, as in the first embodiment. However, since the step coverage is not so good, the plasma oxide film 15a is thick. Can't stack. Therefore, by depositing the TEOS oxide film 15b on the plasma oxide film 15a, the film thickness is increased and the surface is flattened. Further, since the plasma oxide film 15a has a high dielectric constant, the capacitance alone between the wirings becomes large, and this is disadvantageous in increasing the speed. From this point, it is effective to use a TEOS oxide film 15b having a low dielectric constant as an interlayer insulating film having upper and lower electrode wirings. After flattening the TEOS oxide film 15b, annealing is performed at, for example, 300 ° C. to 450 ° C. As described above, the second interlayer insulating film 15 having a two-layer structure in which the plasma oxide film 15a and the TEOS oxide film 15b are stacked in order from the bottom is formed.

Thereafter, in order to make an electrical connection between the first wiring layer 14 and the second wiring layer 16 formed on the second interlayer insulating film 15, the second interlayer insulating film 15 is formed. Then, a via is opened to form a via plug. In the drawings, vias and via plugs are omitted. Subsequently, a 400 nm-thick wiring material film such as Al is deposited on the second interlayer insulating film 15 and patterned to form the second wiring layer 16 as shown in FIG.

Next, as shown in FIG. 11, a TEOS oxide film 17b is deposited, and the TEOS oxide film 17b is flattened by, for example, a CMP method, and further annealed. This planarization is performed, as shown in FIG.
b, and the TEOS on the second wiring layer 16 is removed.
The oxide film 17b is planarized until the film thickness becomes about 600 nm. As the flattening method, in addition to the CMP method as described above, a method of applying a resist and etching back, etc.
Other techniques may be used.

Subsequently, as shown in FIG. 13, a plasma oxide film 17c is deposited on the TEOS-based oxide film 17b under the same conditions as those of the plasma oxide film 15c to a thickness of about 500 nm. Thereafter, in order to make an electrical connection between the second wiring layer 16 and the third wiring layer 18, the TEOS oxide film 1 is formed.
7b, a via hole is formed in the multilayer insulating film composed of two layers of the plasma oxide film 17c to form a via plug. In the drawings, vias and via plugs are omitted.

Thereafter, as shown in FIG. 8, a wiring material film such as Al is formed on the plasma oxide film 17c to a thickness of 600 nm.
The third wiring layer 18 is formed by depositing and patterning. On the third wiring layer 18 and the plasma oxide film 17c
A TEOS oxide film 19a is deposited thereon with a thickness of about 300 nm. Further, a SiN film 19b is deposited on this TEOS oxide film 19a to a thickness of about 600 nm. In the subsequent steps,
A semiconductor device is manufactured according to a commonly used manufacturing method such as selectively etching the TEOS oxide film 19a and the SiN film 19b to open a pad portion.

In the semiconductor device of this embodiment,
The second interlayer insulating film 15 between the first wiring layer 14 and the second wiring layer 16 is an insulating film having a two-layer structure of a plasma oxide film 15a and a TEOS oxide film 15b. Also, the second
The third interlayer insulating film 17 between the first wiring layer 16 and the third wiring layer 18 is made of a TEOS oxide film 17b, a plasma oxide film 1
7c is an insulating film having a two-layer structure.

In the second interlayer insulating film 15 having a two-layer structure, the lower plasma oxide film 15a is
In particular, it has a function of preventing moisture from the TEOS oxide film 15b and TEOS oxide film 17b from diffusing into the nonvolatile memory cell. In order to prevent the diffusion of moisture, the thickness of the plasma oxide film 15a needs to be about 100 nm to 200 nm.

The third interlayer insulating film 17 is an insulating film having a two-layer structure of a TEOS oxide film 17b and a plasma oxide film 17c. Under the TEOS oxide film 17b, an upper layer, particularly, a TEOS oxide film 17b No plasma silicon oxide film is formed to prevent diffusion of moisture from the substrate. However, in this embodiment, as described above, there is no problem because the lower plasma oxide film 15a can fulfill its function instead.

Further, the plasma oxide film 17c has a function of preventing hydrogen diffused from the silicon nitride film 19b, which is the passivation film 19, from diffusing to a lower layer. To prevent diffusion of hydrogen, the plasma oxide film 17 is used.
The thickness of c is desirably 200 nm or more, and is preferably set to a range of 600 nm or less in consideration of the subsequent steps.

As described above, the first wiring layer 14
If the thickness of the plasma oxide film 15a formed on the upper and first interlayer insulating films 13 is set to about 100 nm to 200 nm, as shown in FIG. 6, the moisture permeating the plasma oxide film 15a can be sufficiently reduced. Can be. When the thickness of the plasma oxide film 17c formed as the third interlayer insulating film 17 is about 500 nm, hydrogen permeating the plasma oxide film 17c can be sufficiently reduced as shown in FIG. Can be.

As described above, according to the second embodiment, diffusion of moisture and hydrogen into the nonvolatile memory cell region can be sufficiently prevented, and a highly reliable nonvolatile memory device can be obtained. It becomes possible.

Although the second embodiment has been described by taking as an example a two-layer gate type nonvolatile memory having a three-layer electrode wiring structure, a device having an n-layer multi-layer electrode wiring structure of four or more layers can also be used. Similar effects can be achieved. n
= 4, 5, 6, ..., n. That is, (n
-1) The insulating film between the electrode wiring layer of the layer and the electrode wiring layer of the nth layer has a two-layer structure of a TEOS-based silicon oxide film and a plasma-based silicon oxide film from below, and at least the first layer from the lower layer The insulating film between the second electrode wiring layer and the second electrode wiring layer is formed from below by a plasma silicon oxide film and TE.
With the two-layer structure of the OS-based silicon oxide film, the same effect as that of the second embodiment can be realized.

[Third Embodiment] Next, a third embodiment of the present invention will be described.
The semiconductor device according to the embodiment will be described. Here, a stacked gate nonvolatile memory having a floating gate and a control gate will be described as an example of a semiconductor device having three wiring layers. This semiconductor device is the same as the first embodiment except that the plasma silicon oxide film 17c of the third interlayer insulating film 17 in the first embodiment is omitted. .

FIG. 14 is a sectional view showing the structure of the semiconductor device according to the third embodiment.

As shown in FIG. 14, similarly to the first embodiment, a nonvolatile memory cell 12 and a first interlayer insulating film 13 (for example, a BPSG film) are formed on a semiconductor substrate 11.
Is formed on the first interlayer insulating film 13.
A first wiring layer 14 (for example, Al wiring) is formed.

On the first wiring layer 14 and the first interlayer insulating film 13, as a second interlayer insulating film 15, a plasma SiH 4 -based silicon oxide film 15 a and a TEOS-based silicon oxide film (Tetraethyl Orthosilicate) are sequentially provided from the bottom. Gas: Si
(OC2H5) 4) 15b and a plasma SiH4-based silicon oxide film 15c are formed.

Further, the plasma-based silicon oxide film 1
For example, an Al wiring is formed as the second wiring layer 16 on 5c. On the second wiring layer 16 and the plasma oxide film 15c, as a third interlayer insulating film 17, TE
An OS-based silicon oxide film 17b is formed.

An Al wiring, for example, is formed as a third wiring layer 18 on the TEOS oxide film 17b.
On the third wiring layer 18 and the TEOS oxide film 17b,
As a passivation film 19, a TEOS-based silicon oxide film 19a, a silicon nitride film (SiN film) 19
b is formed.

Next, a method of manufacturing the semiconductor device according to the third embodiment will be described.

FIG. 15 to FIG. 17 are cross-sectional views in respective steps showing a method of manufacturing the semiconductor device.

As shown in FIG. 15, similarly to the first embodiment, first, a nonvolatile memory cell 12, a first interlayer insulating film 13 (for example, a BPSG film) are formed on a semiconductor substrate 11.
Is formed, and a first wiring layer 14 (for example, an Al wiring) is formed on the first interlayer insulating film 13. continue,
On the first wiring layer 14 and the first interlayer insulating film 13, a plasma oxide film 15a is formed to a thickness of 100 nm to 200 nm.
about m. Preferably, the plasma oxide film 15
The thickness of a is set to about 150 nm.

Further, on this plasma oxide film 15a,
A TEOS oxide film 15b is deposited. The TEOS oxide film 15b is flattened by, for example, a CMP method, and further subjected to an annealing process. On the TEOS oxide film 15b, a plasma oxide film 15c is deposited on the order of 500 nm under the same conditions as the plasma oxide film 15a. As described above, the plasma oxide film 15a, the TEOS oxide film 15
b, and a second interlayer insulating film 15 having a three-layer structure in which the plasma oxide film 15c is laminated.

After that, a via is opened in the second interlayer insulating film 15 to form a via plug. Second interlayer insulating film 15
A 600 nm thick wiring material film such as Al is deposited thereon,
The second wiring layer 16 is formed by patterning. The steps so far are the same as those in the first embodiment.

Next, as shown in FIG. 16, a TEOS oxide film 17b is deposited. The TEOS oxide film 17b is flattened by, for example, a CMP method, and further annealed. In this planarization, as shown in FIG. 17, the unevenness on the surface of the TEOS oxide film 17b is removed, and the TEOS oxide film 17b on the second wiring layer 16 is planarized until the film thickness becomes about 1000 nm. As the flattening method, other than the CMP method as described above, other methods such as a method of applying a resist and etching back may be used.

Thereafter, in order to make an electrical connection between the second wiring layer 16 and the third wiring layer 18, the TEOS
Via holes are formed in the interlayer insulating film made of the oxide film 17b to form via plugs. In the drawings, vias and via plugs are omitted. Further, as shown in FIG.
On the OS oxide film 17b, a wiring material film of Al or the like having a thickness of 6
The third wiring layer 18 is formed by depositing and patterning 00 nm.

A TEOS oxide film 19a having a thickness of 300 nm is formed on the third wiring layer 18 and the TEOS oxide film 17b.
Is deposited on the TEOS oxide film 19a.
An N film 19b is deposited to a thickness of about 600 nm. In the subsequent steps, a semiconductor device is manufactured according to a commonly used manufacturing method such as selectively etching the TEOS oxide film 19a and the SiN film 19b to open a pad portion.

In the semiconductor device of this embodiment,
The second interlayer insulating film 15 between the first wiring layer 14 and the second wiring layer 16 is an insulating film having a three-layer structure of a plasma oxide film 15a, a TEOS oxide film 15b, and a plasma oxide film 15c. is there. Further, the third interlayer insulating film 17 between the second wiring layer 16 and the third wiring layer 18 is an insulating film having a one-layer structure of a TEOS oxide film 17b.

Of the second interlayer insulating film 15 having the three-layer structure, the lowermost plasma oxide film 15a prevents the diffusion of moisture from the upper layer, particularly from the TEOS oxide film 15b, into the nonvolatile memory cell. Has the function of preventing. In order to prevent the diffusion of moisture, the thickness of the plasma oxide film 15a needs to be about 100 nm to 200 nm.

The uppermost plasma oxide film 15 c of the three-layer structure prevents the diffusion of hydrogen from the upper layer, particularly from the silicon nitride film 19 b constituting the passivation film 19, into the nonvolatile memory cell 12. It has the function of doing. To prevent the diffusion of hydrogen, the plasma oxide film 15
The thickness of c is desirably 200 nm or more, and is preferably set to a range of 600 nm or less in consideration of the subsequent steps. Further, the plasma oxide film 15c
Also has a function of preventing moisture from the TEOS oxide film 17b from diffusing into the nonvolatile memory cells.

As described above, the first wiring layer 14
If the thickness of the plasma oxide film 15a formed on the upper and first interlayer insulating films 13 is set to about 100 nm to 200 nm, as shown in FIG. 6, the moisture permeating the plasma oxide film 15a can be sufficiently reduced. Can be. When the thickness of the plasma oxide film 15c is set to about 500 nm, as shown in FIG. 7, hydrogen permeating the plasma oxide film 15c can be sufficiently reduced.

As described above, according to the third embodiment, the diffusion of moisture and hydrogen into the nonvolatile memory cell region can be sufficiently prevented, and a highly reliable nonvolatile memory device can be obtained. It becomes possible.

Although the third embodiment has been described by taking as an example a two-layer gate type nonvolatile memory having a three-layer electrode wiring structure, a device having an n-layer multi-layer electrode wiring structure of four or more layers can also be used. Similar effects can be achieved. n
= 4, 5, 6, ..., n. That is, (n
-1) the insulating film between the n-th electrode wiring layer and the n-th electrode wiring layer has a one-layer structure of a TEOS-based silicon oxide film;
At least an insulating film between the first electrode wiring layer and the second electrode wiring layer from the lower layer is formed from the lower side of the plasma-based silicon oxide film, the TEOS-based silicon oxide film, and the plasma-based silicon oxide film. With the three-layer structure, the same effect as in the third embodiment can be realized.

[0088]

As described above, according to the present invention, at least the lowermost layer of the interlayer insulating film between the electrode wiring layers is formed of a dense insulating film such as a plasma oxide film, so that the lower layer is formed from the upper layer to the lower layer. Diffusion of water into the circuit element region can be prevented. Further, a planarizing insulating film such as a TEOS film is formed as an interlayer insulating film, and a dense insulating film such as a plasma oxide film having a thickness greater than that of the lowermost plasma oxide film is formed on the planarizing insulating film. The formation prevents diffusion of hydrogen from the passivation film including the plasma nitride film into a circuit element region such as a lower nonvolatile memory cell. With these effects, it is possible to achieve high reliability while maintaining the characteristics of the nonvolatile memory cell and the like.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to a first embodiment.

FIGS. 2A to 2C are cross-sectional views illustrating each step of the method for manufacturing a semiconductor device according to the first embodiment;

FIGS. 3A to 3C are cross-sectional views illustrating each step of the method for manufacturing the semiconductor device according to the first embodiment;

FIGS. 4A to 4C are cross-sectional views illustrating respective steps of the method for manufacturing the semiconductor device according to the first embodiment;

FIGS. 5A to 5C are cross-sectional views illustrating each step of the method for manufacturing the semiconductor device according to the first embodiment;

FIG. 6 is a diagram showing the relationship between the thickness of a plasma oxide film and the amount of water permeation.

FIG. 7 is a diagram showing the relationship between the thickness of a plasma oxide film and the amount of permeated hydrogen.

FIG. 8 is a cross-sectional view illustrating a structure of a semiconductor device according to a second embodiment.

FIG. 9 is a cross-sectional view illustrating a step in the method for manufacturing a semiconductor device according to the second embodiment.

FIGS. 10A to 10C are cross-sectional views in each step showing the method for manufacturing the semiconductor device of the second embodiment.

FIGS. 11A to 11C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a second embodiment.

FIGS. 12A to 12C are cross-sectional views in each step showing the method for manufacturing the semiconductor device of the second embodiment.

FIGS. 13A to 13C are cross-sectional views in each step showing the method for manufacturing the semiconductor device of the second embodiment.

FIG. 14 is a cross-sectional view illustrating a structure of a semiconductor device according to a third embodiment.

FIGS. 15A to 15C are cross-sectional views in each step showing the method for manufacturing the semiconductor device of the third embodiment.

FIGS. 16A to 16C are cross-sectional views in each step showing the method for manufacturing the semiconductor device of the third embodiment.

FIGS. 17A to 17C are cross-sectional views in each step showing the method for manufacturing the semiconductor device of the third embodiment.

FIG. 18 is a cross-sectional view illustrating a structure of a conventional semiconductor device.

FIG. 19 is a cross-sectional view showing the structure of another conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Semiconductor substrate 12 ... Non-volatile memory cell 12a ... Gate insulating film 12b ... Floating gate 12c ... Control gate 12d ... Diffusion layer of source or drain 13 ... 1st interlayer insulating film 14 ... 1st wiring layer 15 ... 2nd 15a: Plasma SiH4-based silicon oxide film (plasma oxide film) 15b: TEOS-based silicon oxide film (Tetraethyl Ortho)
silicate Gas: Si (OC2H5) 4) (TEOS oxide film) 15c ... plasma SiH4-based silicon oxide film 16 ... second wiring layer 17 ... third interlayer insulating film 17b ... TEOS oxide film 17c ... plasma oxide film 17c is formed Have been. 18 third wiring layer 19 passivation film 19a TEOS oxide film 19b silicon nitride film (SiN film)

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA01 AB02 AD90 AD94 AG03 AG09 AG21 5F033 HH09 HH18 HH33 KK09 KK18 KK33 MM08 MM13 QQ31 QQ37 QQ48 RR04 RR06 RR11 RR15 SS01 SS02 SS04 SS11 SS15 TT02 VXXE XX02 XX NA08 PR21 5F101 BA01 BB02 BD41 BD45 BH02 BH05 BH23

Claims (14)

[Claims] 1. A semiconductor substrate, a circuit element formed on the semiconductor substrate, a first wiring layer formed on the circuit element via an insulating film, and formed on an upper layer of the first wiring layer A second wiring layer formed between the first wiring layer and the second wiring layer, and has a substantially flat surface for eliminating a step of the first wiring layer. A first insulating film, and a second insulating film, which is denser than the first insulating film formed under the first insulating film.
And a third insulating film formed so as to directly cover the upper surface and side surfaces of the second wiring layer and having a substantially flat surface for eliminating a step of the second wiring layer A fourth insulating film formed on the third insulating film, which is denser than the third insulating film and which is thicker than the second insulating film.
A semiconductor device comprising: an insulating film; 2. A semiconductor device comprising: a semiconductor substrate; a circuit element formed on the semiconductor substrate; a multilayer wiring layer including N layers formed on the circuit element via an interlayer insulating film; A first insulating film formed between the second insulating layer and the second insulating layer, the first insulating film having a substantially flat surface for eliminating a step in the first wiring layer; A second insulating film made of a film denser than the first insulating film formed on the first insulating film; and an N-th insulating film formed so as to directly cover the upper surface and side surfaces of the (N-1) th wiring layer. A third insulating film having a substantially flat surface in order to eliminate a step in one wiring layer; and a third insulating film formed on the third insulating film, which is denser than the third insulating film. And a fourth insulating film having a thickness greater than that of the second insulating film.
A semiconductor device comprising: an insulating film; 3. The first and third insulating films are silicon oxide films formed using an organic oxysilane gas as a main source gas, and the second and fourth insulating films are plasmas using silane as a main source gas. 3. The semiconductor device according to claim 1, wherein the semiconductor device is a silicon oxide film deposited by a CVD method. 4. The semiconductor device according to claim 1, wherein said second insulating film has a thickness of 100 to 200 nm.
4. The semiconductor device according to claim 1, wherein the semiconductor device has a thickness of: 5. The semiconductor device according to claim 1, wherein the fourth insulating film has a thickness of 200 to 600 nm.
4. The semiconductor device according to claim 1, wherein the semiconductor device has a thickness of: 6. A semiconductor substrate, a circuit element formed on the semiconductor substrate, a first wiring layer formed on the circuit element via an insulating film, and formed on an upper layer of the first wiring layer. A second wiring layer formed between the first wiring layer and the second wiring layer, and has a substantially flat surface for eliminating a step of the first wiring layer. A first insulating film, a second insulating film denser than the first insulating film formed below the first insulating film, and the first insulating film formed on the first insulating film. A third insulating film denser than the second insulating film and having a thickness greater than the second insulating film; and a second insulating film formed so as to directly cover an upper surface and side surfaces of the second wiring layer. A fourth insulating film having a substantially flat surface to eliminate a step in the wiring layer. 7. A semiconductor substrate, a circuit element formed on the semiconductor substrate, a multilayer wiring layer composed of N layers formed on the circuit element via an interlayer insulating film, and a first wiring layer. A first insulating film formed between the second wiring layer and having a substantially flat surface to eliminate a step in the first wiring layer; A second insulating film formed of a film denser than the formed first insulating film, and a denser film formed on the first insulating film than the first insulating film, and A third insulating film having a thickness greater than that of the second insulating film; and a step between the N-1th wiring layer formed so as to directly cover the upper surface and side surfaces of the (N-1) th wiring layer. And a fourth insulating film having a substantially flat surface to solve the problem. 8. The first and fourth insulating films are silicon oxide films formed by using an organic oxysilane gas as a main source gas, and the second and third insulating films are formed by plasma using silane as a main source gas. 8. The semiconductor device according to claim 6, wherein the semiconductor device is a silicon oxide film deposited by a CVD method. 9. The method according to claim 1, wherein the second insulating film has a thickness of 100 to 200 nm.
9. The semiconductor device according to claim 6, wherein the semiconductor device has a thickness of: 10. The semiconductor device according to claim 1, wherein the third insulating film has a thickness of 200 to 600 n.
The semiconductor device according to claim 6, wherein the semiconductor device has a thickness of m. 11. A semiconductor device further comprising a fifth insulating film formed on the fourth insulating film, the fifth insulating film being denser than the fourth insulating film and having a thickness larger than that of the second insulating film. The semiconductor device according to claim 6, wherein: 12. The semiconductor device according to claim 11, wherein said fifth insulating film is a silicon oxide film deposited by a plasma CVD method using silane as a main source gas. 13. The semiconductor device according to claim 13, wherein the fifth insulating film has a thickness of 200 to 600 n.
12. The semiconductor device according to claim 11, having a thickness of m. 14. The semiconductor device according to claim 1, wherein the circuit element includes a nonvolatile memory cell having a charge storage layer.