JP2900729B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a contact hole.

[0002]

2. Description of the Related Art When a contact is opened between wirings, there is the following prior art in order to prevent a short circuit between the wiring and a wiring formed after the opening of the contact due to misalignment of the contact. A conventional method of manufacturing a semiconductor device will be described with reference to FIG. First, as shown in FIG. 5A, after forming a wiring polysilicon 2 for positioning the oxide film 3 thereon, as shown in FIG. 5C, an oxide film 6 is grown as an interlayer film on the upper surface by CVD, and a mask 7 in which a contact pattern is patterned by photoresist is formed. The cross-sectional structure shown in FIG.

Next, as shown in FIG. 5E, anisotropic dry etching is performed using a photoresist mask 7 with an etching amount slightly smaller than the thickness of the oxide film 6 and the oxide film 3. A semiconductor device having a cross-sectional structure as shown in the figure is obtained.
A contact is formed that allows the next wiring to be formed without contacting the wiring polycrystalline silicon 2. Hereinafter, this conventional technique is referred to as a self-alignment contact forming method.

[0004]

However, in this conventional self-alignment contact structure, as shown in FIG. 5 (e), overetching during contact dry etching causes a significant decrease in the film thickness of the sidewalls, and finally, the wiring polycrystalline structure. Silicon appears in the contacts. FIG. 6 shows that the oxide film 3 has a thickness of 200 nm and the oxide interlayer film 6 has a thickness of 2 nm.
When the overetch amount and the wiring oxide film at 00 nm are represented by 16, and the wiring polycrystalline silicon is 11,
The relationship of the minimum oxide film thickness a between the polysilicon and the contact is shown. Normally, at the time of contact etching, over-etching of 50% or more is performed for the purpose of preventing missing defects.
As shown in FIG. 6, the wiring polycrystalline silicon has already appeared in the contact with the overetch of 60%, so that there has been a problem that the overetch cannot be performed sufficiently.

SUMMARY OF THE INVENTION An object of the present invention is to increase a process margin for over-etching during contact etching in a self-alignment contact step, and to significantly reduce a defect in the above-described step and a short-circuit defect with wiring polycrystalline silicon. An object of the present invention is to provide a method for manufacturing a semiconductor device.

[0006]

According to the method of manufacturing a semiconductor device of the present invention, a semiconductor device is provided on a semiconductor substrate with a gate oxide film interposed therebetween.
And side parts are covered with an upper protective film and a side protective film, respectively.
The first conductive film and the second conductive film are arranged to face each other.
Process, the upper protective film and the side protective film respectively
Including the first conductive film and the second conductive film
Between the first conductive film and the second conductive film
The interlayer insulating film is formed of the upper protective film and the side protective film.
Removing the semiconductor device in a self-aligned manner as a mask .
Of the periphery other than the contact surface with the conductive film and in front of the side protective film
Stopper insulating film around the surface other than the contact surface with the interlayer insulating film
And the stopper insulating film
Etching rate of the interlayer insulating film
It is characterized by being slower than G.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

First, as shown in FIG. 1A, a wiring polysilicon 2 and an oxide film 3 are formed on a semiconductor substrate 1. Next, after the nitride film 4 is grown by CVD, an oxide film sidewall 5 is formed, an oxide film interlayer film 6 is further grown, and a photoresist mask 7 is formed. When anisotropic etching is performed from this state using a low-frequency narrow gap type dry contact etcher, FIG.
A shape as shown in FIG. When a low-frequency narrow gap type dry contact etcher is used, the selectivity of the oxide film / nitride film can be controlled up to 5 or more, so that even if the overetch amount is increased, the wiring polycrystalline silicon hardly appears in the contact hole. Further, a margin can be secured for misalignment of the mask. Now add oxide film 3 to 20
0 nm, the nitride film 4 is 50 nm, and the oxide interlayer film 6 is 200
FIG. 2 shows the relationship between the amount of overetching and the minimum film thickness a between the wiring polysilicon and the contact when the thickness is set to nm.
As can be seen from FIG. 2, a minimum interlayer film thickness of 40 nm can be ensured between the wiring polycrystalline silicon and the contact even if 100% overetching is performed.

FIG. 3 is a sectional view of a semiconductor chip shown in the order of steps for explaining a manufacturing method related to the present invention.
This related technology is manufactured when the sidewalls are formed of a nitride film in the self-alignment contact process .
Manufacturing method .

In manufacturing this chip, as shown in FIG. 3A, after forming a wiring polycrystalline silicon 2 and an oxide film 3 on a semiconductor substrate 1, a sidewall 8 is formed by a nitride film. In the same manner as in 1, the oxide interlayer film 6 is grown, and the mask 7 is formed. When anisotropic etching is performed from this state using a low frequency narrow gap dry contact etcher, a shape as shown in FIG. 3B is obtained. When a dry contact etcher having a low-frequency narrow gap is used, the selectivity of the oxide film / nitride film can be set high as in the first embodiment, so that the process margin for over-etching increases. Now oxide film 3 is 200n
FIG. 4 shows the relationship between m, the overetch amount when the oxide interlayer film 6 is 200 nm, and the minimum film thickness a between the wiring polysilicon and the contact.

However, this related art has a problem that when a damaged layer removing step is added after the formation of the sidewall by the nitride film, the shape of the sidewall may be changed.
It has .

[0012]

As described above, the present invention uses a nitride film as a part of the interlayer film in the self-alignment contact step and increases the process margin for over-etching during contact etching. The result is that the yield of the conventional structure, which is caused by a defect in etching and a short circuit with wiring polysilicon, is improved from 50% to 90%.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an overetch amount and a minimum film thickness in the first embodiment in FIG. 1;

FIG. 3 is a cross-sectional view of a semiconductor chip shown in a process order for explaining a manufacturing method related to the present invention.

FIG. 4 is a diagram showing a relationship between an overetch amount and a minimum film thickness of the related art in FIG. 3;

FIG. 5 is a cross-sectional view of a semiconductor chip shown in the order of steps for describing a conventional method of manufacturing a semiconductor device.

6 is a diagram showing a relationship between an overetch amount and a minimum film thickness in the conventional example of FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 wiring polycrystalline silicon 3 oxide film 4 nitride film 5 sidewall (oxide film) 6 interlayer film 7 mask (photoresist) 8 sidewall (nitride film) 11 wiring polycrystalline silicon 12 wiring film + nitride film 13 nitride film 14 Oxide film 15 Mask a Minimum film thickness

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768

Claims (1)

(57) [Claims] 1. A semiconductor substrate having a gate oxide film interposed therebetween.
The upper and side parts of the top protection film and side protection film respectively
Positioning the covered first conductive film and the second conductive film facing each other
Removing the upper protective film and the side protective film.
The first conductive film and the second conductive film each containing
The first conductive film and the second conductive film covered with an insulating film;
The interlayer insulating film between the upper protective film and the side protection
The method of manufacturing a film <br/> semiconductor device comprising a step of self-aligned removal of the mask, the said upper protective layer
Peripheral and side protective films other than the contact surface with the first conductive film
The stopper other than the contact surface with the interlayer insulating film
It is formed so as to be covered with an edge film, and the stopper
The etching rate of the edge film is the etching of the interlayer insulating film.
A method for manufacturing a semiconductor device, wherein the method is slower than a rate .