JPH05175155A - Manufacture of grid line of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent the formation of a silicide film on grid lines and, at the same time, to remove all CVD films from the grid lines without increasing the man-hour during a process for manufacturing the grind lines of semiconductor integrated circuit devices. CONSTITUTION:The title method is a method for manufacturing grid lines of integrated circuit devices including a process for forming a silicide layer in a contact hole by self-matching. The method includes a process for forming films 11 and 12 which do not react with a high melting point metal in a grid line area 103, process for forming an insulating film 105 for insulating an element from a wiring film, and process for forming a contact hole 107. The method also includes a process for removing the insulating film 105 from the grid line area 103, process for forming the high melting point metal for forming a silicide, heat treatment process for making the high melting point metal to react with a substrate in the contact hole 107, and process for removing the non-reacted part from the high melting point metal film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a grid line of a semiconductor integrated circuit device having a step of forming a silicide layer in a submicron contact hole in a self-aligned manner.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there were the following. 3 and 4
FIG. 4 is a sectional view of a conventional grid line manufacturing process of a semiconductor integrated circuit device.

(1) First, as shown in FIG. 3A, a field oxide film 101 is provided on a silicon substrate 100 by using a well-known LOCOS technique, and a wafer 104 in which an element region 102 and a grid line region 103 are formed respectively. To prepare. Here, the grid line region 103 is a region for cutting with a diamond saw (cutter) when the wafer 104 is completed as an integrated circuit and then divided into chips, and a width of about 100 μm is generally prepared.

(2) Next, as shown in FIG. 3B, after forming the elements on the wafer 104, the insulating film 105 formed by the CVD technique for wiring between the elements and the insulating film 105 prior to the insulating film 105. Oxide film 1 to prevent the inflow of impurities
06 is formed. (3) Next, as shown in FIG. 3C, contact holes 107 and grid lines 108 are simultaneously formed in the insulating film 105. Here, regarding the grid line 108,
This will be described with reference to FIG. FIG. 5 shows the grid line portion of the wafer surface after the integrated circuit of the wafer is completed and the cutting process is performed by the diamond saw (cutter).
This is an example of a defect that occurs when the cutting process is performed while the oxide film remains.

As shown in FIG. 5, the grid line area 1
The insulating film 105 remains on the surface of the insulating film 03, and the groove 109 is generally formed by a diamond saw (cutter) having a width of 20 μm at the center of the grid line. However, when the CVD oxide film is present in the grid line region 103, cracks 110 called chipping run from the groove 109 by 100 μm or more, increasing the number of cracks reaching the wire bonding pads 111.
Causes defective electrical characteristics such as a pat leak, resulting in extremely low chip yield. Therefore, generally, the CVD film is not left in the grid line region, and the metal film for wiring also extremely shortens the life of the diamond saw (cutter), so it cannot be left in the grid line region, and the grid line region cannot be left in the silicon substrate. The surface of is exposed. In this way, the grid lines 108 are simultaneously formed in the step of forming the contact holes.

(4) Next, as shown in FIG. 3D, in order to reduce the contact resistance in the submicron contact hole and prevent alloy spikes, a refractory metal for forming a silicide layer, for example, platinum is sputtered. After heat treatment at 500 to 600 ° C., platinum 112 on the insulating film 105
Remains as unreacted, and platinum silicide is formed in each of the contact hole 107 and the grid line 108.

(5) Next, as shown in FIG. 3E, the insulating film 105 is obtained by subjecting the wafer 104 to aqua regia treatment.
The unreacted platinum 112 above is removed, and the aqua repellent platinum silicide has platinum silicide 113 formed in the contact holes 107 and platinum silicide 114 formed in the grid lines 108, respectively. (6) Next, as shown in FIG.
4, a barrier metal 115 as a wiring film, an aluminum film 116, and an amorphous-Si film 117 as an antireflection film necessary for forming a wiring of a submicron width are formed by a sputtering technique, and a resist pattern 118 is formed by a well-known photolithography technique. After forming, amorphous by dry etching technology
The Si film 117, the aluminum film 116, and the barrier metal 115 are etched in this order. Here, no wiring film or the like is left on the grid line 108.

(7) Next, as shown in FIG. 4A, a single-layer wiring film 119 is formed by removing the unnecessary amorphous-Si film 117 on the wiring by dry etching. At the time of etching, the surface of the platinum silicide film 114 of the grid line 108 is attacked by the plasma of dry etching, and also in the overetching step of the dry etching of the barrier metal 115 in the previous step FIG. The surface is attacked by the plasma.

(8) Next, as shown in FIG. 4B, an interlayer insulating film 120 for multi-layer wiring is formed on the wafer 104 by the CVD technique, and is also formed on the grid line 108. (9) Next, as shown in FIG. 4C, a single layer wiring film 11 is formed by a well-known photolithography technique, which is not shown here.
A resist 121 including a via hole pattern and a grid line connecting 9 and the two-layer wiring film was formed, and dry etching was performed.
To form. Therefore, also in this process, the platinum silicide film 114 is attacked by the plasma in the overetching process.

(10) Next, as shown in FIG.
The resist 121 on the wafer 104 is removed, a two-layer wiring film 122 is formed by a sputtering technique, a resist 123 is formed by a well-known photolithography technique, and a grid line 108 and a two-layer wiring 122 are formed by dry etching. It is a thing. Also in this process, the platinum silicide film 114 is subject to plasma attack in the overetching process.

(11) Next, as shown in FIG.
The resist 123 on the wafer 104 is removed, and a passivation film 124 is formed by a CVD technique. Although not shown here, a pattern in which bonding pads are opened and a resist 12 in which grid lines are opened are formed.
5 is formed by the well-known photolithography technique, and the bonding pad and the grid line 108 are formed by dry etching. Similar to the previous step, the platinum silicide film 114 of the grid line 108 is attacked by plasma in the over-etching step.

[0012]

However, in the above-described conventional manufacturing method, since the grid lines are simultaneously formed in the contact hole forming step, the silicide film which originally needs to be formed with only the contact holes is a grid line. However, due to the formation of the above, there were the following problems.

(1) The grid line silicide film is etched in the over-etching step of dry etching of the single-layer / two-layer wiring film, but the etching rate by the fluorine radicals is slow (especially platinum silicide) and the boiling point of the product. Therefore, the dry etching equipment for exclusive use of metal is contaminated and particles are increased, and it is necessary to dedicate equipment and shorten the maintenance cycle.

(2) Dry etching of the antireflection film of the one-layer wiring film and gate polysilicon, dry etching of via holes and LDD sidewalls, dry etching of passivation and Si _{3 of} LOCOS.
In etching N ₄ , each silicon etcher
Oxide film etcher / nitride film etcher cannot be shared due to the problem of contamination, so it is necessary to specialize the device.

(3) The silicon substrate is etched by the silicide film etching by the repeated dry etching from the single-layer wiring to the multi-layer wiring, and the wet cleaning (HF) is performed.
Peeling of the silicide film occurs. (4) In the assembly process, the silicide film on the grid line is peeled off, causing a short circuit between the wire and the substrate.

(5) If the CVD film is left in order to prevent the formation of the silicide film on the grid line, the chip yield is lowered due to the dicing in the assembly process. That is, chipping failure occurs. Due to the above problems, no technically satisfactory product was obtained. The present invention eliminates the above problems, does not increase the number of steps, prevents the formation of a silicide film on a grid line, and further removes all the CVD film of the grid line, which is an excellent grid line for a semiconductor integrated circuit device. It is intended to provide a manufacturing method.

[0017]

In order to achieve the above object, the present invention provides a grid line manufacturing method for a semiconductor integrated circuit device including a step of forming a silicide layer in a contact hole in a self-aligned manner. Of forming a film that does not react with the refractory metal in at least the alignment mark formation area, forming an insulating film that insulates the element from the wiring film, forming a contact hole, and forming an insulating film in the grid line area. A removing step, a step of forming a refractory metal film for forming silicide, a heat treatment step of reacting the substrate of the contact hole with the refractory metal film, and a step of removing the unreacted refractory metal film. Is to be applied.

[0018]

The function of the film formed in the alignment mark formation region is to prevent the grid lines from being silicidized when the contact holes are silicidized.

Therefore, even if the grid line is formed by etching the insulating film in the grid line region in the contact hole forming step, the silicide layer is not formed in the grid line in the silicide layer forming step in a self-aligned manner with the contact hole.

[0020]

Embodiments of the present invention will be described in detail below with reference to the drawings. 1 and 2 are cross-sectional views of a grid line manufacturing process of a semiconductor integrated circuit device showing a first embodiment of the present invention. The same parts as those in the conventional example are designated by the same reference numerals.

(1) First, as shown in FIG. 1A, a field oxide film 101 is provided on a silicon substrate 100 by using a well-known LOCOS technique to form an element region 102 and a grid line region 103, respectively. The grid line region 103 is a region for cutting with a diamond saw (cutter) when the wafer 104 is completed as an integrated circuit and then divided into chips, and a width of about 100 μm is generally prepared.

(2) Next, as shown in FIG. 1B, the wafer 104 is subjected to gate oxidation to obtain a film thickness of 10
Gate oxide film 10 of 0 to 200Å is formed, and low pressure CVD is performed.
A polysilicon film 11 of 1500 to 2000 Å by a sputtering method, and a tungsten silicide film (hereinafter referred to as WSix) 12 of 2000 to 2500 Å by a sputtering method.
After the formation, a well-known photolithographic etching technique is used to form the pattern 13 while leaving the element gate pattern and the grid line, although omitted here. The lower layer is composed of a polysilicon film 11 to which phosphorus is added as an impurity in a sheet resistance of 10 to 20 Ω / □, and the upper layer is made of WSix12.

(3) Next, as shown in FIG. 1C, although not shown here, the wafer 104 is formed by the CVD technique for wiring between the elements after the element forming process after the gate is completed. The insulating film 105 and the thermal oxide film 106 for preventing the inflow of impurities into the insulating film 105 are formed in advance, and then the contact holes 107 and the grid lines 10 are formed by using a well-known photolithography etching technique.
8 is formed.

(4) Next, as shown in FIG. 1 (d), platinum 112 is formed on the wafer 104 by a sputtering method of 200 to 1000Å and then at 500 to 600 ° C. for 20 minutes in an inert atmosphere. Perform heat treatment. Contact hole 107
Platinum silicide is formed on. On the other hand, at the grid line 108, platinum silicide is not formed because the surface is WSix.

(5) Next, as shown in FIG. 1E, the wafer is subjected to aqua regia etching. The platinum 112 on the insulating film 105 and the grid line 108 is removed, and the contact hole 10 which is platinum silicide having aqua regia resistance is removed.
A platinum silicide film 113 is formed on 7. (6) Next, as shown in FIG. 1F, a barrier metal (Ti / W) 115 is formed on the wafer 104 as a wiring film by 100.
0 ~ 2000Å and aluminum film 116 5000 ~
6000 Å, and 500 Å of amorphous-Si film 117 as an antireflection film necessary for forming sub-micron width wiring.
After forming the resist pattern 118 by the well-known photolithography technique, the amorphous-Si film 117 and the aluminum film 116 are sequentially etched by the dry etching technique to form the barrier metal 11.
5 is a plasma dry etch of SF ₆ + CHCl ₃ system.
The over-etching of about 0% is performed, and the WSix12 of the grid line 108 is removed.

(7) Next, as shown in FIG. 2A, the resist pattern 118 on the wafer 104 is removed, and C
F ₄ + O ₂ -based plasma etching was performed, and 100% over-etching was performed on the amorphous-Si etching to form the grid lines 108 from which the polysilicon film 11 was removed and the single-layer wiring film 119.

(8) Next, as shown in FIG. 2B, an interlayer insulating film 120 having a multilayer wiring is formed on the wafer 104 by CVD.
The grid line 108 is a film composed of a gate oxide film and an interlayer insulating film 120, which is produced by a technique and SOG (spin on glass) technique to have a film thickness of 1 μm. (9) Next, as shown in FIG. 2C, a resist including a via hole pattern and a grid line connecting the single-layer wiring film 119 and the double-layer wiring film, which is not shown here by a well-known photolithography technique. 121 is formed and dry etching is performed by 50% overetching, and all the CVD film and the thermal oxide film of the grid line 108 can be removed.

(10) Next, as shown in FIG.
The resist 121 on the wafer 104 is removed, a two-layer wiring film 122 is formed by a sputtering technique, a resist 123 is formed by a well-known photolithography technique, and a grid line 108 and a two-layer wiring film 122 are formed by dry etching. To do. (11) Next, as shown in FIG.
The resist 123 of 04 is removed, and the passivation film 1
Although not shown in the drawing, the pattern 24 in which the bonding pad is opened and the resist 125 in which the grid line is opened are formed by the well-known photolithography technique, and the bonding pad 24 is formed by dry etching. And grid lines 108 are formed.

In the first embodiment, it is estimated that this is because the surface of the grid line is WSix.
The surface of x has a generation rate of a natural oxide film twice or more than that of the surface of a normal silicon substrate, and an oxide film that affects the silicide reaction is formed more quickly after the completion of pre-sputtering cleaning.
(2) Since the temperature of the silicidation reaction is only 600 ° C. and the processing time is about 20 minutes, Pt cannot move in WSix, and it is considered that only a small amount of Si can be supplied from WSix, and as a result, Pt and WSix interface Platinum silicide that can be formed is a thin Pt-rich film, and a W film is formed under the silicide film, and is dissolved by aqua regia etching. From the above two points, it is considered that platinum silicide is not generated. As a result, there is no platinum contamination, so there is no need to specialize the etching equipment or to remove the silicide film.

Further, the fact that TiW is used as the barrier metal for the one-layer wiring and that SF ₆ + CHC is used for the etching
Since l ₃ system plasma is used, WSix / TiW is more than twice as high as the etching rate.
In the over-etching process, the grid line WSix is removed by about 50% etching. Subsequently, in the etching of the amorphous-Si on the one-layer wiring, about 100% of the etching is performed in the over-etching step because it is necessary to completely remove the amorphous-Si. Therefore, the grid line is made of poly-phosphorus containing a large amount of phosphorus. This is a silicon film, and the polysilicon is removed leaving the gate oxide film. And in the via hole etch,
The interlayer insulating film has a thickness of 1 μm, and the oxide film on the grid line can be removed by adding a slight overetch time.

6 to 8 are a plan view and a process sectional view of a semiconductor integrated circuit device showing a second embodiment of the present invention. The same parts as those in the first embodiment are designated by the same reference numerals.

FIG. 6 is a plan view of the second embodiment.
7 is a process sectional view of the embodiment of FIG. In FIG. 6, the element region 102 is separated from the element region 102a of the adjacent chip by the grid line 103. On the grid line 103, an alignment region 128 is provided between the element regions 102 and 102a. 7 and 8 are cross-sectional views of the element region 102 and the grid line 103 taken along the line AA ′ (FIG. 7).
(A1) to (f1) and FIGS. 8 (a1) to (e1)) and a cross-sectional view of the alignment region 128 taken along the line BB ′ (FIGS. 7 (a2) to (f2) and FIG. 8 (a2)). ~ (E
2)), and the second embodiment of the present invention will be described below with reference to these drawings.

First, as shown in FIG. 7A1, a feed oxide film 101 is provided on a silicon substrate 100 using a known LOCOS technique, and a wafer 104 having an element region 102 and a grid line region 103 formed thereon is prepared.
The grid line area 103 is an area for cutting with a diamond saw cutter when the wafer 104 is completed as an integrated circuit and then divided into chips.
It has a width of around 00 μm. On the other hand, as shown in FIG. 7A2, the field oxide film 101 is formed over the entire alignment mark region 128.

Next, as shown in FIG. 7 (b1), although not shown in the present cross-sectional view of the wafer 104, SiO formed by the CVD technique for wiring between the elements after performing the element forming step. Insulating film 105 mainly composed of ₂
A 00 Å film and a 200 Å thermal oxide film 106 for preventing the inflow of impurities into the insulating film 105 are formed prior to the film. Further, as shown in FIG. 7B2, the insulating film 105 is also formed on the alignment mark region 128 by the field oxide film 10.
1 is formed on. After that, a well-known photolithography / etching technique is used to form a contact hole 107 as shown in FIG. 7C1 and leave the insulating film 105 in the grid line region 103 as it is. In addition, as shown in FIG. 7C2, grid lines 129 (hereinafter, referred to as second grid lines) 129 in the alignment mark area for performing alignment by photolithography are also formed in the alignment mark area 128.

Next, platinum 112 is deposited on the wafer 104.
00-1000Å After film formation by sputtering method, 500-
Heat treatment is performed at 600 ° C. for 20 minutes in an inert atmosphere. By this heat treatment, platinum silicide is formed in the contact hole 107. On the other hand, in the grid line region 103, platinum 112 is formed on the insulating film 105 which is an oxide film, so that platinum silicide is not formed. Similarly, FIG.
As shown in 2), platinum silicide is not formed on the second grid line 129 either.

After that, the aqua regia process is performed on the wafer 104 to remove the platinum 112 on the insulating film 105 and the second grid lines 129, and the contact hole 107 has a platinum silicide film 113 having an aqua regia resistance. Are left (FIGS. 7 (e1) and (e2)). Furthermore, in FIG.
1) and (f2), a barrier metal Ti / W115 of 1000 to 2000 is formed as a wiring film on the wafer 104.
Å, the aluminum film 116 is 5000-6000Å,
An .alpha.-Si film 117 is formed as an antireflection film necessary for forming a submicron width wiring by a sputtering technique with a thickness of about 500 .ANG. The resist pattern 118 is formed by the well-known photolithography technique.
Is formed on the α-Si film 117 by the dry etching technique,
Etching is performed on the α-Si film 117 and the aluminum film 116 in this order. Plasma Dr of barrier metal 115
Even if the y-etch is over-etched by about 50%, there is no platinum silicide in the grid line region 103 and the second grid line 129, and no contamination occurs.

Next, as shown in FIGS. 8A1 and 8A2, after removing the resist pattern 118, CF ₄ + O is formed.
By performing a _two- system plasma etching, the α-Si film 117 on the aluminum film 116 is removed and a one-layer wiring film 119 is formed. Even if the etching of the α-Si film 117 is performed by overetching, the second grid line 129
There is no platinum contamination including. After that, as shown in FIG. 8B1, the interlayer insulating film 120 of the multilayer wiring is formed by the CVD technique and the SOG.
An insulating film 105 is formed in the grid line region 103 by forming a film thickness of 1 μm by the (spin-on-glass) technique.
A composite film including the interlayer insulating film 120 is formed. On the other hand, as shown in FIG. 8B2, the field oxide film 101 and the interlayer insulating film 12 are formed on the second grid line 129.
A composite film composed of 0 and 0 is formed.

Although not shown in this sectional view by a well-known photolithography technique, a resist 121 including a via hole pattern and a grid line pattern connecting the one-layer wiring film 119 and the two-layer wiring film is formed on the interlayer insulating film 120. Formed into C
Overetching by narrow gap parallel plate type RIE using F ₄ + CHF ₃ gas system 50-100%
Do in. All the CVD films of the grid line 108, that is, the interlayer insulating film 120 and the insulating film 105, and the thermal oxide film 10
6 can be removed (FIG. 8 (c1)). On the other hand, also in the second grid line 129, the field oxide film 101 having a film thickness about half that of the interlayer insulating film 120 and the insulating film 105 is formed by using the resist 121 as a mask (the etching rate of the thermal oxide film under this etching condition is Similarly, it is removed by etching to form grid lines 108 (FIG. 8C2).

Further, as shown in FIGS. 8 (d1) and 8 (d2), the resist 121 is removed, a two-layer wiring film 122 is formed by a sputtering technique, and a resist 123 is formed by a well-known photolithography technique. The grid line 108 and the two-layer wiring 122 in which the two-layer wiring material does not remain are formed by dry etching. Finally, as shown in FIGS. 8E1 and 8E2, the resist 123 is removed, and the passivation film 12 is removed.
4 is formed by the CVD technique, and although not shown in the present cross-sectional view, a pattern in which the bonding pad is opened and a resist 125 in which the grid line is opened are formed by the well-known photolithography technique, and the bonding pad is formed by dry etching. And grid lines 108 are formed.

As described above, in the second embodiment,
A CVD oxide film is used as an interlayer insulating film of the multi-layer wiring, and a CF ₄ + CHF ₃ gas-based narrow gap parallel plate type RIE is used to etch a via hole for connecting the single-layer wiring and the double-layer wiring. 100%
Since the grid line is etched by the grid line, the insulating film and the thermal oxide film under the interlayer insulating film are removed from the grid line, and the sidewall of the via hole is protected by the deposition film during etching, so the sidewall of the via hole during over etching The shape is not transformed into a barrel. Further, since the aluminum wiring is directly below the via hole and the etching rate is extremely low, the performance of the multilayer wiring is not impaired.

9 (a) and 9 (b) are sectional views showing a third embodiment of the present invention, showing a case of a single layer wiring (one layer wiring). 9 (a) and 9 (b) are the same as FIG. 8 of the second embodiment.
The PSG film 126, which is a passivation film, is formed on the field wiring film 119, the insulating film 105, and the field oxide film 101 of the second grid line 129 by the steps (a1) and (a2).
Of the plasma-excited nitride film 127 having a thickness of about 1 to about 1000 μm by the CVD method, and then the resist 1 having the pattern of the bonding pad and the grid line 108.
25 is formed and CF ₄ plasma etching is performed. After that, etching is performed in the same manner as the via hole etching conditions of the first embodiment until the substrate 100 of the grid line 108 appears, and the resist 125 is removed to simultaneously form the grid line area 103 and the second grid line 129. 108 is formed.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention, and these modifications are not excluded from the scope of the present invention.

[0043]

As described above in detail, according to the present invention, since the film that does not react with the refractory metal is formed in at least the alignment mark formation region of the grid line region, the contact hole forming step. Even if the insulating film in the grid line region is etched to form the grid line, the silicide layer is not formed in the grid line in the silicide layer forming step in a self-aligned manner with the contact hole.

As described above, the grid line C
Since the VD film and the like are all removed, the grid line of the semiconductor integrated circuit device can be efficiently manufactured without lowering the chip yield in dicing in the assembly process and increasing the number of processes.

[Brief description of drawings]

FIG. 1 is a sectional view of a grid line manufacturing process of a semiconductor integrated circuit device showing an embodiment of the present invention (Part 1)

FIG. 2 is a sectional view of a grid line manufacturing process of the semiconductor integrated circuit device showing the embodiment of the present invention (Part 2).

FIG. 3 is a sectional view of a conventional grid line manufacturing process for a semiconductor integrated circuit device (No. 1)

FIG. 4 is a sectional view of a conventional grid line manufacturing process for a semiconductor integrated circuit device (Part 2).

FIG. 5 is an explanatory diagram of problems in the conventional technology.

FIG. 6 is a sectional explanatory view of a second embodiment of the present invention.

FIG. 7 is a process sectional view of the second embodiment of the present invention (No. 1)

FIG. 8 is a process sectional view of the second embodiment of the present invention (No. 2)

FIG. 9 is a sectional view of a third embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 gate oxide film 11 polysilicon film 12 tungsten silicide film (WSix) 13 grid line leaving pattern 100 silicon substrate 101 field oxide film 102 element region 103 grid line region 104 wafer 105 insulating film 106 thermal oxide film 107 contact hole 108 grid line 112 Platinum 113 Platinum silicide film 115 Barrier metal (Ti / W) 116 Aluminum film 117 Amorphous-Si film 118 Resist pattern 119 One-layer wiring film 120 Interlayer insulating film 121, 123, 125 Resist 122 Two-layer wiring film 124 Passivation film

Claims (2)

[Claims] 1. A grid line manufacturing method for a semiconductor integrated circuit device, comprising: forming a silicide layer in a contact hole in a self-aligned manner in an integrated circuit having a polycide gate; (a) forming a polycide film in a grid line region. Steps, (b) a step of forming an insulating film that insulates the element from the wiring film, (c) a step of forming a contact hole, (d) a step of removing the insulating film in the grid line region, and (e) a polycide film A step of forming a refractory metal film for forming a second silicide that is different from the first silicide constituting the above, and (f) a heat treatment step of reacting the substrate of the contact hole with the refractory metal film. (G) a step of removing an unreacted refractory metal film, a grid line manufacturing method for a semiconductor integrated circuit. 2. A step of forming a field oxide film in a region surrounding an active region of a semiconductor substrate and an alignment mark forming region of a grid line, and an insulating film for insulating a device formed on the semiconductor substrate from a wiring layer. A step of forming a contact hole exposing the substrate on the active region by removing a part of the insulating film on the alignment mark forming region and the active region, and thereafter, Grid line manufacturing method for semiconductor integrated circuit, comprising: forming a refractory metal and heat-treating it to react the substrate with exposed contact holes with the refractory metal; and removing the unreacted refractory metal ..