JPH08306786A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide a semiconductor device in which the fabrication yield does not decrease even if the overlap margin of a wide interconnection/hole is set on the order of overlap margin for fine pattern interconnection/hole. CONSTITUTION: In an interconnection structure where wide lines 11 and 12, e.g. a power supply line and an earth line, are connected vertically through a plurality of holes 13, 13 made through an interlayer insulation layer of SiO2 , SiN, etc., the width W11, W12 of the line 11, 12 is set at 10μm or less at the joint. With such structure, shrinkage of resist by UV cure can be suppressed at the joint.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a wiring portion of the semiconductor device.

[0002]

2. Description of the Related Art With the progress of higher integration and higher density of integrated circuits, in memory cells, logic circuits, etc., the line width of metal wiring for interconnection has been miniaturized. 0.45 in sub-half micron generation (64 Mbit)
Metal wiring having a width of about 0.80 μm has come to be used.

However, a wide metal wiring having a width of several tens to 200 μm or more is also used at the same time in order to supply a required current in the power supply line of the peripheral circuit and to prevent noise in the ground line.

In the sub-half micron generation and later,
Contact holes that connect the board to the wiring and between the wiring
Since the miniaturization of through holes is progressing and it becomes difficult to fill holes with Al, a process using W deposition and etch back or a buried metal by W selective CVD method has been adopted. In these methods, in order to reduce the recess amount in the etch back and to keep the deposition time in the selective CVD method constant, the hole diameter must be constant (the hole diameter is one type).

Therefore, not only in the connection between the fine wirings but also in the connection between the wide wirings, it is necessary to adopt a method of arranging and connecting the fine holes in an array. Generally, the wiring / hole overlap margin is defined by the resistance of the holes on the fine wiring.

[0006]

Looking at photolithography and etching processes, when metal wiring mainly made of Al alloy is processed by dry etching using a resist as a mask, it is possible to prevent thermal deformation of the resist during the dry etching. Therefore, the resist is thermally cured (UV cure) at 150 to 200 ° C. while being irradiated with UV light in advance.

In fine metal wiring, the resist is thermally cured by UV curing, but in wide metal wiring such as a power supply line, the resist is thermally cured during UV curing and heat shrinkage (shrank) remarkably occurs. The wiring / hole overlap margin defined by fine wiring (generally 0.3μ in the sub-half micron generation)
(m or less), the holes on the outermost periphery may be dislocated from the metal wiring and may cause a short circuit defect when they are arranged in an array in the case of designing with an overlap margin of the same order. Therefore, for wide metal, it is necessary to separately set a large wiring / hole overlap margin.

In addition, in Japanese Patent Laid-Open No. 3-196663, a slit 1 is formed inside a metal wiring as shown in FIG.
There is disclosed a semiconductor integrated circuit having a shape which is not substantially wide metal wiring by providing 12. In FIG. 5, 110 is a lower layer wiring, 111 is an upper layer wiring, and 114 is a fine wiring. However, in this structure, since the slit is not provided in the connection portion, the resist is significantly shrunken by UV curing, and it is necessary to separately determine a large wiring / hole overlap margin.

The present invention has been made in consideration of the above-mentioned drawbacks, and an object thereof is to widen the width by connecting the wide wirings such as the power supply line and the earth line by suppressing the resist shrank due to UV curing. It is an object of the present invention to provide a semiconductor device having a structure that does not reduce the yield even if the overlap margin of the wiring / hole is about the same as the overlap margin of the wiring / hole defined by the fine wiring.

[0010]

According to another aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein wirings connected in a vertical direction through a plurality of holes in an interlayer insulating film have a wiring width of 10 μm or less at a connecting portion. Characterize.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect.
The wiring according to the present invention is characterized in that the wiring width of the connection portion in one wiring is equal to the wiring width of the portion other than the connection portion.

A semiconductor device according to a third aspect is the semiconductor device according to the first aspect.
In item 2 or 2, one wiring is divided into a plurality of wirings, and a width of a connection portion of each of the divided wirings is 10 μm or less.

The structure and operation of the semiconductor device according to the present invention will be specifically described below. In the sub-half micron generation, the wiring is also fine wiring of about 0.45 to 0.80 μm, so it is common to perform processing by dry etching. The current mainstream novolak type resist for i-line has a heat resistance of only 130 to 140 ° C, so if it is not cured by UV cure, the resist will be thermally deformed during dry etching of the wiring. In the worst case, if the wiring is thin, the shape of the wiring is deteriorated such as disconnection. In order to prevent these, heat curing of the resist by UV curing is essential.

Generally, when the temperature of UV cure increases, the heat resistance of the resist itself improves, but at 200 ° C. or higher, the heat resistance becomes almost constant. On the other hand, schrank in a wide resist becomes remarkable as the UV curing temperature becomes higher, and it does not saturate even at about 200 °. Therefore, UV curing is generally performed at 150 to 220 ° C.

The present inventors investigated the relationship between the wiring width and the degree of shrank in this temperature range. The degree of shrunking is defined by the amount of resist receding from the design dimension, and the relationship between resist line width and shrunking is shown in FIG. Resist line width is 1
When it exceeds 0 μm, shrank appears remarkably, and when it is 10 μm or less, the wiring / hole overlap margin defined by fine wiring (0.3 μm in the sub-half micron generation).
It was found that Schrank was sufficiently small compared to (degree). In other words, considering that an overlapping margin similar to that of a fine wiring is used for a wide wiring, by setting the wiring width to 10 μm or less, receding of the resist due to shrank can be suppressed, and It has been found that the wiring can be processed to the design size (working can be made to a thickness of 0.1 to 0.2 μm smaller than the design size). Therefore, it was found that the yield does not decrease even if a wide wiring / hole overlap margin is not separately set for a wide wiring.

FIG. 1 shows an example of the configuration of the semiconductor device of the present invention. This example shows that a wide wiring 11 and a wiring 12 such as a power line and a ground are vertically connected through a plurality of holes 13, 13, ... In an interlayer insulating film of SiO ₂ , SiN or the like. ing. Assuming that the wiring widths at the connecting portions of the wirings 11 and 12 are W11 and W12, both W11 and W12 are 10 μm or less. By adopting this configuration, it is possible to suppress the shrinkage due to the UV curing of the resist at the connection portion, so that the overlap margin of the wiring / hole is made approximately the same as the wiring / hole overlap margin defined by the fine wiring. You can

The wiring according to the present invention is mainly composed of Al or Al.
Good to be composed of alloys. Wiring resistance can be reduced by using Al or an Al alloy. Therefore, the wiring width of the power supply line, the ground line, etc. can be relatively easily reduced. As the Al alloy, AlSi, A
lSiCu, AlCu, AlPd, etc. are suitable.

The wiring may be composed of a multi-layer wiring mainly composed of Al or an Al alloy and another metal or alloy. In particular, when a wide wiring and a fine wiring are mixed in the same layer, if a layer mainly composed of Al or an Al alloy is in the uppermost layer, a dye-containing resist must be used for notching by halation in photolithography. Therefore, the resolution is insufficient and the wiring width cannot be reduced. Therefore, generally, an antireflection film is laminated on the uppermost layer of the wiring. Naturally, the wide wiring is mixed in the same layer as the fine wiring, so that the antireflection film is laminated. However, there is no problem in terms of function, and it is not necessary to remove the antireflection film. TiN, T as an antireflection film
iW or the like is used. Alternatively, one or both sides of a layer mainly composed of Al or Al alloy may be laminated with a layer of TiW, TiN or the like in order to suppress electromigration of wiring.

FIG. 2 shows another structural example of the semiconductor device of the present invention. In this example, in the wirings 41 and 42 connected through a plurality of holes 43 in the interlayer insulating film such as SiO ₂ or SiN, the wiring width of the connection portion of one wiring is equal to the wiring width of the portion other than the connection portion. The wiring widths W41 and W42 are 10 μm or less.

It is generally said that the rapid narrowing of the wiring width accelerates electromigration. Therefore,
By adopting this configuration, it is possible to prevent a wide wiring from being abruptly reduced at the connection portion, so that disconnection of the wiring due to electromigration can be suppressed and long-term reliability is improved. In this example, the upper and lower wirings have the same wiring width in the connecting portion and the portions other than the connecting portion, but the effect of the present invention is expected even when the wiring width in the connecting portion and the portion other than the connecting portion is the same only on one side. Therefore, it is included in the present invention.

FIG. 3 shows still another configuration example of the semiconductor device of the present invention. In this example, one wiring 52 is a plurality of wirings 52.
It is divided into a, 52b and 52c and is connected to the wiring 51 through a plurality of holes 53a, 53b and 53c in the interlayer insulating film. The wirings 52a, 52b, 52c after the division have a wiring width of 10 μm or less at the connecting portion. By adopting this configuration, the current capacity of the wiring is increased in the power supply line, and the earth line is resistant to noise.

In this example, the number of divided wirings is three, but if there are a plurality of wirings, there is no problem. Further, in this example, only the upper layer wiring is divided, but it is assumed that the present invention includes the division of the lower layer wiring and the division of both the upper layer and lower layer wirings. Further, the present invention includes the case where some or all of the divided wirings are connected again after passing through the connection portion.

In the configuration examples shown in FIGS. 1, 2 and 3, wide wirings are connected to each other through a plurality of holes, but the effect of the present invention can also be expected in the connection of the wirings and the semiconductor substrate. . Therefore, if at least one connected is a wiring, it is included in the present invention.

[0024]

EXAMPLES Next, examples of the present invention and comparative examples will be described. Example 1 After forming a memory cell made of a CMOS having a gate length of 0.35 μm and a peripheral circuit in which wiring is not formed on a semiconductor substrate (silicon wafer), BPSG of 600 is formed by a CVD method.
A 0Å film was formed to form the first interlayer insulating film. After that, a 0.4 μm contact hole is opened in the interlayer insulating film on the source / drain and the gate, and Ti is sputtered to 4
A 00Å film was formed, and the source / drain was silicided by 850 ° C. annealing to reduce the resistance. After that, 8000 liters of W was formed by the CVD method of reducing WF ₆ gas with hydrogen, and then W was buried in the contact hole by etchback using SF ₆ and Ar gas. Then, the AlSiCu is sputtered at 5500 Å and the upper layer is T
iN was formed into a 400Å film. After that, remove the resist by 1.6μ
m coating, a resist mask was formed by photolithography, the resist was thermally cured through UV curing at 150 to 200 ° C., and then the first layer wiring was processed by dry etching using Cl ₂ and BCl ₃ gas.

The wiring of the first layer is wired with a width of 0.50 μm in the memory cell area, and the wiring width is 5 μm in the area connected to the wiring of the second layer in the peripheral circuit power supply line and ground line. In other areas, the wiring has a width of 20 μm.

After processing the wiring of the first layer, NSG was formed into a film of 8000 Å by a CVD method to form an interlayer insulating film of the second layer. After forming a 1.2 μm thick resist mask by photolithography on the second interlayer insulating film, CH
0.50 μm hole (through hole) in the second interlayer insulating film by dry etching using F ₃ and Ar gas
Was provided. In the peripheral circuit power supply line and ground line, the through holes 1 are arranged in an array so that the through hole / wiring overlap is 0.3 μm regardless of the wiring width.

After that, the above-mentioned through hole 1 is carried out as described above.
Was filled with W by a W deposition and etch back process, and a second layer wiring was formed by the same process as the first layer wiring. The wiring of the second layer has a width of 0.60 μm in the memory cell area, and the wiring width of the power supply line and the ground line of the peripheral circuit is 5 μm in the area connected to the wiring of the first layer. The wiring width is 10 μm in the region connected to the wiring of the layer and 20 μm in the other regions.

After the wiring of the second layer was processed, NSG was formed into a film of 8000 Å in the same manner as described above to form an interlayer insulating film of the third layer. A 0.50 μm through hole 2 is formed on the third interlayer insulating film by photolithography and dry etching.
Was provided. In the peripheral circuit power line and ground line, the through holes 2 are arrayed so that the wiring / through hole and the through hole / wiring overlap is 0.3 μm regardless of the wiring width when the wiring width is 5 μm and the wiring width is 10 μm. Placed in. A part of the through hole 2 in the peripheral circuit directly connects the wiring of the first layer and the wiring of the third layer through the interlayer insulating films of the second and third layers. In that case, the wiring / through hole overlap was also set to 0.3 μm regardless of the wiring width.

After that, the above-mentioned through hole 2 is formed as described above.
Then, W was embedded therein, and a wiring for the third layer was formed by the same process as the wiring for the second layer. The wiring of the third layer has a width of 0.80 μm on the memory cell area, and the wiring width of the power supply line and the ground line of the peripheral circuit is 10 μm in the area connected to the wiring of the second layer. In the region, the wiring is 100 μm wide. After that, 5000 Å of NSG and 3000 Å of SiN are formed by the CVD method,
It was used as a passivation film. Then, the pad was opened by dry etching to complete the device.

Comparative Example 1 In the peripheral circuit power supply line and ground line, the elements in which the wiring widths of the first, second and third wirings are the same at the connecting portions with the upper and lower wirings and at other places are used. , Was manufactured by the same process. The wiring width of the power supply line and the ground line of the peripheral circuit was set to 20 μm in the first layer, 20 μm in the second layer, and 100 μm in the third layer. Contact hole at the connection between the power line and the ground line of the peripheral circuit, through hole 1,
The through holes 2 were arranged in an array so that the overlap margin of the contact hole / wiring, the wiring / through hole and the through hole / wiring was 0.3 μm. When the above-mentioned overlap margin is taken, the outermost through hole of the through hole array is located outside the wiring after the wiring is etched.

Comparative Example 2 First layer in the power supply line and ground line of the peripheral circuit,
An element having the same wiring width in the second layer and the third layer as the connecting portion with the upper and lower wirings and in other places was manufactured by the same process. Wiring width is 20μm for the first layer and 20μ for the second layer
The third layer has a thickness of 100 μm. The arrangement of the contact hole, the through hole 1 and the through hole 2 at the connection portion of the wiring in the power supply line and the earth line of the peripheral circuit is UV.
In consideration of the thinning of the wiring due to the shrinkage of the resist during curing, the wiring / through hole and the through hole / wiring overlap margin was set to 3.0 μm and arranged in an array. Taking the overlap margin above,
Even after the wiring is etched, the through hole array is entirely located in the wiring. The yields of Example 1 and Comparative Examples 1 and 2 were evaluated. The results are shown in [Table 1].

[0032]

[Table 1]

The yield of Example 1 is higher than that of Comparative Example 1,
The yield was the same as that of Comparative Example 2 in which the overlap margin of the wide wiring / hole was made larger than that of the fine wiring. Comparative Example 1
The main cause of the decrease in yield is a short circuit between the semiconductor substrate and the third layer wiring via the through hole 2 arranged outside the wiring in the peripheral circuit. Therefore, as in Example 1 above,
In the connection portion of the wide wiring of the present invention, the wiring width is 10 μm.
By setting the following, it is possible to suppress the resist shrank by UV curing, and the yield is not reduced even if the overlap margin of the wide wiring / hole is set to the same level as the overlap margin of the fine wiring / hole. I understand.

Example 2 By the same process as in Example 1, an element having the following constitution was produced. The wiring of the first layer is 0.50 μm on the memory cell area
With respect to the width, in the power supply line and the ground line of the peripheral circuit, the region connected to the second layer wiring and the other regions are also wired with a width of 5 μm, and the second layer wiring is 0 in the memory cell region. The width of the wiring is 60 .mu.m, and in the power supply line and the ground line of the peripheral circuit, the wiring connected to the wirings of the first and third layers and the other areas are also arranged with the wiring width of 5 .mu.m. 0.80 on the cell area
An element having a width of 10 μm in a region connected to the second layer wiring in the power supply line and the ground line of the peripheral circuit and a width of 100 μm in other regions was manufactured.

The yield of Example 2 was 50%, and
It was confirmed that there is a similar effect to. Example 2
Was encapsulated in a plastic package and the life was measured. As a result, electromigration of the wirings of the first and second layers was suppressed, and it was found that the life was about 1.5 times that of Example 1.

Example 3 By the same process as in Example 1, an element having the following constitution was produced. The wiring of the first layer is 0.50 μm on the memory cell area
With respect to the width, in the power supply line and the ground line of the peripheral circuit, the region connected to the second layer wiring and the other regions are also wired with a width of 5 μm, and the second layer wiring is 0 in the memory cell region. The width of the wiring is 60 .mu.m, and the wiring connected to the wirings of the first and third layers in the peripheral circuit power supply line and the ground line and other areas are also wired with a wiring width of 5 .mu.m. 0.80 on the cell area
Wired in μm width, and 1 in areas other than the area connected to the second layer wiring in the power supply line and ground line of the peripheral circuit.
An element having a width of 00 μm and divided into 10 wirings having a wiring width of 10 μm only in the connection portion and the vicinity thereof was manufactured.

The yield of Example 3 was 62%.
It was confirmed that there is a similar effect to. In addition, Example 3
When the current capacity of the power supply line of the third layer wiring of the peripheral circuit was measured for the device of No. 3, it was found to be about 10 times that of Example 1.

Although all the holes are filled with W in the above Examples 1 to 3, after the film of the wiring material Al or Al alloy is formed, it is annealed at 400 to 600 ° C.,
There is no problem even if the holes are filled by improving the reflowability of the wiring material by sputtering at a high temperature.

[0039]

As is apparent from the above description, claim 1
According to the semiconductor device described in (1), U of the resist at the connection portion is
Shrinkage due to V-cure can be suppressed, and even if the overlap margin of wide wiring / hole is set to the same extent as the overlap margin of fine wiring / hole, there is an effect that the yield is not reduced. According to the semiconductor device of the second aspect, in addition to the effect of the first aspect, it is possible to prevent the wide wiring from being abruptly reduced at the connection portion, so that the disconnection of the wiring due to electromigration is suppressed. This has the effect of improving the long-term reliability and improving the life. According to the semiconductor device of the third aspect, in addition to the effect of the first or second aspect, there is an effect that the current capacity of the wiring is increased in the power supply line and noise is increased in the ground line.

[Brief description of drawings]

FIG. 1 is a plan view showing a configuration example of a semiconductor device according to the present invention.

FIG. 2 is a plan view showing another configuration example of a semiconductor device.

FIG. 3 is a plan view showing still another configuration example of the semiconductor device.

FIG. 4 is a graph showing the relationship between resist line width and resist receding amount.

FIG. 5 is a plan view showing a configuration example of a conventional semiconductor device.

[Explanation of symbols]

11, 12, 41, 42, 51, 52, 52a to 52c
Wiring 13, 43, 53a to 53c Holes W11, W12, W41, W42 Wiring width

Claims (3)

[Claims] 1. In a wiring which is vertically connected through a plurality of holes in an interlayer insulating film, a wiring width of a connecting portion is 10
A semiconductor device having a thickness of μm or less. 2. The semiconductor device according to claim 1, wherein, in the wiring, a wiring width of a connection portion of one wiring is equal to a wiring width of portions other than the connection portion. 3. The semiconductor device according to claim 1, wherein one wiring is divided into a plurality of wirings, and a width of a connection portion of each of the divided wirings is 10 μm or less.