JPH0547756A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a metallic wiring of a fine structure on a semiconductor device by a selective growth method. CONSTITUTION:The first metal film 2 and a dummy conductive layer are laminated on an insulating film 1 on a semiconductor substrate 10. Then this laminated body is etched into a form of wiring. Spacers 8 of insulator are formed on the sidewalls of the laminated body, and then the dummy conductive layer is removed by etching. Finally, the second metal film 6 is embedded in the region enclosed with the spacers 8 and the first metal film 2, forming an interconnection of a two-layer structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for forming metal wiring used in an integrated circuit.

[0002]

2. Description of the Related Art Electrode wiring technology is an important technology for electrically connecting each element formed on a semiconductor substrate such as silicon. The electrode wiring is required to have low resistance and high reliability, and aluminum or its alloy is usually used. However, as the current aluminum wiring, for example, an Al-Si-Cu alloy film using a TiN / Ti film as a base layer has a wiring resistance of about 3.
Since it is as high as 3 μΩcm, signal delay may occur in the integrated circuit formed on the semiconductor substrate, and development of a material having a lower resistance of about 1.7 μΩcm such as copper wiring is expected. Known methods for forming the electrode wiring include vacuum deposition, sputtering, and CVD. CVD is a method of forming a thin film by a chemical reaction in a vapor phase state, and is called thermal CVD, plasma CVD, or photo CVD depending on whether the reaction method is thermal, plasma chemical reaction, or photoexcitation. Conventionally, polysilicon has been used as a gate electrode material in particular, but it has a resistivity of 1000 μm no matter how much impurities are added.
There is also Ωcm, which has been a cause of signal delay due to wiring in the speeding up of LSI. Therefore, as a new gate electrode material and internal wiring, refractory metal silicides such as MoSi ₂ , WSi ₂ and TiSi _{2 having} a resistance lower than that of polysilicon by about one digit have been used. When silicide is used as a gate electrode, it is important that not only the resistivity is low, but also that it is thermally stable, resistant to oxidation, and resistant to chemicals.
It is necessary to create a stable MOS structure in terms of devices. However, since metal atoms penetrate or react into the gate oxide film to cause deterioration of breakdown voltage and increase in interface order, a silicide is formed directly on the gate oxide film to form a stable MOS structure. It is difficult. Therefore, TiS
When a silicide such as i ₂ is used for the gate electrode, a polysilicon film is often formed under the gate electrode to form a polycide structure.

A method of forming metal wiring used in a conventional semiconductor integrated circuit will be described with reference to FIGS. 7 and 8. For example, TiN is formed on the interlayer insulating film 1 such as BPSG or PSG formed on the n-type silicon semiconductor substrate 10.
A laminated metal film 2 of / Ti or the like is formed in the wiring planned region by a usual method. This metal film is used as a base layer of metal wiring to be formed later (FIG. 7a). Then, an interlayer insulating film 3 of a silicon oxide film is formed on the interlayer insulating film 1 including the metal film 2. The method is 300 ° C to 40 ° C.
Plasma CVD, which is performed at a relatively low temperature of 0 ° C., is used (FIG. 7b). Next, a PEP process is performed to form a groove 4 by anisotropically etching, for example, RIE so as to expose the metal film 2 by etching and opening the interlayer insulating film 3 (FIG. 8A). At this time, it suffices if the groove 4 is accurately formed on the metal film 2 using the resist pattern, but in reality,
Since the alignment accuracy and the processing accuracy with respect to the metal film are not sufficient, the groove 5 is formed on the side of the metal film 2 as shown in the drawing, and when the metal wiring covers the metal film 4, it becomes a void and its reliability is improved. Cause to lose. Therefore, conventionally, the metal film 2 is formed wider than the original width of the metal wiring to prevent the formation of the groove 5. Then, on the metal film 2,
A metal film such as an Al—Si—Cu film is selectively grown using the CVD method to form the metal wiring 6 (FIG. 8B).

[0004]

As described above, in the prior art, the width of the metal wiring is defined by the width of the groove 4 of the interlayer insulating film 3 formed on the metal film 2 as the underlayer. Therefore, fine processing is difficult. This is because, regardless of whether the light source for the exposure apparatus used for wiring processing is a g-line, an i-line, or an excimer laser, the resolution of the removal pattern is inferior to that of the remaining pattern. Further, as described above, the width of the metal film must be made wider than the width of the metal wiring in consideration of the alignment accuracy and the processing accuracy with respect to the metal film 4, which hinders the densification of the semiconductor device. If the width of the metal film 2 is adjusted to the metal wiring, the groove 5 is formed in the groove 4 due to the misalignment as described above, and a void is generated, which reduces the reliability of the semiconductor device. Also,
As mentioned above, as semiconductor devices such as ICs and LSIs are miniaturized, the cross-sectional area of the metal wiring becomes smaller. However, the size of the device chip does not change and tends to be larger, so that the wiring length becomes longer and the wiring resistance further increases accordingly. Moreover, the higher integration will further increase the complexity of the wiring layout. It is multilayer wiring that can cope with this, for example,
In the case of a three-layer wiring structure, the first layer is the wiring in the circuit block,
The second layer supplies wiring between circuit blocks, and the third layer supplies power to each circuit block. In addition to the wiring structure, selection of materials is important. At present, aluminum or its alloy is mainly used as a wiring material, but in the future, for example, copper and its alloy are promising as low resistance materials. However, copper is generally a material that is difficult to form as a thin film. First, since the etching process is difficult, it is necessary to use selective CVD like tungsten.
The present invention has been made under the above circumstances,
An object of the present invention is to provide a method for selectively forming fine and highly reliable metal wiring of a semiconductor device.

[0005]

According to the present invention, when selectively forming a metal wiring, a dummy conductive film is first provided in a wiring forming region surrounded by a spacer, and this conductive film is used as an original metal. It is characterized by replacing it with wiring. That is, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a first metal film on a semiconductor substrate, laminating a conductive film on the metal film, and etching the first metal film and the conductive film. Forming a wiring pattern made of the first metal film and the conductive film thereon, forming a spacer made of an insulating film on the sidewall of the wiring pattern, and forming the conductive film. The method is characterized by including a step of forming a groove in the side wall by etching and removing, and a step of providing a metal wiring by selectively forming a second metal film in the groove. The metal wiring, including a spacer made of the insulating film, is covered with an interlayer insulating film or a protective insulating film. After the step of providing the metal wiring on the semiconductor substrate by selectively forming the second metal film in the groove, W, A are formed on the exposed portion of the metal wiring.
It is also possible to apply a protective film selected from 1, Ti, and TiN. The first metal film is made of Ti, W, Nb, V,
A material selected from Mo, TiN, polysilicon, and a composite film of these can be used. Also, the second
A material selected from the metal film 1, Al, Cu and alloys thereof can be used. This second metal film is Cu
Alternatively, in the case of an alloy thereof, the first metal film is particularly preferably a material selected from W, Nb, Ti and polysilicon.

[0006]

Since the conductive film of the dummy provided on the side surface of the spacer is selectively removed by etching and the metal wiring is formed in that portion, a high precision and high accuracy can be achieved without increasing the extra dimension. A reliable metal wiring can be formed.

[0007]

Embodiments of the present invention will be described below with reference to FIGS. First, the first embodiment will be described with reference to FIGS. For example, the insulating film 1 is coated on the silicon semiconductor substrate 10 in which an active region such as an integrated circuit is formed. For the insulating film 1, for example, a BPSG film is used. This insulating film 1
A metal film 2, for example, a Ti film is deposited on the upper surface of 500 angstroms.
Deposition by a well-known technique such as sputtering (hereinafter referred to as A). For example, an amorphous Si film 7 is formed on the metal film by low temperature plasma CVD to 400
About 0 to 6000 A is deposited (FIG. 2a). These are patterned by etching to form the first metal film 2 and the dummy conductive film 7 on the first metal film 2 in the region where the metal wiring is to be formed. The first metal film 2 is a base layer and is used as an adhesion layer for improving the adhesion (FIG. 2b). Then, for example, a Si ₃ N ₄ film of about 1000 A is deposited on the insulating film 1, the metal film 2 and the dummy conductive film 7,
By anisotropic etching such as IE, the metal film and the dummy are damaged.
The other part is removed, leaving the part attached to the side surface of the conductive film. The remaining Si ₃ N ₄ film 8 is used as a spacer surrounding the wiring (FIG. 3a). Next, the dummy conductive film 7 is removed by etching to form a groove 9 surrounded by a spacer 8 (FIG. 3).
b). Finally, a Cu film 6 is formed in the groove 9 as a second metal film.
Are grown by selective CVD. The Cu film is, for example, Cu
It is formed by reacting bishexafluoroacetylacetonate copper represented by (HFA) ₂ . Of course, other reaction gases can be used. The spacer 8 prevents the Cu film 6 from growing unduly in the lateral direction when growing.

The wiring is formed in this way, and a protective film is formed on this. If a multi-layered wiring is to be formed, an interlayer insulating film is further applied thereon, and then an upper wiring is provided. For example, if the illustrated wiring is a first layer wiring, a second layer of wiring between circuit blocks is formed thereon, and if it is a second layer wiring, a third layer of power supply wiring to each circuit block is formed. At present, an integrated circuit mainly composed of a memory has two layers in many cases, and in the case of logic, many circuits have three layers or more. Since the first metal film is used as the underlayer, it is chemically stable and is selected from a material that does not cause an unnecessary reaction with the base material such as an insulating film that supports the first metal film and the second metal film thereon. Be done. For example, Ti, W, N
b, V, Mo, polysilicon, etc., and Ti
In some cases, it may have a laminated structure like an N / Ti film. The second metal film is selected from materials having low resistance, and for example, Al and its alloy, Cu and its alloy, etc. are used. For the first metal film, the above materials are not arbitrarily selectable,
It is determined by the combination with the second metal film which is the main material of the metal wiring. As mentioned above, for Al,
Polysilicon for Ti, TiN / Ti, Cu,
W, Nb, etc. are suitable. The dummy conductive film is not limited to the amorphous Si illustrated in the embodiment, but a material such as aluminum can be used. In addition,
The silicon is not limited to the Si ₃ N ₄ film and may be a SiO ₂ film.
Since the present invention is a kind of buried wiring forming method for selectively forming metal wiring in a spacer provided on the side surface of a wiring planned area, it does not involve a large process change as in the conventional method, and Since it is not necessary to consider the misalignment between the wiring groove and the underlying layer, this is a highly feasible method. Further, since the CVD is selectively used, it is possible to apply a Cu film or the like which has a low resistance and has a future prospect but is difficult to process. Therefore, it is useful as a method for manufacturing a next-generation highly reliable wiring.

Next, a second embodiment will be described with reference to FIG. In this embodiment, the metal wiring of the present invention is applied to an LSI such as an inverter having a CMOS structure. First, the n-type silicon semiconductor substrate 10 is used as the semiconductor substrate. The conductivity type of the semiconductor substrate may basically be either, unless there is a special reason. Next, both regions of the p well 11 and the n well 12 are formed in the semiconductor substrate 10. For example, boron is ion-implanted in the p-well and phosphorus is ion-implanted in the n-well. After this ion implantation is completed, the semiconductor substrate is heat-treated at a high temperature of 1100 ° C. or higher to a depth of 3-6.
A well region of about μm is formed. Then, an element isolation region is formed. Element isolation is a step of electrically isolating elements from each other and is important in determining element density. Here, the most commonly used LOCOS method is used.
A thin thermal oxide film 13 is formed on the semiconductor substrate 10, and a Si ₃ N ₄ film is formed on this by a CVD. Next, this is patterned by lithography and etching techniques to leave the Si ₃ N ₄ film only in the element region, and the semiconductor substrate 10 is thermally oxidized at about 1000 ° C. in a wet oxygen atmosphere. Since Si ₃ N ₄ is not oxidized, it is selectively oxidized only when the Si ₃ N ₄ film is removed, and the element isolation oxide film 13 is formed around the element region. The remaining S
The i ₃ N ₄ film is removed. Next, a gate oxide film is formed. First, the thin oxide film covering the surface of the element region is removed by etching, and a thermal oxide film 14 having a thickness of, for example, about 200 A is formed on the exposed surface of the silicon semiconductor substrate, and this is used as a gate oxide film.

Next, a gate electrode is formed. The gate electrode material is at the same time as the gate electrode of the MOS transistor,
Since it is also used as a wiring such as a word line of a memory, it must also have a low resistance. Polysilicon, which has been used for a long time, has a resistivity of about 0.001 Ωcm even if the maximum amount of impurities is added.
The layer resistance at a film thickness of 0.3 to 0.5 .mu.m, which is easy to use as a gate electrode, is 20 to 30 .OMEGA. / Squere, which is one of the causes of the wiring delay caused by the miniaturization of semiconductor devices. Therefore, silicide of refractory metal has come to be used as a new electrode material. For example, M
oSi ₂ , WSi ₂ , TiSi _2, etc. are an order of magnitude smaller than the conventional specific resistance. However, an important condition for the gate electrode is to realize and sell a stable MOS structure. In that respect, since polysilicon brings about the most stable MOS structure, it is often a laminated structure with polysilicon even when silicide is used. Also in this embodiment, the gate electrode having the above-mentioned laminated structure is used. Polysilicon to be a gate electrode is formed by CVD. Then, the gate electrode portion is patterned with a resist by a lithographic technique and then etched by using RIE or the like to form a gate electrode 15. For the polysilicon film 15, a CVDSiO ₂ side wall is used to make the MOS transistor have an LDD structure.

Then, a source / drain region is formed. In the p well 11, the n ⁺ layer 16 is formed as the region,
For example, it is formed by ion implantation of As. n-well 1
A p ⁺ layer 17 is formed in the region in ₂ by ion implantation of B or BF ₂ , for example. After that, a Ti thin film is deposited on the entire surface of the semiconductor substrate, and is silicidized by heating at an appropriate temperature to form a TiSi ₂ film 18 on the gate electrode 15 and the source electrode 15.
Formed on the drain / srain regions 16 and 17. Oxide film 1
The non-silicided Ti thin film on 3 is removed by etching. The gate electrode on the semiconductor substrate 10 is eventually composed of a laminated structure of the polysilicon film 15 and the TiSi ₂ film 18. The gate electrode has a thickness of 0.2 to 0.
It is about 3 μm and its length is about 0.3 to 0.5 μm. Then, the gate electrode and the oxide film are covered with the insulating film 1. The insulating film 1 is composed of a CVDSiO ₂ film deposited to a thickness of about 0.2 to 0.3 μm and a BPSG film formed thereon to a thickness of about 0.5 to 0.7 μm.
In general, the surface of the insulating film formed on the element has irregularities due to the influence of the step shape of the lower portion. These irregularities cause non-uniformity in the thickness of the photoresist and non-uniformity in the resolution during exposure in the lithography process for fine contact holes and metal wiring in the next process. Therefore, a flattening technique is required for smooth metal wiring. Here, BPSG containing phosphorus and boron in high concentration for flattening
The reflow method is used, which utilizes the property that the fluidity of the film surface increases when exposed to the high temperature atmosphere of the film. That is, after depositing the BPSG film, a heat treatment at about 800 ° C. is performed to planarize the surface. Metal wiring is formed on the flattened insulating film 1 by the manufacturing method of the present invention. First, contact holes reaching the gate electrode and the source / drain regions are formed in the insulating film 1 in order to achieve electrical connection. The size of the contact opening is 0.6μ as the device shrinks.
It has a fine dimension of about m × 0.6 μm. The opening is performed by using the lithography technique and the etching technique.

Then, a metal 1 is embedded in the contact hole.
Fill 9. Here, the refractory metal W is selected by CVD.
However, other than this, TiN, Al, polysilicon, or the like is used. The embedded metal of W is, for example, WF
It is formed by the reaction of ₆ + SiH ₄ based gas. The material of the embedded metal is determined mainly in consideration of the compatibility with the underlying layer of the metal wiring thereabove, which is in contact with the embedded metal. The metal wiring of the first layer is formed on this insulating film 1 and
9 is also in contact with the first metal film 2 made of a Ti film
And a second metal film 6 made of a Cu film or an Al film formed thereon by selective CVD and a spacer 8 surrounding the side walls of these metal films. In this figure,
The metal wiring of the first layer is connected to the source / drain region 16 in the p well 11 and the gate electrode in the n well 12 via the buried W19 in the contact hole. Next, the first metal wiring is covered with the interlayer insulating film 21. This interlayer insulating film is preferably formed at a temperature as low as possible so that the metal wiring is not damaged by high temperature. This embodiment utilizes plasma CVD to perform low temperature formation, and at the same time, LPD (Liquid Phase)
Deposition) film is used. This film consists of SiO ₂ deposited from a hydrofluoric acid solution in which silica is in a supersaturated state and can be formed at room temperature. It is a potential material because it has good adhesion to other films and high insulation, but it requires aluminum or aluminum for the metal wiring to raise the temperature or to bring the solution into a supersaturated state. In that case, another insulating film must be interposed. In this example, the plasma CVD SiO ₂ film is interposed as described above. That is, as shown in FIG. 5, the LPDSiO ₂ film is sandwiched between the plasma CVD films to form the interlayer insulating film 21. The plasma CVD SiO ₂ film is obtained by thermal decomposition of TEOS, for example,
Since it is formed at a relatively low temperature of 0 ° C. to 400 ° C., the interlayer insulating film 21 is formed at a low temperature and does not damage the metal wiring. First, the insulating film 1 and the second metal film 6 of the first-layer metal wiring are, for example, plasma C having a thickness of about 5000A.
It is almost completely covered with the VD film 211. An LPDSiO ₂ film 212 having a thickness of about 4000 A is formed thereon.
This has a low deposition rate but gives a dense film. On top of this, also plasma CVD SiO _{2 of} about 5000 A thick
The film 213 is formed.

By the way, the spacer 8 formed on the side wall of the metal wiring may be removed after the metal wiring is formed since it is not necessary, but it is better to leave it as it is because the number of removing steps increases. However, if this material has a high dielectric constant such as Si ₃ N ₄ , the parasitic capacitance becomes large. Therefore, if such a state is disliked, it is better to remove it even if the number of steps is increased. A second-layer metal wiring is formed on this interlayer insulating film 21. The metal wiring of the second layer is the first metal wiring considering the ease of the manufacturing process.
The same material as the first layer is used. The two metal wirings are connected to each other through the W-embedded metal 19 embedded in the contact hole formed in the interlayer insulating film 21. Second
The metal wiring of is covered with the interlayer insulating film 31. The interlayer insulating film 31 is the interlayer insulating film 2 formed thereunder.
It is formed by the same method as 1. On this interlayer insulating film 31, a third-layer metal wiring having the same composition as the lower-layer metal wiring is provided. The second-layer and third-layer metal wirings are also the interlayer insulating film 3.
They are connected to each other through the W-buried metal 19 in the contact hole provided in No. 1. In this embodiment, since three layers of multi-layered wiring are used, the wiring process is completed, and the surface of the semiconductor substrate including the third layer of metal wiring is formed of PSG film or plasma nitride film (not shown). It is protected by such a passivation film 41. In the case of a multi-layered wiring having three or more layers, metal wiring may be stacked with an interlayer insulating film interposed.

Next, referring to FIG. 6, as another embodiment of the present invention, a metal wiring having a structure different from that of the previous embodiment will be described. The feature of this example is that after the metal wiring is formed in the underlayer, the wiring is protected by the protective film before the interlayer insulating film and the passivation film are subsequently applied. This is necessary to protect the wiring from natural oxidation during the manufacturing process. In the figure, when the spacer 8 is left on the side wall of the wiring (FIG. 6a), the protective film 61 is
It is formed only on the surface of the wiring. However, when the spacer 8 is to be removed (FIG. 6b), the protective film 61 must be formed also on the side wall thereof. That is, all exposed parts must be covered. In the case of the aluminum wiring 6, the oxidation progresses to a certain extent and does not proceed further, but when copper is used for the wiring 6, it is endlessly oxidized and finally a step line is recognized. The protective film 61 has several hundred
The thickness is about A, and W is used as the material. Any material may be used as long as it prevents oxidation of copper or the like, but Al, Ti, TiN or the like is also used. Since the protective film is formed by using CVD, it must be formed by CVD and must prevent the oxidation of the wiring.

As the elements in the semiconductor device are miniaturized, the internal electric field becomes higher, which causes electrons flowing from the source to the drain to be accelerated by the strong electric field to obtain a large amount of energy. The carrier at this time is called a hot carrier, and an electron-hole pair is created by impact ionization at this time. When hot carriers enter the gate oxide film, they cause a change in the threshold value of the transistor and a change in the mutual conductance, which deteriorates the characteristics of the element such as the transistor. In order to solve this problem, the electric field near the drain is relaxed. As shown in FIG. 6, a structure in which a region (n ⁻ layer) having a low impurity concentration in contact with the drain region is formed between the gate electrode and the drain region (n ⁺ layer) to relax the electric field near the drain. Can be achieved. This structure is LDD (Lightly Doped Drai)
n) known as structure, which can improve breakdown voltage.

[0016]

Since the method of forming the metal wiring of the semiconductor device of the present invention uses a kind of buried wiring method which does not rely on the etching process for the wiring pattern, it does not involve a large process change as compared with the conventional method, and There is no misalignment between the wiring groove and the underlying layer, which is highly feasible. In addition, choices will be broader, such as the ability to use previously unwieldy materials such as copper.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to the present invention.

FIG. 2 is a sectional view of a manufacturing process of a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view of the manufacturing process of the semiconductor device of the present invention.

FIG. 4 is a sectional view of a semiconductor device having a CMOS structure according to the present invention.

5 is an enlarged cross-sectional view of a main part of FIG.

FIG. 6 is a sectional view of a semiconductor device according to the present invention.

FIG. 7 is a sectional view of a conventional semiconductor device manufacturing process.

FIG. 8 is a sectional view of a conventional semiconductor device manufacturing process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Insulating film 2 1st metal film 3 Interlayer insulating film 4 Groove 5 Groove 6 2nd metal film 7 Dummy conductive film 8 Spacer made of an insulating film 9 Groove 10 Semiconductor substrate 11 p-well 12 n-well 13 Oxidation Film 14 Thermal oxide film 15 Gate electrode 16 n + layer 17 p + layer 18 TiSi ₂ film 19 Embedded W 21 Interlayer insulating film 31 Interlayer insulating film 41 Passivation film 61 Protective film 211 Plasma CVD SiO ₂ film 212 LPDSiO ₂ film 213 Plasma CVD SiO ₂ film

Claims (7)

[Claims] 1. A first metal film is formed on a semiconductor substrate,
A step of laminating a conductive film on the metal film; a step of etching the first metal film and the conductive film to form a wiring pattern made of the first metal film and the conductive film thereon. A step of forming a spacer made of an insulating film on a side wall of the wiring pattern, a step of forming a groove in the side wall by removing the conductive film by etching, and a second metal in the groove. And a step of selectively forming a film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the metal wiring is covered with an interlayer insulating film or a protective insulating film together with a spacer made of the insulating film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the second metal film is made of Cu or its alloy. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the first metal film is selected from W, Nb, Ti and polysilicon. 5. A protective coating is applied to the exposed portion of the metal wiring after the step of providing the metal wiring on the semiconductor substrate by selectively forming a second metal film in the groove. The method for manufacturing a semiconductor device according to claim 1, wherein the method is for manufacturing a semiconductor device. 6. The protective coating is W, Al, Ti, Ti
6. A material selected from N. 6.
A method of manufacturing a semiconductor device according to item 1. 7. The first metal film comprises Ti, W, Nb,
2. The manufacturing of a semiconductor device according to claim 1, wherein the second metal film is selected from V, Mo, TiN, polysilicon and a composite film thereof, and the second metal film is selected from Al, Cu and an alloy thereof. Method.