JPH0955424A - Method of forming multilayer interconnection - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the dielectric strength of an insulating film separating an intermediate layer wiring from an upper layer wiring while avoiding the chipping of an offset SiOx film and the first sidewall in case of making a contact hole in the formation of self-align contact. SOLUTION: Impurity containing polysilicon film 9 is used as an etching stopper film in the case of making a contact hole 14 in an interlayer insulating film 10. At this time, the underneath selectivity in the case of anisotropical etching step of the interlayer insulating film 10 and the impurity containing polysilicon film 9 can be improved compared with the conventional example using an SixNy film as the etching stopper film. After the completion of the etching step, sidewall type sealing patterns 15sw made of SiOx film are formed like covering the processed ends 9a of the conductive impurity containing polysilicon film 9 so as to avoid the conduction to a bit wire leading out electrode to be buried in the contact hole in the latter step.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to a method of forming a multi-layer wiring adopted in a highly integrated semiconductor device such as a memory or a gate array, and particularly, a so-called self-aligned contact structure is formed with high accuracy. Regarding the method.

[0002]

2. Description of the Related Art In recent highly integrated semiconductor devices such as VLSI and ULSI, the area occupied by the wiring portion on the chip is increasing, and this tendency is particularly noticeable in memories and gate arrays. In such devices, there is a limit to reducing the chip area only by reducing the wiring interval, and the problem is solved by using multilayer wiring in which wiring is stacked in multiple layers in the vertical direction with an insulating film interposed. I am trying to

In multi-layer wiring, there are many cases in which connection holes are formed between the wirings. For example, when there are three wiring layers, that is, a lower layer wiring, a middle layer wiring, and an upper layer wiring, a connection hole reaching the lower layer wiring by opening the interlayer insulating film in the inter-wiring space between two adjacent middle layer wirings. This corresponds to the case where the lower layer wiring and the upper layer wiring are electrically connected by forming a conductive material in the connection hole. Here, the distance between the middle layer wiring and the connection hole is designed in consideration of the following scaling factor. (A) Distance required to insulate the middle-layer wiring from the connection hole (b) Overlap margin between the connection hole pattern and the middle-layer wiring pattern (c) Variation in processing of connection hole diameter and wiring width (a) Is substantially a function of the dielectric constant and the film thickness of the interlayer insulating film that separates the intermediate wiring from the conductive material in the contact hole. The above (b) is an overlap that may occur with respect to a connection hole that should originally fit within the inter-wiring space of the middle layer wiring when forming a photoresist mask for opening the connection hole in the interlayer insulating film that covers the middle layer wiring. This is a tolerance for misalignment. Indicates a position shift. Further, (c) above is related to the dimension conversion difference with the photoresist mask due to the etching conditions.

However, these scaling factors are not always ones that can be easily scaled down in parallel with the reduction of design rules, and this leads to reduction of the space between wirings, and consequently memory cells and gates.
This is a cause of hindering the reduction of the area occupied by the array. In particular, the overlay margin in the photolithography in (b) is more difficult to scale down than other items, and if the overlay error becomes large, a short circuit occurs between the middle layer wiring and the connection hole, or the lower layer wiring is MOS-FE
In the case of the T source / drain region, there arises inconvenience that the connection hole reaches the LDD region and the operating characteristics are deteriorated.

Therefore, as a method for solving the above problem, a so-called self-aligned contact (SAC) structure has been proposed in which a connection hole is formed in a self-aligning manner even if the space between wirings is reduced. FIG. 16 shows a part of an SRAM memory cell to which this structure is applied. Here, in a contact hole 43 formed between two word lines 35 (gate electrodes of MOS-FET) made of a tungsten polycide film (W-poly), a bit line lead electrode made of an Al-based alloy film. S is provided at a portion where 44 contacts the source / drain region 38.
AC structure is adopted. The source / drain region 38, the word line 35, and the bit line extraction electrode 44 correspond to the lower layer wiring, the middle layer wiring, and the upper layer wiring, respectively.
The W-poly film is a film in which the impurity-containing polysilicon film 33 and the WSix film 34 are sequentially stacked from the lower layer side.

An offset SiOx film 36 is formed on the upper surface of the word line 35 in the same pattern as that of the word line 35, and a sidewall 37 made of SiOx is also formed on the side wall surfaces of the word line 35 and the offset SiOx film 36. ing. Here, the offset oxide film 36 and the sidewall 37 contribute to the insulation between the word line 35 and the bit line extraction electrode 43.

[0007]

In the SAC structure as described above, it is important to secure the breakdown voltage between the middle layer wiring and the upper layer wiring, but conventionally, as shown in FIG. 15, the offset SiOx film 36 is formed. However, there is a problem that the film thickness is partially reduced and the breakdown voltage easily deteriorates. This is due to the method of forming the SAC structure. A conventional general forming method will be described with reference to FIGS. 14 and 15.

FIG. 14 shows a gate S on a silicon substrate 31.
After the iOx film 32 is formed, the offset SiOx film 36 and the word lines 35 are collectively patterned, and the sidewalls 37 are formed, a thin etching stopper film 3 is formed on the entire surface of the wafer.
9 shows a state in which the entire surface of the wafer is substantially flattened by the interlayer insulating film 40 and the resist pattern 41 is formed thereon. Here, as the interlayer insulating film 40, for example, a BPSG (boron phosphorus silicate glass) film having excellent planarization characteristics is used.

It is to be noted that the contact hole 43 is used to temporarily flatten the surface of the substrate by the interlayer insulating film 40.
This is because a resist pattern that will serve as a mask when the bit line extraction electrode 44 is etched is accurately formed by photolithography.

The reason why the opening diameter of the opening 42 of the resist pattern 41 is larger than the inter-wiring space of the word line 35 is that the misalignment of the contact holes 43 is expected.

When the contact hole 43 is formed in such a wafer structure, excessive over-etching is required to etch the interlayer insulating film 40 having a large local variation in film thickness. The etching stop film 39 is an indispensable film for protecting the offset SiOx film 36 and the sidewalls 37 during this over-etching, and is usually composed of a SixNy-based material film.

However, in dry etching, it is generally difficult to perform selective etching between SiOx and SixNy. This is Si-O bond and Si-N
This is because the interatomic bond energies of bonds are relatively close to each other, and basically the same etching species can be used for etching. Moreover, etching of a SiOx-based material such as BPSG requires a large ion incident energy, and it is basically difficult to secure the underlayer selectivity. For this reason, it is extremely difficult to completely stop the etching of the interlayer insulating film 40 on the etching stop film 39, and normally, as shown in FIG. 15, the offset SiOx film 36 and the sidewall 37 are greatly eroded. .

In order to solve this problem, it seems that the film thickness of the offset insulating film 36 should be increased.
In reality, further increase in film thickness has reached an unacceptable level. That is, the film thickness of the offset insulating film 36 is (d) the film thickness variation during the film formation by CVD (e) the film thickness decreases when the sidewalls 37 are formed by etch back (f) the contact between the interlayer insulating film 40 and Film reduction due to over-etching when opening the hole 43 (g) Design is made in consideration of scaling factors such as film reduction during dilute hydrofluoric acid treatment (removal of natural oxide film) immediately before the upper layer wiring 44 is deposited However, even under the present circumstances, the value is much larger than the film thickness of the word line 35, and it is the actual situation that further increase of the step difference is unacceptable.

Therefore, the present invention solves such a problem by
It is an object of the present invention to provide a method for forming a multi-layered wiring that can secure the dielectric strength of an insulating film that separates a middle layer wiring and an upper layer wiring in an AC structure.

[0015]

As described above, since it is impossible to increase the film thickness of the offset insulating film, it is necessary to improve the withstand voltage of the insulating film between the middle layer wiring and the upper layer wiring in the SAC structure by improving the etching stop film. It is necessary to realize it by improving its own etching resistance. From this viewpoint, the present invention uses a conductive material film as the etching stop film instead of the conventional insulating film. The conductive material film used in the semiconductor process is typically a silicon-based material or an aluminum-based material. These films are usually SiOx, S
As is clear from the fact that patterning is performed on the insulating film made of ixNy or the like, it is possible to sufficiently secure the selection ratio with respect to the insulating film.

However, since this conductive material film is not a film that is finally used as a wiring film, after it has served as an etching stop film, it is separated from the conductive material that will be deposited in the connection hole in a later step. It is necessary to take measures to prevent electrical continuity. In the present invention, as a countermeasure against this, either (h) the processed end surface of the etching stop film is covered with an insulating sealing pattern. (I) The vicinity of the processed end surface of the etching stop film is modified into an insulating film.

As a concrete method of the measure (h), an insulating film may be deposited on the entire surface of the substrate and then anisotropically etched back. As a result, the sealing pattern is formed in a sidewall shape.

On the other hand, as a concrete method of the countermeasure (i), either (i-1) reforming is performed by annealing in an oxygen atmosphere, or (i-2) reforming is performed by oxygen ion implantation. is there. However, when the measure (i) is taken, unlike the case of the measure (h), it is necessary that the lower layer wiring cannot be affected by annealing or ion implantation.
Therefore, a protective insulating film is formed in advance under the etching stop film, and annealing or ion implantation is performed with the protective insulating film left on the surface of the lower wiring. When the protective insulating film is removed after the modification is completed, the connection hole is completed.

[0019]

In the present invention, in the formation of SAC, a conventional insulating film is used as an interlayer insulating film, and a conductive material film is used as an etching stop film. Insulation film) / Six
A high selection ratio is achieved as compared with the Ny (etching stop film) laminated system, thereby preventing a decrease in film thickness of the offset insulating film and the first sidewall. Here, the word "first" is attached to the notation of the side wall formed on the side wall surface of the middle layer wiring as a specific method of the above countermeasure (h): (overall deposition) + (etch back). This is because the encapsulation pattern formed in the case of is also sidewall-like, so that they are distinguished from each other.
Note that, when the measure (i) is taken, no new side wall is generated except the side wall of the side wall of the middle layer wiring, but for convenience of explanation, this side wall is also referred to as "first". I will decide.

The interlayer insulating film is made of SiOx or Si.
It can be configured using at least one of xNy. These compounds do not necessarily have to have a stoichiometric composition. For example, SiOxFy in which a predetermined amount of F is contained in SiOx for the purpose of lowering the dielectric constant may be used.

On the other hand, as a conductive etching stop film which can have an etching selection ratio with respect to this interlayer insulating film,
For example, impurity-containing polysilicon film, WSix film, Si
Silicon-based material film such as OxNy film or Al-Si
An Al-based material such as an alloy, an Al-Cu alloy, or an Al-Si-Cu alloy can be used.

Since this etching stopper film is also a film that is selectively removed in the contact hole, the offset insulating film and the first sidewall, which serve as the etching base, are subject to the etching conditions for the etching stopper film. The film must be resistant to it. Therefore, it is preferable that the offset insulating film and the first sidewalls are made of at least one of SiOx and SixNy, like the interlayer insulating film. Also when the protective insulating film is provided below the etching stop film, it is convenient to use at least one compound selected from SiOx, SixNy, or AlOx for the same reason.

The annealing in the oxygen atmosphere, which is carried out in the above countermeasure (i-1), can be carried out by a conventionally known method. For example, if the etching stopper film is a silicon-based material, ordinary pyrogenic oxidation is carried out. be able to.
On the other hand, the oxygen ion implantation performed as the countermeasure (i-2) is
Since it is necessary to oxidize the anisotropically machined end face, it is preferable to perform the oblique rotation ion implantation.

[0024]

The preferred practical examples of the present invention will be described below.

Embodiment 1 This embodiment is an example in which the present invention is applied to a process of forming a multi-layer wiring in which a bit line extraction electrode is brought into contact with a substrate between two word lines in an SRAM memory cell, The impurity-containing polysilicon film was used as an etching stopper film, and its processed end face was covered with a sidewall-shaped insulating sealing pattern. The process of this embodiment will be described with reference to FIGS.

First, as shown in FIG. 1, the surface of the Si substrate 1 on which the wells have been formed and the elements have been separated in advance is thermally oxidized,
A gate oxide film 2 having a thickness of about 8 nm was formed. This thermal oxidation was formed by carrying out pyrogenic oxidation at 850 ° C. using a H ₂ / O ₂ mixed gas, for example. Subsequently, a W-polycide (W-poly) film, which is a laminated body of the impurity-containing polysilicon film 3 with a film thickness of about 70 nm and the WSix film 4 with a film thickness of about 70 nm, is formed, and the film thickness is further reduced by CVD under this condition. An offset SiOx film 6 of about 170 nm was deposited. Here, the WSix film 4 is formed of WF ₆
/ SiCl ₂ H ₂ mixed gas, depressurized CV at 680 ° C
A film was formed by performing D. Further, the impurity-containing polysilicon film 3 uses a SiH ₄ / PH ₃ mixed gas,
The n ⁺ -type amorphous Si film formed by performing the low pressure CVD at 550 ° C. was formed by growing crystal grains by the heat load during the CVD of the above-mentioned WSix film 4.

Next, a resist mask (not shown) is formed on the offset SiOx film 6, and the offset S is formed.
The iOx film 6, the WSix film 4, and the impurity-containing polysilicon film 3 were anisotropically etched. This anisotropic etching can be performed collectively under common conditions for all three types of films using, for example, a magnetic field microwave plasma etching device and a Cl ₂ / O ₂ mixed gas, but It may be performed by sequentially switching the optimum etching conditions for the film. By this etching, as shown in the figure, the word line 5 in which the offset SiOx film 6 was laminated in the same pattern was formed. This word line 5
Has a line width of about 0.55 μm and the space between wires is about 0.7 μm
m.

Next, low-concentration As ⁺ ion implantation for LDD region formation was performed on the Si substrate 1 using the offset SiOx film 6 as a mask. The ion implantation conditions at this time are
For example, ion acceleration energy of 20 keV and dose of 6
It was set to × 10 ¹³ / cm ² . Subsequently, a SiOx film having a film thickness of about 150 nm was formed on the entire surface of the wafer by a low pressure CVD method, and this was anisotropically etched back. This allows
First sidewalls 7 as shown in FIG. 2 were formed on the side wall surfaces of the word lines 5 and the offset SiOx film 6. Next, using the first side wall 7 and the offset SiOx film 6 as a mask, high-concentration As ⁺ ion implantation (ion acceleration energy of 20 keV, dose amount of 5 ×) is performed.
10 ¹⁵ / cm ² ) and further RTA (Rapid Thermal Annealing) at 1050 ° C. for 10 seconds to activate the impurities (As) to form the source / drain regions 8 having the LDD structure.

Next, as shown in FIG. 3, impurity-containing polysilicon 9 is formed as a thin and conformal etching stop film on the entire surface of the wafer to a thickness of about 150 nm, and then the entire surface of the wafer is substantially flattened. Then, a thick interlayer insulating film 10 was deposited. The conditions for forming the impurity-containing polysilicon film 9 were the same as the conditions for forming the impurity-containing polysilicon film 3 in the W-poly film described above. Further, the interlayer insulating film 10 is formed by performing atmospheric pressure CVD at 400 ° C. using SiH ₄ / B ₂ H ₆ / PH ₃ mixed gas.
A BPSG (boron phosphorus silicate glass) film deposited to a thickness of 0 to 1000 nm was reflowed under an annealing condition of 850 ° C. for 30 minutes.

Next, as shown in FIG. 4, photolithography was performed to form a resist pattern (PR) 11 having an opening 12 following the contact hole pattern on the interlayer insulating film 10. The photolithography was performed using a chemically amplified positive photoresist material and a KrF excimer laser stepper as an example.
Since the surface of the interlayer insulating film 10 was substantially flattened in advance, the film thickness of the resist coating film could be made substantially uniform and relatively thin over the surface of the substrate, so that the resolution characteristics were extremely good.

Next, as shown in FIG.
The interlayer insulating film 10 exposed in 2 is anisotropically etched,
The opening 13 was formed. This anisotropic etching is performed by using, for example, a magnetron RIE apparatus under the following conditions: C ₄ F ₈ flow rate 20 SCCM CO flow rate 150 SCCM Ar flow rate 150 SCCM pressure 10 Pa RF source power 1000 W (13.56 MHz) magnetic field The strength was 6.5 T, and the wafer temperature was 10 ° C. This gas system is C for the interlayer insulating film 10.
Although there is an effect of increasing the etching rate by extracting O atoms from the film by the O gas, CO gas traps F * (fluorine radical) on the exposed surface of the impurity-containing polysilicon film 9 to which O atoms are not supplied. Shows the effect of lowering the etching rate. That is, since the selection ratio to the impurity-containing polysilicon film 9 is high, the interlayer insulating film 1
Even if the portion corresponding to the maximum film thickness of 0 is etched, if the etching stopper film 9 is exposed, the etching does not proceed any further.

Further, as shown in FIG.
The etching stop film 9 exposed on the bottom surface of the film was removed by dry etching to complete the contact hole 14.
This anisotropic etching is performed by, for example, magnetron RIE.
The apparatus was used under the conditions of SF ₆ flow rate 20 SCCM pressure 20 Pa RF source power 800 W (13.56 MHz) magnetic field strength 6.5 T wafer temperature 10 ° C. In the conventional process using the SixNy film as the etching stopper film, the offset SiOx film 6 and the first sidewall 7 were often eroded at this point (see FIG. 15). However, in this embodiment, since the impurity-containing polysilicon film 9 is used as the etching stopper film, a high selection ratio is maintained for the SiOx-based material film,
Little such erosion occurred. Moreover, since the impurity-containing polysilicon film 9 is thin, the amount of overetching is small, and the erosion of the underlying source / drain regions 8 can be suppressed to a level without any problem. At this point, the processed end surface 9a of the conductive impurity-containing polysilicon film 9 is still in contact hole 1
4 is exposed.

Therefore, the process for forming an insulating sealing pattern for covering the processed end surface 9a will be described below. First, ordinary O ₂ plasma ashing was performed to remove the resist pattern 11. Subsequently, as shown in FIG. 7, plasma CVD using TEOS (tetraethoxysilane) as a source gas is performed to form a wafer with a thickness of about 5
A 0 nm SiOx film 15 was deposited. Further, the above S
The iOx film 15 was anisotropically etched back under the same conditions as the above-described etching of the interlayer insulating film 10 to form a sidewall-shaped sealing pattern 15sw as shown in FIG. This prevents conduction between the etching stop film and the upper wiring.

After that, the bit line extraction electrode 16 was formed by a conventional method. This bit line extraction electrode 1
6 is, for example, a Ti-based barrier metal in which a Ti film and a TiN film are sequentially stacked by a sputtering method, and further Al
This is a film obtained by patterning a film in which -1% Si film 14 is laminated by a sputtering method.

In the present invention, both the offset SiOx film 6 and the first sidewall 7 are maintained to have a sufficient thickness, so that the insulation between the bit line extraction electrode 16 and the word line 5 is good. The sealing pattern 15sw includes
This also has the effect of making the cross-sectional shape of the contact hole 14 gentle, which improves the coverage of the bit line extraction electrode 16 and improves the reliability of the SRAM.

Embodiment 2 In this embodiment, a WSix film is used as an etching stop film in the process of forming a memory cell of SRAM. Since this process is almost the same as the process described in the first embodiment except that the WSix film 17 having a thickness of about 150 nm is used instead of the impurity-containing polysilicon film 9, only the essential points will be described below.

First, in the anisotropic etching process of the interlayer insulating film 10 shown in FIG. 5, the selectivity to the WSix film 17 is good.

In the subsequent etching of the WSix film 17, a magnetic field microwave plasma etching apparatus is used. As an example, Cl ₂ flow rate 50 SCCM O ₂ flow rate 10 SCCM pressure 0.01 Pa microwave power 1000 W (2.45 GHz) ) Solenoid coil current 21 A (upper stage) 5 A (lower stage) RF bias power 20 W (2 MHz) Wafer temperature -10 ° C. By this etching, the contact hole 14 is completed as shown in FIG. 6, but the selectivity with respect to the offset SiOx film 6 and the first sidewall 7 at this time was good.

The processed end surface 17a of the WSix film 17 formed by the above etching is covered with the sidewall-shaped sealing pattern 15sw as in the first embodiment, and finally, as shown in FIG.
The bit line lead-out electrode 16 as shown in (3) is formed to complete the memory cell.

Example 3 In this example, the impurity-containing polysilicon film 9 was used as an etching stopper film, and the vicinity of the processed end face 9a was modified by oxidation annealing into a SiOx type insulating film. The process of this embodiment will be described with reference to FIGS. The reference numerals in these drawings are partially common to those in FIGS. 1 to 9 described above.

In this embodiment, in order to protect the source / drain regions 8 from the oxidation treatment for modification, a protective insulating film having a thickness of about 5 nm is formed below the impurity-containing polysilicon film 9 which is an etching stop film. 50 nm SiOx film 18
Was formed. FIG. 10 shows a state where anisotropic etching of the interlayer insulating film 10 and the impurity-containing polysilicon film 9 is sequentially completed on the wafer and the resist pattern 11 is removed by ashing. At this point,
The processed end surface 9a of the impurity-containing polysilicon film 9 has the opening 1
9 is exposed inside.

Next, this wafer was annealed in an O ₂ / H ₂ atmosphere to oxidize the vicinity of the processed end surface 9a. As an example, the annealing conditions were O ₂ flow rate 51 SCCM H ₂ flow rate 51 SCCM temperature 950 ° C. time 10 minutes. By this annealing, the vicinity of the processed end surface 9a was changed to the modified layer 20 made of SiOx, as shown in FIG.

Subsequently, the thin SiOx film 18, which is a protective insulating film, is selectively removed by dry etching using a fluorocarbon-based gas to complete a contact hole 21 as shown in FIG. Further, a bit line lead-out electrode 22 is formed so that a memory cell as shown in FIG.
Completed the cell. In this memory cell, although the side wall-shaped sealing pattern 15sw as described in the first and second embodiments does not exist, the insulation between the impurity-containing polysilicon film 9 as the etching stop film and the upper wiring is not provided. Was secured by the modified layer 20.

Example 4 In this example, oblique rotation ion implantation of O ⁺ (oxygen ion) was applied as another modification method.

Here, at the stage of FIG. 11, ion implantation is performed on the processed end surface 9a of the impurity-containing polysilicon film 9 under the conditions of, for example, ion acceleration energy of 30 keV, dose amount of 5 × 10 ¹⁵ / cm ^{2 and} implantation angle of 7 °. It was Also in this example, similarly, the processed end surface 9a of the impurity-containing polysilicon film 9 could be changed to the modified layer 20 made of SiOx.

Although the four examples have been described above, the present invention is not limited to these examples. For example, although the impurity-containing polysilicon film and the WSix film have been described as the etching stop film, an AlOx-based material can be used as well. In addition, details such as the structure of the sample wafer, the size of each film, the film forming method, the etching conditions, the annealing conditions, and the ion implantation conditions can be appropriately changed and selected.

[0047]

As is apparent from the above description, by applying the present invention, it becomes possible to secure the dielectric strength voltage between the middle layer wiring and the upper layer wiring in the SAC structure. Therefore, taking advantage of the SAC process that can open the connection hole without depending on the diameter of the connection hole or the width of the wiring space,
It is possible to design an integrated circuit with a high degree of freedom.

The present invention promotes the reduction of the occupied area of memory cells and gate arrays by improving the accuracy of multilayer wiring formation, and greatly contributes to higher integration and higher reliability of these semiconductor devices. Is.

[Brief description of drawings]

FIG. 1 is a process example in which the present invention is applied to the formation of a multilayer wiring of a memory cell of an SRAM in which a substrate contact of a bit line extraction electrode is provided between two word lines, and a gate oxide film is provided on a Si substrate. FIG. 6 is a schematic cross-sectional view showing a state in which a word line and an offset oxide film are formed in the same pattern.

FIG. 2 is a schematic cross-sectional view showing a state in which first sidewalls are formed on the sidewalls of the word line and the offset oxide film of FIG.

3 is a schematic cross-sectional view showing a state in which a conformal etching stop film is deposited on the entire surface of the wafer of FIG. 2 and the surface of the wafer is substantially flattened with a thick interlayer insulating film.

4 is a schematic cross-sectional view showing a state in which a resist pattern is formed on the interlayer insulating film of FIG.

5 is a schematic cross-sectional view showing a state in which the interlayer insulating film of FIG. 4 is anisotropically etched.

FIG. 6 is a schematic cross-sectional view showing a state in which an etching stopper film exposed on the bottom surface of the opening of FIG. 5 is removed by anisotropic etching to open a contact hole.

7 is a conformal SiO 2 over the entire surface of the wafer of FIG.
It is a typical sectional view showing the state where the x film was deposited.

8 is a schematic cross-sectional view showing a state in which the SiOx film of FIG. 7 is etched back to form a sealing pattern.

FIG. 9 is a schematic cross-sectional view showing a state in which a bit line extraction electrode covering a contact hole is formed.

FIG. 10 shows another process example in which the present invention is applied to the formation of a multilayer interconnection of a memory cell of an SRAM in which a substrate contact of a bit line extraction electrode is provided between two word lines,
Anisotropically etch the interlayer insulating film and the etching stop film,
It is a typical sectional view showing the state where a protective insulating film was exposed.

11 is a schematic cross-sectional view showing a state in which the vicinity of the processed end surface of the etching stopper film of FIG. 10 is changed into a modified layer by an oxidation treatment.

FIG. 12 is a schematic cross-sectional view showing a state in which a protective insulating film exposed on the bottom surface of the opening of FIG. 11 is removed by anisotropic etching and a contact hole is opened.

FIG. 13 is a schematic cross-sectional view showing a state in which an upper layer wiring is formed so as to cover a contact hole.

FIG. 14 is a schematic cross-sectional view showing a state in which the resist patterning is completed in the process of forming the multilayer wiring of the memory cell of the conventional SRAM in which the SixNy film is formed as the etching stop film.

FIG. 15 is a schematic cross-sectional view showing a state in which the offset SiOx film and the sidewall are eroded as a result of etching the interlayer insulating film of FIG. 14 to open a contact hole.

16 is a schematic cross-sectional view showing a conventional self-aligned contact in which a bit line extraction electrode is formed so as to cover the contact hole of FIG.

[Explanation of symbols]

 1 Si Substrate 5 Word Line 6 Offset SiOx Film 7 First Sidewall (SiOx) 9 Polysilicon Film Containing Impurities (Etching Stop Film) 9a Processed End Face (of Polysilicon Film Containing Impurities) 10 Interlayer Insulating Film (BPSG) 14, 21 Contact hole 15 SiOx film 15a Encapsulation pattern 16,22 Bit line extraction electrode 17 WSix film (etching stop film) 17a (processed end surface of WSix film) 18 SiOx film (protective insulating film) 20 Modified layer (SiOx)

Claims (11)

[Claims] 1. A method of forming a multi-layered wiring for establishing continuity between a lower layer wiring and an upper layer wiring in an inter-wiring space between two adjacent middle layer wirings. A first step of forming an insulating film; and a second step of forming an insulating first sidewall on the side wall surface of the pattern formed of the intermediate wiring and the offset insulating film.
A third step of conformally forming an etching stopper film made of a conductive material to cover the entire surface of the substrate, and a fourth step of forming an interlayer insulating film on the etching stopper film substantially flatly, A fifth step of selectively anisotropically etching the interlayer insulating film in a region including the inter-wiring space; and a fifth step of selectively removing the etching stopper film exposed in the region to form a connection hole. A method for forming a multi-layer wiring comprising 6 steps, a 7th step of covering at least the processed end surface of the etching stop film with an insulating sealing pattern, and an 8th step of covering the connection hole with a conductive material. 2. The interlayer insulating film is made of at least one of a silicon oxide compound and a silicon nitride compound, and the etching stop film is made of at least one of a silicon conductive material and an aluminum conductive material. The method for forming a multilayer wiring according to claim 1, which is configured. 3. The method for forming a multilayer wiring according to claim 2, wherein the offset insulating film and the first sidewall are each formed of at least one of a silicon oxide compound and a silicon nitride compound. 4. The sealing pattern is formed in a sidewall shape by forming an insulating film so as to cover the entire surface of the base after the sixth step and etching back the insulating film. A method for forming a multilayer wiring as described above. 5. The method for forming a multilayer wiring according to claim 4, wherein the sealing pattern is formed by using at least one of a silicon oxide compound and a silicon nitride compound. 6. A method for forming a multi-layered wiring for establishing continuity between a lower layer wiring and an upper layer wiring in an inter-wiring space between two adjacent middle layer wirings. A first step of forming an insulating film; and a second step of forming an insulating first sidewall on the side wall surface of the pattern formed of the intermediate wiring and the offset insulating film.
Steps, a third step of forming a protective insulating film on the entire surface of the substrate, a fourth step of conformally forming an etching stop film made of a conductive material on the cap insulating film, and a step of stopping the etching. A fifth step of forming an interlayer insulating film on the film substantially flatly, a sixth step of selectively anisotropically etching the interlayer insulating film in a region including the inter-wiring space, and A seventh step of selectively removing the exposed etching stopper film, an eighth step of modifying the vicinity of the processed end surface of the etching stopper film into an insulating film, and a selective removal of the cap insulating film exposed in the region. And a tenth step of coating the connection hole with a conductive material. 7. The interlayer insulating film is made of at least one of a silicon oxide-based compound and a silicon nitride-based compound, and the etching stop film is made of at least one of a silicon-based conductive material and an aluminum-based conductive material. The method for forming a multilayer wiring according to claim 6, which is configured. 8. The method for forming a multilayer wiring according to claim 7, wherein the protective insulating film is made of at least one compound selected from silicon oxide compounds, silicon nitride compounds, and aluminum oxide. 9. The method for forming a multilayer wiring according to claim 7, wherein the modification is performed by annealing in an oxidizing atmosphere. 10. The method for forming a multilayer wiring according to claim 7, wherein the modification is performed by implanting oxygen ions into the processed end surface. 11. The method for forming a multilayer wiring according to claim 7, wherein the offset insulating film and the first sidewall are each formed of at least one of a silicon oxide compound and a silicon nitride compound.