JP3495492B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP3495492B2 JP3495492B2 JP01981896A JP1981896A JP3495492B2 JP 3495492 B2 JP3495492 B2 JP 3495492B2 JP 01981896 A JP01981896 A JP 01981896A JP 1981896 A JP1981896 A JP 1981896A JP 3495492 B2 JP3495492 B2 JP 3495492B2
- Authority
- JP
- Japan
- Prior art keywords
- metal silicide
- silicide layer
- layer
- wiring
- lower metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
Description
【発明の詳細な説明】
【0001】
【発明の属する技術分野】フォトリソグラフィー技術を
用いて金属配線の微細パターンを形成するのに好適な半
導体装置の製造方法に関する。
【0002】
【従来の技術】一般に、半導体装置の配線は、金属層の
上部を上部金属シリサイド層、下部を下部金属シリサイ
ド層で積層した構造である。上部金属シリサイド層を備
える理由は、以下の通りである。つまり、一般的にフォ
トリソグラフィー技術を利用して配線を加工しようとす
る場合、マスクパターン形成時に被加工膜の反射率が大
きいと、ハレーションと呼ばれるマスクパターンの欠陥
が発生することがある。ハレーションの発生は配線の断
線や細りを引き起こし、半導体装置の性能や信頼性を低
下させる。そこで、このハレーションを防止するため
に、配線の上面に低反射率の金属膜または金属シリサイ
ド膜(上部金属シリサイド層)を形成していた。
【0003】しかし、上部金属シリサイド層はボンディ
ング材料との密着性が悪く高抵抗であること等により、
上部金属シリサイド層上にボンディング材料を直接、接
続することができないために、配線形成後からボンディ
ングまでの間に、フォトリソグラフィー技術を利用して
上部金属シリサイド層を除去してボンディングパッド部
を形成しなければならない。そこで、通常、配線形成工
程が終了した後、ボンディングパッド部を形成するため
のフォトリソグラフィー工程が行われる。このため、ボ
ンディングパッド部用のマスクが必要となり、製造工程
数も増加する。
【0004】一方、下部金属シリサイド層を備える理由
は、以下の通りである。つまり、配線の下部は層間絶縁
層やシリコン基板、下部配線膜と接する。このような異
なる二層が接する界面の構造安定性は、その組み合わせ
により大きく変化する。配線材料として最も多く使用さ
れるアルミニウム(Al)またはアルミニウム合金の場
合、半導体装置の基板として一般的なシリコン(Si)
との安定性が悪く、コンタクト部の接合を破壊するスパ
イク現象や、熱処理の冷却過程でシリコンがコンタクト
部に析出し抵抗を増大させるなどの問題が発生すること
が知られている。この対策として配線材料膜の下面に高
融点金属膜または金属シリサイド膜(下部金属シリサイ
ド層)を形成するのが有効である。
【0005】図1に、上部金属シリサイド層、金属層、
下部金属シリサイド層の従来の配線構造の加工手順を示
す。図1(a)から図1(h)に製造工程を工程別に示
す。すなわち、図1(a)は、下地の絶縁層またはシリ
コン基板11、下部金属シリサイド層12、金属層13
および上部金属シリサイド層14上に、マスク(パター
ン)15が形成された状態を示し、図1(b)は、上部
金属シリサイド層14がエッチングされた状態を示し、
図1(c)は、次いで金属層13がエッチングされた状
態を示し、図1(d)は、さらに下部金属シリサイド層
12がエッチングされた状態を示す。図1(e)は、マ
スク材料15をアッシングした後の状態を示している。
また、図1(f)〜(h)はボンディングパッド部の形
成を示すものである。
【0006】また、アルミニウム合金等を配線材料とし
た場合、エッチング終了後に金属配線の腐蝕が発生する
ことがある。腐蝕防止のためにプラズマエッチングおよ
びマスク材料の除去が同一装置で処理されることは公知
である。
【0007】そこで、マスク材料を除去するため、プラ
ズマ処理(アッシング)を行うが、この時に使用される
アッシングガスは、酸素(O2 )またはこれにSF6 ,
CF4 等フッ素化合物のガス等が添加される。しかし、
これらのSF6 ,CF4 等フッ素化合物のガスはアッシ
ング速度を大きくするために添加されたものであり、マ
スク材料が除去された後に上部金属シリサイド層または
/および下部金属シリサイド層がオーバーエッチングさ
れることにより不具合が生じる。
【0008】
【発明が解決しようとする課題】ボンディング性を向上
させるためには、上部金属シリサイド層の除去が不可欠
である。したがって、ボンディングパッド形成のため、
専用のマスクおよびフォトリソグラフィー工程が必要と
なり、製造工程数が増加する。また、従来の製造方法で
は下部金属シリサイド層のエッチングが過剰に実施され
るため下地となる絶縁層の損傷が大きい。
【0009】本発明は、前記問題点を解決するためにな
されたもので、次のような事項を目的としている。
【0010】(a)ボンディングパッド形成のための工
程を削減する。
【0011】(b)下地の絶縁層または基板などに与え
る損傷を低減する。
【0012】
【課題を解決するための手段】本発明は、配線が絶縁層
の上に下部金属シリサイド層と、該下部金属シリサイド
層の上に金属層と、該金属層の上に上部金属シリサイド
層とを有する半導体装置の製造方法において、前記配線
を選択的に除去するためにマスクを形成し、前記上部金
属シリサイド層と前記金属層を前記下部金属シリサイド
層を残してプラズマエッチングし、その後、前記マスク
のアッシングと、前記上部金属シリサイド層および前記
下部金属シリサイド層のプラズマエッチングを同時に同
一処理室で処理することを特徴とする半導体装置の製造
方法を提供するものである。
【0013】
【発明の実施の形態】本発明の製造工程を工程別に図3
(a)から(d)に示す。すなわち、図3(a)は、前
記図1(a)と同様にマスクパターンが形成された状態
を示し、図3(b)は、前記図1(b)と同様に上部金
属シリサイド層14がエッチングされた状態を示し、図
3(c)は、下部金属シリサイド層12を残して上部金
属シリサイド層14および金属層13をプラズマエッチ
ングした状態を示し、図3(d)は、マスク材料15の
アッシングと同時に上部金属シリサイド層および下部金
属シリサイド層とが同時にプラズマエッチングされた状
態を示すものである。
【0014】なお、プラズマ処理のためのプラズマ発生
方法は、高周波電力の印加によるもの、マイクロ波の導
入によるものおよび/またはその他の方法によるもので
あっても構わない。また、上部金属シリサイド層および
下部金属シリサイド層がモリブテン(Mo)、タングス
テン(W)および/またはそれらのシリサイドであるこ
と、配線材料がアルミニウム(Al)またはアルミニウ
ム合金であること、上部金属シリサイド層および下部金
属シリサイド層のエッチングガスにSF6 ,CF4 等の
フッ素化合物を含むガスを使用することが好ましい。
【0015】配線パターンが形成された後、マスク材料
を除去するためにプラズマ処理(アッシング)が行われ
る。この時に使用されるアッシングガスにSF6 ,CF
4 等フッ素化合物のガスを添加することにより、モリブ
デン(Mo),タングステン(W)および/またはそれ
らのシリサイドはフッ化物となりエッチングされる。こ
れは、モリブデン(Mo),タングステン(W)および
ケイ素(Si)のフッ化物の蒸気圧が大きいことによ
る。マスク材料の除去と上部金属シリサイド層とを同一
処理で取り除くことにより、ボンディングパッド形成の
ための専用のマスクおよびフォトリソグラフィー工程が
不要となる。
【0016】また、従来の方法による半導体装置の製造
にあっては、配線のエッチングは上部金属シリサイド膜
と金属膜、下部金属シリサイド膜とでエッチング条件を
変える多段エッチングで実施され、この後、別の処理室
でマスクが除去される。この工程を図1(a)から図1
(b),図1(c),図1(d)そして図1(e)に示
す。この時、下部金属シリサイドのエッチングが不十分
であると配線の短絡を引き起こし、収率の低下を招くた
め、通常過剰のエッチング(オーバーエッチング)を行
う。オーバーエッチングが過ぎると、図2に示されるよ
うに下部金属シリサイド層に大きなサイドエッチングが
生じ、さらに下地絶縁層にも損傷が生じる。
【0017】本発明では、図3(c)(図1(c)と同
様)に示すように下部金属シリサイド層が残存する状態
でエッチングを終了し、マスクのアッシングと上部金属
シリサイド層および下部金属シリサイド層のプラズマエ
ッチングとを同時に同一処理室で処理することにより、
下部金属シリサイド層へのサイドエッチを大きく低減す
ることができ、同時に従来の工程数を減少することがで
きる。
【0018】
【実施例】以下に、本発明の実施例を比較例とともに示
す。
【0019】(実施例1)上部金属シリサイド層:Mo
Si2 /金属層:Al−Si(1%)−Cu(0.5
%)/下部金属シリサイド層:MoSi2 (膜厚:各々
40nm/800nm/60nm)の積層構造を持つ配
線を下部金属シリサイド層を残してプラズマエッチング
し(図3(a)〜図3(c))、O2 流量6.3ml/
sec.(at 0℃,1atm)、CF4 流量0.6
7ml/sec.(at 0℃,1atm)、圧力19
0Paでプラズマを発生させ、150秒処理を行った。
処理後、配線表面のモリブデン(Mo)の濃度を蛍光X
線を用いて測定したところ、7.2×1012atom/
cm2 であった。また、下地絶縁層である酸化膜の削れ
量は60nmであった。
【0020】(実施例2)上部金属シリサイド層:Mo
Si2 /金属層:Al−Si(1%)−Cu(0.5
%)/下部金属シリサイド層:MoSi2 (膜厚:各々
40nm/800nm/60nm)の積層構造を持つ配
線を下部金属シリサイド層を残してプラズマエッチング
し(図3(a)〜図3(c))、O2 流量6.7ml/
sec.(at 0℃,1atm)、CF4 流量0.3
3ml/sec.(at 0℃,1atm)、圧力19
0Paでプラズマを発生させ、150秒間処理を行っ
た。処理後、配線表面のモリブデン(Mo)の濃度を蛍
光X線を用いて測定したところ、8.1×1012ato
m/cm2 であった。また、下地絶縁層である酸化膜の
削れ量は45nmであった。
【0021】(実施例3)上部金属シリサイド層:Mo
Si2 /金属層:Al−Si(1%)−Cu(0.5
%)/下部金属シリサイド層:MoSi2 (膜厚:各々
40nm/800nm/60nm)の積層構造を持つ配
線を下部金属シリサイド層を残してプラズマエッチング
し(図3(a)〜図3(c))、O2 流量6.0ml/
sec.(at 0℃,1atm)、CF4 流量1.0
ml/sec.(at 0℃,1atm)、圧力190
Paでプラズマを発生させ、120秒間処理を行った。
処理後、配線表面のモリブデン(Mo)の濃度を蛍光X
線を用いて測定したところ、7.1×1012atom/
cm2 であった。また、下地絶縁層である酸化膜の削れ
量は80nmであった。
【0022】(比較例1)上部金属シリサイズ層:Mo
Si2 /金属層:Al−Si(1%)−Cu(0.5
%)/下部金属シリサイド層:MoSi2 (膜厚:各々
40nm/800nm/60nm)の積層構造を持つ配
線を下部金属シリサイド層を残さずプラズマエッチング
し(図1(a)〜図1(d))、その後、O2 流量6.
3ml/sec.(at 0℃,1atm)、CF4 流
量0.33ml/sec.(at 0℃,1atm)、
圧力190Paでプラズマを発生させ、50秒間処理を
行った(図1(e))。処理後、配線表面のモリブデン
(Mo)の濃度を蛍光X線を用いて測定したところ、
3.1×1014atom/cm2 であった。また、下地
絶縁層である酸化膜の削れ量は140nmであった。
【0023】(比較例2)上部金属シリサイド層:Mo
Si2 /金属層:Al−Si(1%)−Cu(0.5
%)/下部金属シリサイド層:MoSi2 (膜厚:各々
40nm/800nm/60nm)の積層構造を持つ配
線を下部金属シリサイド層を残さずプラズマエッチング
し(図1(a)〜図1(d))、その後、O2 流量6.
3ml/sec.(at 0℃,1atm)、CF4 流
量0.33ml/sec.(at 0℃,1atm)、
圧力190Paでプラズマを発生させ、50秒間処理を
行った(図1(e))。引き続いて、ボンディングパッ
ド形成のためのフォトリソグラフィー工程を実施した
(図1(f))。上部金属シリサイド層のエッチングは
平行平板型のエッチング装置を使用し、O2 流量0.6
0ml/sec.(at0℃,1atm)、CF4 流量
0.05ml/sec.(at 0℃,1atm)、圧
力50Paで高周波電力150Wを印加し、60秒プラ
ズマ処理した(図1(g))。配線表面のモリブデン
(Mo)の濃度を蛍光X線を用いて測定したところ、
7.0×1012atom/cm2 であった。また、下地
絶縁層である酸化膜の削れ量は140nmであった。
【0024】
【発明の効果】本発明によれば、次の効果が得られる。
【0025】(a)マスク材料の除去後、連続的に同一
処理室内で上部金属シリサイド層のエッチングを行うた
め、ボンディングパッド形成のための専用のマスクおよ
びフォトリソグラフィー工程を削減でき、しかも非常に
簡便である。
【0026】(b)下地となる絶縁層または基板などの
損傷を低減することができる。Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing a semiconductor device suitable for forming a fine pattern of a metal wiring by using a photolithography technique. 2. Description of the Related Art In general, a wiring of a semiconductor device has a structure in which an upper portion of a metal layer is stacked with an upper metal silicide layer and a lower portion is stacked with a lower metal silicide layer. The reason for providing the upper metal silicide layer is as follows. That is, generally, when wiring is to be processed by using the photolithography technology, a defect of a mask pattern called halation may occur if the reflectance of a film to be processed is large at the time of forming a mask pattern. The occurrence of halation causes disconnection or thinning of the wiring, and lowers the performance and reliability of the semiconductor device. Therefore, in order to prevent this halation, a metal film or a metal silicide film (upper metal silicide layer) having a low reflectance is formed on the upper surface of the wiring. However, the upper metal silicide layer has poor adhesion to the bonding material and has a high resistance.
Since the bonding material cannot be directly connected to the upper metal silicide layer, the upper metal silicide layer is removed using photolithography technology between the wiring formation and the bonding, and the bonding pad is formed. There must be. Therefore, usually, after the wiring forming step is completed, a photolithography step for forming a bonding pad portion is performed. For this reason, a mask for the bonding pad portion is required, and the number of manufacturing steps increases. On the other hand, the reason for providing the lower metal silicide layer is as follows. That is, the lower part of the wiring is in contact with the interlayer insulating layer, the silicon substrate, and the lower wiring film. The structural stability of the interface where these two different layers are in contact greatly changes depending on the combination. In the case of aluminum (Al) or aluminum alloy, which is most frequently used as a wiring material, silicon (Si) generally used as a substrate of a semiconductor device
It is known that problems such as a spike phenomenon that breaks the junction of the contact portion, and the deposition of silicon on the contact portion during the cooling process of the heat treatment to increase the resistance occur. As a countermeasure, it is effective to form a high melting point metal film or a metal silicide film (lower metal silicide layer) on the lower surface of the wiring material film. FIG. 1 shows an upper metal silicide layer, a metal layer,
1 shows a processing procedure of a conventional wiring structure of a lower metal silicide layer. 1 (a) to 1 (h) show the manufacturing process for each process. That is, FIG. 1A shows an underlying insulating layer or silicon substrate 11, a lower metal silicide layer 12, a metal layer 13.
1B shows a state in which a mask (pattern) 15 is formed on the upper metal silicide layer 14, and FIG. 1B shows a state in which the upper metal silicide layer 14 is etched.
FIG. 1C shows a state in which the metal layer 13 is subsequently etched, and FIG. 1D shows a state in which the lower metal silicide layer 12 is further etched. FIG. 1E shows a state after the mask material 15 has been ashed.
FIGS. 1F to 1H show the formation of a bonding pad portion. In the case where an aluminum alloy or the like is used as a wiring material, metal wiring may be corroded after completion of etching. It is known that plasma etching and mask material removal are performed in the same apparatus to prevent corrosion. In order to remove the mask material, plasma processing (ashing) is performed. The ashing gas used at this time is oxygen (O 2 ) or SF 6 ,
A gas of a fluorine compound such as CF 4 is added. But,
These fluorine compound gases such as SF 6 and CF 4 are added to increase the ashing rate, and after the mask material is removed, the upper metal silicide layer and / or the lower metal silicide layer is over-etched. This causes a problem. In order to improve the bonding property, it is essential to remove the upper metal silicide layer. Therefore, to form the bonding pad,
A dedicated mask and a photolithography step are required, and the number of manufacturing steps increases. In addition, in the conventional manufacturing method, the lower metal silicide layer is excessively etched, so that the underlying insulating layer is greatly damaged. The present invention has been made to solve the above problems, and has the following objects. (A) Steps for forming bonding pads are reduced. (B) Damage to the underlying insulating layer or substrate is reduced. According to the present invention, a wiring is provided in which a lower metal silicide layer is formed on an insulating layer, a metal layer is formed on the lower metal silicide layer, and an upper metal silicide is formed on the metal layer. In the method for manufacturing a semiconductor device having a layer, a mask is formed to selectively remove the wiring, and the upper metal silicide layer and the metal layer are plasma-etched while leaving the lower metal silicide layer. An object of the present invention is to provide a method of manufacturing a semiconductor device, wherein ashing of the mask and plasma etching of the upper metal silicide layer and the lower metal silicide layer are simultaneously performed in the same processing chamber. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
(A) to (d) are shown. That is, FIG. 3A shows a state in which a mask pattern is formed in the same manner as in FIG. 1A, and FIG. 3B shows a state in which the upper metal silicide layer 14 is formed as in FIG. FIG. 3C shows a state in which the upper metal silicide layer 14 and the metal layer 13 are plasma-etched while leaving the lower metal silicide layer 12, and FIG. This shows a state in which the upper metal silicide layer and the lower metal silicide layer are simultaneously plasma-etched simultaneously with the ashing. The plasma generation method for the plasma processing may be a method by applying a high-frequency power, a method by introducing a microwave, and / or another method. The upper metal silicide layer and the lower metal silicide layer are molybdenum (Mo), tungsten (W) and / or a silicide thereof, the wiring material is aluminum (Al) or an aluminum alloy, the upper metal silicide layer and It is preferable to use a gas containing a fluorine compound such as SF 6 or CF 4 as an etching gas for the lower metal silicide layer. After the wiring pattern is formed, plasma processing (ashing) is performed to remove the mask material. The ashing gas used at this time is SF 6 , CF
By adding a gas of a fluorine compound such as 4 , molybdenum (Mo), tungsten (W) and / or silicide thereof becomes fluoride and is etched. This is because the vapor pressure of fluorides of molybdenum (Mo), tungsten (W) and silicon (Si) is large. By removing the mask material and removing the upper metal silicide layer in the same process, a dedicated mask and a photolithography process for forming the bonding pad are not required. In the conventional method of manufacturing a semiconductor device, wiring is etched by multi-stage etching in which etching conditions are changed between an upper metal silicide film, a metal film, and a lower metal silicide film. The mask is removed in the processing chamber. This process is shown in FIGS.
(B), FIG. 1 (c), FIG. 1 (d) and FIG. 1 (e). At this time, if the etching of the lower metal silicide is insufficient, a short circuit of the wiring is caused and a reduction in the yield is caused. Therefore, excessive etching (over-etching) is usually performed. After the over-etching, as shown in FIG. 2, large side etching occurs in the lower metal silicide layer, and damage also occurs to the underlying insulating layer. In the present invention, as shown in FIG. 3 (c) (similar to FIG. 1 (c)), the etching is completed with the lower metal silicide layer remaining, ashing of the mask, the upper metal silicide layer and the lower metal silicide layer. By simultaneously performing the plasma etching of the silicide layer in the same processing chamber,
Side etching on the lower metal silicide layer can be greatly reduced, and at the same time, the number of conventional steps can be reduced. EXAMPLES Examples of the present invention will be described below together with comparative examples. (Example 1) Upper metal silicide layer: Mo
Si 2 / metal layer: Al—Si (1%) — Cu (0.5
%) / Lower metal silicide layer: Wiring having a laminated structure of MoSi 2 (thickness: 40 nm / 800 nm / 60 nm, respectively) is plasma-etched while leaving the lower metal silicide layer (FIGS. 3A to 3C). ), O 2 flow rate 6.3 ml /
sec. (At 0 ° C., 1 atm), CF 4 flow rate 0.6
7 ml / sec. (At 0 ° C., 1 atm), pressure 19
Plasma was generated at 0 Pa, and the treatment was performed for 150 seconds.
After processing, the concentration of molybdenum (Mo) on the wiring surface is
When measured using a line, 7.2 × 10 12 atoms /
cm 2 . The amount of shaving of the oxide film serving as the base insulating layer was 60 nm. (Embodiment 2) Upper metal silicide layer: Mo
Si 2 / metal layer: Al—Si (1%) — Cu (0.5
%) / Lower metal silicide layer: Wiring having a laminated structure of MoSi 2 (thickness: 40 nm / 800 nm / 60 nm, respectively) is plasma-etched while leaving the lower metal silicide layer (FIGS. 3A to 3C). ), O 2 flow rate 6.7 ml /
sec. (At 0 ° C., 1 atm), CF 4 flow rate 0.3
3 ml / sec. (At 0 ° C., 1 atm), pressure 19
Plasma was generated at 0 Pa, and the treatment was performed for 150 seconds. After the treatment, the concentration of molybdenum (Mo) on the wiring surface was measured using fluorescent X-rays to find that the concentration was 8.1 × 10 12 at.
m / cm 2 . The amount of shaving of the oxide film serving as the base insulating layer was 45 nm. (Embodiment 3) Upper metal silicide layer: Mo
Si 2 / metal layer: Al—Si (1%) — Cu (0.5
%) / Lower metal silicide layer: Wiring having a laminated structure of MoSi 2 (thickness: 40 nm / 800 nm / 60 nm, respectively) is plasma-etched while leaving the lower metal silicide layer (FIGS. 3A to 3C). ), O 2 flow 6.0 ml /
sec. (At 0 ° C., 1 atm), CF 4 flow rate 1.0
ml / sec. (At 0 ° C., 1 atm), pressure 190
Plasma was generated at Pa and the treatment was performed for 120 seconds.
After processing, the concentration of molybdenum (Mo) on the wiring surface is
When measured using a line, 7.1 × 10 12 atoms /
cm 2 . Further, the shaved amount of the oxide film serving as the base insulating layer was 80 nm. (Comparative Example 1) Upper metal silicide layer: Mo
Si 2 / metal layer: Al—Si (1%) — Cu (0.5
%) / Lower metal silicide layer: Wiring having a laminated structure of MoSi 2 (thickness: 40 nm / 800 nm / 60 nm, respectively) is plasma-etched without leaving the lower metal silicide layer (FIGS. 1A to 1D). 5.) then the O 2 flow rate
3 ml / sec. (At 0 ° C., 1 atm), CF 4 flow rate 0.33 ml / sec. (At 0 ° C, 1 atm),
Plasma was generated at a pressure of 190 Pa, and the treatment was performed for 50 seconds (FIG. 1E). After the treatment, the concentration of molybdenum (Mo) on the wiring surface was measured using fluorescent X-rays.
3.1 × 10 14 atoms / cm 2 . The amount of shaving of the oxide film serving as the base insulating layer was 140 nm. Comparative Example 2 Upper Metal Silicide Layer: Mo
Si 2 / metal layer: Al—Si (1%) — Cu (0.5
%) / Lower metal silicide layer: Wiring having a laminated structure of MoSi 2 (thickness: 40 nm / 800 nm / 60 nm, respectively) is plasma-etched without leaving the lower metal silicide layer (FIGS. 1A to 1D). 5.) then the O 2 flow rate
3 ml / sec. (At 0 ° C., 1 atm), CF 4 flow rate 0.33 ml / sec. (At 0 ° C, 1 atm),
Plasma was generated at a pressure of 190 Pa, and the treatment was performed for 50 seconds (FIG. 1E). Subsequently, a photolithography process for forming a bonding pad was performed (FIG. 1F). For etching the upper metal silicide layer, a parallel plate type etching apparatus was used, and the O 2 flow rate was 0.6.
0 ml / sec. (At 0 ° C., 1 atm), CF 4 flow rate 0.05 ml / sec. (At 0 ° C., 1 atm), a high-frequency power of 150 W was applied at a pressure of 50 Pa, and plasma treatment was performed for 60 seconds (FIG. 1 (g)). When the concentration of molybdenum (Mo) on the wiring surface was measured using fluorescent X-rays,
It was 7.0 × 10 12 atoms / cm 2 . The amount of shaving of the oxide film serving as the base insulating layer was 140 nm. According to the present invention, the following effects can be obtained. (A) After the mask material is removed, the upper metal silicide layer is continuously etched in the same processing chamber, so that a dedicated mask for forming a bonding pad and a photolithography step can be reduced, and it is very simple. It is. (B) Damage to the underlying insulating layer or substrate can be reduced.
【図面の簡単な説明】
【図1】(a)〜(h)は、従来の製造工程を示す縦断
面図である。
【図2】従来の製造工程でアッシング処理時間のみを延
長した場合の縦断面図である。
【図3】(a)〜(d)は、本発明の実施例の製造工程
を工程別に示す縦断面図である。
【符号の説明】
11 下地の絶縁層またはシリコン基板
12 下部金属シリサイド層
13 金属層
14 上部金属シリサイド層
15 マスク材料BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1H are longitudinal sectional views showing a conventional manufacturing process. FIG. 2 is a longitudinal sectional view when only ashing processing time is extended in a conventional manufacturing process. FIGS. 3A to 3D are longitudinal sectional views showing the manufacturing steps of the embodiment of the present invention step by step. [Description of Signs] 11 Underlying insulating layer or silicon substrate 12 Lower metal silicide layer 13 Metal layer 14 Upper metal silicide layer 15 Mask material
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/3213 H01L 21/3205 H01L 21/60 H01L 21/3065 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/3213 H01L 21/3205 H01L 21/60 H01L 21/3065
Claims (1)
層と、該下部金属シリサイド層の上に金属層と、該金属
層の上に上部金属シリサイド層とを有する半導体装置の
製造方法において、前記配線を選択的に除去するために
マスクを形成し、前記上部金属シリサイド層と前記金属
層を前記下部金属シリサイド層を残してプラズマエッチ
ングし、その後、前記マスクのアッシングと、前記上部
金属シリサイド層および前記下部金属シリサイド層のプ
ラズマエッチングを同時に同一処理室で処理することを
特徴とする半導体装置の製造方法。(57) [Claim 1] A wiring comprises a lower metal silicide layer on an insulating layer, a metal layer on the lower metal silicide layer, and an upper metal silicide layer on the metal layer. Forming a mask for selectively removing the wiring, plasma-etching the upper metal silicide layer and the metal layer while leaving the lower metal silicide layer, and then forming the mask Ashing and plasma etching of the upper metal silicide layer and the lower metal silicide layer are simultaneously performed in the same processing chamber.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP01981896A JP3495492B2 (en) | 1996-02-06 | 1996-02-06 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP01981896A JP3495492B2 (en) | 1996-02-06 | 1996-02-06 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09213705A JPH09213705A (en) | 1997-08-15 |
JP3495492B2 true JP3495492B2 (en) | 2004-02-09 |
Family
ID=12009908
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Application Number | Title | Priority Date | Filing Date |
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JP01981896A Expired - Fee Related JP3495492B2 (en) | 1996-02-06 | 1996-02-06 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
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JP (1) | JP3495492B2 (en) |
-
1996
- 1996-02-06 JP JP01981896A patent/JP3495492B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH09213705A (en) | 1997-08-15 |
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