JP3495492B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing a semiconductor device suitable for forming a fine pattern of a metal wiring by using a photolithography technique. 2. Description of the Related Art In general, a wiring of a semiconductor device has a structure in which an upper portion of a metal layer is stacked with an upper metal silicide layer and a lower portion is stacked with a lower metal silicide layer. The reason for providing the upper metal silicide layer is as follows. That is, generally, when wiring is to be processed by using the photolithography technology, a defect of a mask pattern called halation may occur if the reflectance of a film to be processed is large at the time of forming a mask pattern. The occurrence of halation causes disconnection or thinning of the wiring, and lowers the performance and reliability of the semiconductor device. Therefore, in order to prevent this halation, a metal film or a metal silicide film (upper metal silicide layer) having a low reflectance is formed on the upper surface of the wiring. However, the upper metal silicide layer has poor adhesion to the bonding material and has a high resistance.
Since the bonding material cannot be directly connected to the upper metal silicide layer, the upper metal silicide layer is removed using photolithography technology between the wiring formation and the bonding, and the bonding pad is formed. There must be. Therefore, usually, after the wiring forming step is completed, a photolithography step for forming a bonding pad portion is performed. For this reason, a mask for the bonding pad portion is required, and the number of manufacturing steps increases. On the other hand, the reason for providing the lower metal silicide layer is as follows. That is, the lower part of the wiring is in contact with the interlayer insulating layer, the silicon substrate, and the lower wiring film. The structural stability of the interface where these two different layers are in contact greatly changes depending on the combination. In the case of aluminum (Al) or aluminum alloy, which is most frequently used as a wiring material, silicon (Si) generally used as a substrate of a semiconductor device
It is known that problems such as a spike phenomenon that breaks the junction of the contact portion, and the deposition of silicon on the contact portion during the cooling process of the heat treatment to increase the resistance occur. As a countermeasure, it is effective to form a high melting point metal film or a metal silicide film (lower metal silicide layer) on the lower surface of the wiring material film. FIG. 1 shows an upper metal silicide layer, a metal layer,
1 shows a processing procedure of a conventional wiring structure of a lower metal silicide layer. 1 (a) to 1 (h) show the manufacturing process for each process. That is, FIG. 1A shows an underlying insulating layer or silicon substrate 11, a lower metal silicide layer 12, a metal layer 13.
1B shows a state in which a mask (pattern) 15 is formed on the upper metal silicide layer 14, and FIG. 1B shows a state in which the upper metal silicide layer 14 is etched.
FIG. 1C shows a state in which the metal layer 13 is subsequently etched, and FIG. 1D shows a state in which the lower metal silicide layer 12 is further etched. FIG. 1E shows a state after the mask material 15 has been ashed.
FIGS. 1F to 1H show the formation of a bonding pad portion. In the case where an aluminum alloy or the like is used as a wiring material, metal wiring may be corroded after completion of etching. It is known that plasma etching and mask material removal are performed in the same apparatus to prevent corrosion. In order to remove the mask material, plasma processing (ashing) is performed. The ashing gas used at this time is oxygen (O ₂ ) or SF ₆ ,
A gas of a fluorine compound such as CF ₄ is added. But,
These fluorine compound gases such as SF ₆ and CF ₄ are added to increase the ashing rate, and after the mask material is removed, the upper metal silicide layer and / or the lower metal silicide layer is over-etched. This causes a problem. In order to improve the bonding property, it is essential to remove the upper metal silicide layer. Therefore, to form the bonding pad,
A dedicated mask and a photolithography step are required, and the number of manufacturing steps increases. In addition, in the conventional manufacturing method, the lower metal silicide layer is excessively etched, so that the underlying insulating layer is greatly damaged. The present invention has been made to solve the above problems, and has the following objects. (A) Steps for forming bonding pads are reduced. (B) Damage to the underlying insulating layer or substrate is reduced. According to the present invention, a wiring is provided in which a lower metal silicide layer is formed on an insulating layer, a metal layer is formed on the lower metal silicide layer, and an upper metal silicide is formed on the metal layer. In the method for manufacturing a semiconductor device having a layer, a mask is formed to selectively remove the wiring, and the upper metal silicide layer and the metal layer are plasma-etched while leaving the lower metal silicide layer. An object of the present invention is to provide a method of manufacturing a semiconductor device, wherein ashing of the mask and plasma etching of the upper metal silicide layer and the lower metal silicide layer are simultaneously performed in the same processing chamber. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG.
(A) to (d) are shown. That is, FIG. 3A shows a state in which a mask pattern is formed in the same manner as in FIG. 1A, and FIG. 3B shows a state in which the upper metal silicide layer 14 is formed as in FIG. FIG. 3C shows a state in which the upper metal silicide layer 14 and the metal layer 13 are plasma-etched while leaving the lower metal silicide layer 12, and FIG. This shows a state in which the upper metal silicide layer and the lower metal silicide layer are simultaneously plasma-etched simultaneously with the ashing. The plasma generation method for the plasma processing may be a method by applying a high-frequency power, a method by introducing a microwave, and / or another method. The upper metal silicide layer and the lower metal silicide layer are molybdenum (Mo), tungsten (W) and / or a silicide thereof, the wiring material is aluminum (Al) or an aluminum alloy, the upper metal silicide layer and It is preferable to use a gas containing a fluorine compound such as SF ₆ or CF _{4 as} an etching gas for the lower metal silicide layer. After the wiring pattern is formed, plasma processing (ashing) is performed to remove the mask material. The ashing gas used at this time is SF ₆ , CF
By adding a gas of a fluorine compound such as ₄ , molybdenum (Mo), tungsten (W) and / or silicide thereof becomes fluoride and is etched. This is because the vapor pressure of fluorides of molybdenum (Mo), tungsten (W) and silicon (Si) is large. By removing the mask material and removing the upper metal silicide layer in the same process, a dedicated mask and a photolithography process for forming the bonding pad are not required. In the conventional method of manufacturing a semiconductor device, wiring is etched by multi-stage etching in which etching conditions are changed between an upper metal silicide film, a metal film, and a lower metal silicide film. The mask is removed in the processing chamber. This process is shown in FIGS.
(B), FIG. 1 (c), FIG. 1 (d) and FIG. 1 (e). At this time, if the etching of the lower metal silicide is insufficient, a short circuit of the wiring is caused and a reduction in the yield is caused. Therefore, excessive etching (over-etching) is usually performed. After the over-etching, as shown in FIG. 2, large side etching occurs in the lower metal silicide layer, and damage also occurs to the underlying insulating layer. In the present invention, as shown in FIG. 3 (c) (similar to FIG. 1 (c)), the etching is completed with the lower metal silicide layer remaining, ashing of the mask, the upper metal silicide layer and the lower metal silicide layer. By simultaneously performing the plasma etching of the silicide layer in the same processing chamber,
Side etching on the lower metal silicide layer can be greatly reduced, and at the same time, the number of conventional steps can be reduced. EXAMPLES Examples of the present invention will be described below together with comparative examples. (Example 1) Upper metal silicide layer: Mo
Si ₂ / metal layer: Al—Si (1%) — Cu (0.5
%) / Lower metal silicide layer: Wiring having a laminated structure of MoSi ₂ (thickness: 40 nm / 800 nm / 60 nm, respectively) is plasma-etched while leaving the lower metal silicide layer (FIGS. 3A to 3C). ), O ₂ flow rate 6.3 ml /
sec. (At 0 ° C., 1 atm), CF ₄ flow rate 0.6
7 ml / sec. (At 0 ° C., 1 atm), pressure 19
Plasma was generated at 0 Pa, and the treatment was performed for 150 seconds.
After processing, the concentration of molybdenum (Mo) on the wiring surface is
When measured using a line, 7.2 × 10 ¹² atoms /
cm ² . The amount of shaving of the oxide film serving as the base insulating layer was 60 nm. (Embodiment 2) Upper metal silicide layer: Mo
Si ₂ / metal layer: Al—Si (1%) — Cu (0.5
%) / Lower metal silicide layer: Wiring having a laminated structure of MoSi ₂ (thickness: 40 nm / 800 nm / 60 nm, respectively) is plasma-etched while leaving the lower metal silicide layer (FIGS. 3A to 3C). ), O ₂ flow rate 6.7 ml /
sec. (At 0 ° C., 1 atm), CF ₄ flow rate 0.3
3 ml / sec. (At 0 ° C., 1 atm), pressure 19
Plasma was generated at 0 Pa, and the treatment was performed for 150 seconds. After the treatment, the concentration of molybdenum (Mo) on the wiring surface was measured using fluorescent X-rays to find that the concentration was 8.1 × 10 ^{12 at.}
m / cm ² . The amount of shaving of the oxide film serving as the base insulating layer was 45 nm. (Embodiment 3) Upper metal silicide layer: Mo
Si ₂ / metal layer: Al—Si (1%) — Cu (0.5
%) / Lower metal silicide layer: Wiring having a laminated structure of MoSi ₂ (thickness: 40 nm / 800 nm / 60 nm, respectively) is plasma-etched while leaving the lower metal silicide layer (FIGS. 3A to 3C). ), O ₂ flow 6.0 ml /
sec. (At 0 ° C., 1 atm), CF ₄ flow rate 1.0
ml / sec. (At 0 ° C., 1 atm), pressure 190
Plasma was generated at Pa and the treatment was performed for 120 seconds.
After processing, the concentration of molybdenum (Mo) on the wiring surface is
When measured using a line, 7.1 × 10 ¹² atoms /
cm ² . Further, the shaved amount of the oxide film serving as the base insulating layer was 80 nm. (Comparative Example 1) Upper metal silicide layer: Mo
Si ₂ / metal layer: Al—Si (1%) — Cu (0.5
%) / Lower metal silicide layer: Wiring having a laminated structure of MoSi ₂ (thickness: 40 nm / 800 nm / 60 nm, respectively) is plasma-etched without leaving the lower metal silicide layer (FIGS. 1A to 1D). 5.) then the O ₂ flow rate
3 ml / sec. (At 0 ° C., 1 atm), CF ₄ flow rate 0.33 ml / sec. (At 0 ° C, 1 atm),
Plasma was generated at a pressure of 190 Pa, and the treatment was performed for 50 seconds (FIG. 1E). After the treatment, the concentration of molybdenum (Mo) on the wiring surface was measured using fluorescent X-rays.
3.1 × 10 ¹⁴ atoms / cm ² . The amount of shaving of the oxide film serving as the base insulating layer was 140 nm. Comparative Example 2 Upper Metal Silicide Layer: Mo
Si ₂ / metal layer: Al—Si (1%) — Cu (0.5
%) / Lower metal silicide layer: Wiring having a laminated structure of MoSi ₂ (thickness: 40 nm / 800 nm / 60 nm, respectively) is plasma-etched without leaving the lower metal silicide layer (FIGS. 1A to 1D). 5.) then the O ₂ flow rate
3 ml / sec. (At 0 ° C., 1 atm), CF ₄ flow rate 0.33 ml / sec. (At 0 ° C, 1 atm),
Plasma was generated at a pressure of 190 Pa, and the treatment was performed for 50 seconds (FIG. 1E). Subsequently, a photolithography process for forming a bonding pad was performed (FIG. 1F). For etching the upper metal silicide layer, a parallel plate type etching apparatus was used, and the O ₂ flow rate was 0.6.
0 ml / sec. (At 0 ° C., 1 atm), CF ₄ flow rate 0.05 ml / sec. (At 0 ° C., 1 atm), a high-frequency power of 150 W was applied at a pressure of 50 Pa, and plasma treatment was performed for 60 seconds (FIG. 1 (g)). When the concentration of molybdenum (Mo) on the wiring surface was measured using fluorescent X-rays,
It was 7.0 × 10 ¹² atoms / cm ² . The amount of shaving of the oxide film serving as the base insulating layer was 140 nm. According to the present invention, the following effects can be obtained. (A) After the mask material is removed, the upper metal silicide layer is continuously etched in the same processing chamber, so that a dedicated mask for forming a bonding pad and a photolithography step can be reduced, and it is very simple. It is. (B) Damage to the underlying insulating layer or substrate can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1H are longitudinal sectional views showing a conventional manufacturing process. FIG. 2 is a longitudinal sectional view when only ashing processing time is extended in a conventional manufacturing process. FIGS. 3A to 3D are longitudinal sectional views showing the manufacturing steps of the embodiment of the present invention step by step. [Description of Signs] 11 Underlying insulating layer or silicon substrate 12 Lower metal silicide layer 13 Metal layer 14 Upper metal silicide layer 15 Mask material

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/3213 H01L 21/3205 H01L 21/60 H01L 21/3065

Claims (1)

(57) [Claim 1] A wiring comprises a lower metal silicide layer on an insulating layer, a metal layer on the lower metal silicide layer, and an upper metal silicide layer on the metal layer. Forming a mask for selectively removing the wiring, plasma-etching the upper metal silicide layer and the metal layer while leaving the lower metal silicide layer, and then forming the mask Ashing and plasma etching of the upper metal silicide layer and the lower metal silicide layer are simultaneously performed in the same processing chamber.