KR0150751B1 - Method for removing remaining polysilicon - Google Patents
Method for removing remaining polysilicon Download PDFInfo
- Publication number
- KR0150751B1 KR0150751B1 KR1019950019154A KR19950019154A KR0150751B1 KR 0150751 B1 KR0150751 B1 KR 0150751B1 KR 1019950019154 A KR1019950019154 A KR 1019950019154A KR 19950019154 A KR19950019154 A KR 19950019154A KR 0150751 B1 KR0150751 B1 KR 0150751B1
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- polysilicon
- film
- layer
- insulating
- forming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
본 발명은 단차를 갖는 소정의 하부층이 형성된 상태의 웨이퍼 상에 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막 상에 제1 절연막을 형성하는 단계; 상기 제1 절연막 및 폴리실리콘막을 동일 마스크를 사용하여 차례로 건식식각하는 단계; 전체구조 상부에 제2절연막을 형성하는 단계; 상기 제2 절연막을 비등방성 전면식각하는 단계; 및 제1 절연막 및 제2절연막과 상기 폴리실리콘막 간의 식각선택비가 우수한 습식식각 용액으로 상기 폴리실리콘막의 패터닝시 하부층의 단차가 심한 부위에 발생한 잔류 폴리실리콘을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 하는 잔류 폴리실리콘 제거 방법에 관한 것으로, 게이트 산화막과 같은 폴리실리콘막의 하부층에 손상을 주는 것을 방지하여 소자의 신뢰성 향상 및 제조 수율을 향상시키는 효과가 있다.The present invention provides a method for forming a polysilicon film on a wafer in which a predetermined lower layer having a step is formed; Forming a first insulating film on the polysilicon film; Sequentially etching the first insulating film and the polysilicon film using the same mask; Forming a second insulating film on the entire structure; Anisotropic full surface etching of the second insulating layer; And removing the residual polysilicon generated in a region having a high level of step difference during the patterning of the polysilicon layer with a wet etching solution having an excellent etching selectivity between the first insulating layer and the second insulating layer and the polysilicon layer. The present invention relates to a method for removing residual polysilicon, which is effective in preventing damage to an underlying layer of a polysilicon film such as a gate oxide film, thereby improving device reliability and manufacturing yield.
Description
제1a도 내지 제1e도는 본 발명의 일실시예에 따른 폴리실리콘막 패턴 형성 공정도.1a to 1e is a polysilicon film pattern forming process according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘 기판 12 : 필드 산화막11: silicon substrate 12: field oxide film
13, 15, 17 : 산화막 14 : 폴리실리콘막13, 15, 17: oxide film 14: polysilicon film
16 : 감광막 패턴 14' : 잔류 폴리실리콘16: photosensitive film pattern 14 ': residual polysilicon
17' : 스페이서 산화막17 ': spacer oxide
본 발명은 반도체 소자 제조 공정중 폴리실리콘막 식각공정후, 단차가 심한 기판 상에 잔류하는 잔류 폴리실리콘(Poly Stringer)을 제거하는 공정에 관한 것이다.The present invention relates to a process of removing residual polysilicon (Poly Stringer) remaining on the substrate having a high level of step after the polysilicon film etching process in the semiconductor device manufacturing process.
일반적으로, 반도체 소자가 점차 고집적화 되어감에 따라 기판의 단차는 더욱 심하게 형성되고, 이에따라 공정상의 문제점이 다량 발생하게 된다.In general, as the semiconductor devices are increasingly integrated, the steps of the substrate are more severely formed, and thus, a large amount of process problems occur.
특히, 폴리실리콘막을 패턴닝 하기 위하여 식각공정을 수행하였을 때, 기판의 단차가 심한 부분에서는 제거되어야할 폴리실리콘이 제거되지 않고 잔류하게 됨으로, 과도식각(over etching)을 실시하여야 한다.In particular, when the etching process is performed to pattern the polysilicon film, the polysilicon to be removed remains in the region where the step difference is severe, so overetching should be performed.
그러나, 반도체 소자의 고집적화로 인해 기판의 단차가 매우 심해진 곳에서는 과도식각을 실시하여도 잔류 폴리실리콘이 형성되며, 남아있는 잔류 폴리실리콘이 브리지(bridge)를 유발하여 소자 특성에 악영향을 미칠뿐만 아니라, 과도식각시 폴리실리콘막의 하부층(underlayer)에 손상(damage)을 주게되어 역시 소자에 악영향을 미치게 된다.However, in the case where the step height of the substrate becomes very severe due to the high integration of the semiconductor device, residual polysilicon is formed even after excessive etching, and the remaining polysilicon causes a bridge to adversely affect the device characteristics. In case of overetching, damage is caused to the underlayer of the polysilicon film, which also adversely affects the device.
상기 문제점을 해결하기 위하여 안출된 본 발명은 기판의 단차가 심한 지역의 잔류 폴리실리콘막을 충분히 제거하는 동시에 폴리실리콘막 하부층의 손상을 방지하는 잔류 폴리실리콘 제거 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a method for removing residual polysilicon that sufficiently removes the residual polysilicon film in a region where the step height is severe and prevents damage to the polysilicon underlayer.
상기 목적을 달성하기 위한 본 발명은 단차를 갖는 소정의 하부층이 형성된 상태의 웨이퍼 상에 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘막 상에 제1 절연막을 형성하는 단계; 상기 제1 절연막 및 폴리실리콘막을 동일 마스크를 사용하여 차례로 건식식각하는 단계; 전체구조 상부에 제2절연막을 형성하는 단계; 상기 제2 절연막을 비등방성 전면식각하는 단계; 및 제1 절연막 및 제2절연막과 상기 폴리실리콘막간의 습식식각으로 상기 폴리실리콘막의 패터닝시 하부층의 단차가 심한 부위에 발생한 잔류 폴리실리콘을 제거하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is a step of forming a polysilicon film on the wafer in a state where a predetermined lower layer having a step; Forming a first insulating film on the polysilicon film; Sequentially etching the first insulating film and the polysilicon film using the same mask; Forming a second insulating film on the entire structure; Anisotropic full surface etching of the second insulating layer; And removing residual polysilicon generated in a region having a high step difference when the polysilicon layer is patterned by wet etching between the first insulating layer, the second insulating layer, and the polysilicon layer.
이하, 첨부된 도면을 참조하여 본 발명의 일실시예를 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;
제1a도 내지 제1e도는 본 발명의 일실시예에 따른 폴리실리콘막 패턴 형성 공정도로서, 먼저, 제1a도는 실리콘 기판(11)상에 소자분리막인 필드산화막(12)을 형성하고, 산화막(13), 폴리실리콘막(14), 산화막(또는 질화막, 15)을 차례로 형성한후, 사진식각공정에 의해 폴리실리콘막 패턴 마스크인 감광막 패턴(16)을 형성한 상태를 나타낸다. 이때, 폴리실리콘막(14)상의 산화막(15)은 이후의 스페이서 형성공정시 폴리실리콘막 상부 표면을 보호하는 역할을 하게 된다.1A to 1E are process charts for forming a polysilicon film pattern according to an embodiment of the present invention. First, FIG. 1A shows a field oxide film 12 as an isolation layer on a silicon substrate 11, and then an oxide film 13 ), The polysilicon film 14 and the oxide film (or nitride film) 15 are sequentially formed, and then the photosensitive film pattern 16 serving as the polysilicon film pattern mask is formed by a photolithography process. At this time, the oxide film 15 on the polysilicon film 14 serves to protect the upper surface of the polysilicon film during the subsequent spacer formation process.
이어서, 제1b도와 같이 감광막 패턴(16)을 식각장벽으로 산화막(15)과 폴리실리콘막(14)을 건식식각하여 패턴을 형성한 후, 감광막 패턴(16)을 제거한다. 이때 단차(필드산화막에 의한 단차)가 심한 지역은 폴리실리콘 식각시의 오버식각에도 불구하고 폴리실리콘이 완전히 제거되지 않고 남아있게 되어 잔류 폴리실리콘(폴리스트링거, 14'))이 형성된다.Subsequently, as shown in FIG. 1B, the oxide film 15 and the polysilicon film 14 are dry-etched using the photosensitive film pattern 16 as an etch barrier, and then the photosensitive film pattern 16 is removed. At this time, the region with a high level of step difference due to the field oxide film is left without polysilicon being completely removed despite the over-etching during polysilicon etching, thereby forming residual polysilicon (Polyringer, 14 ').
이어서, 제1c도와 같이 폴리실리콘막(14) 측벽에 스페이서를 형성하기 위해 스페이서용 산화막(또는 질화막, 17)을 증착한 상태를 나타내고 있다.Next, as shown in FIG. 1C, the spacer oxide film (or nitride film 17) is deposited to form a spacer on the sidewall of the polysilicon film 14.
이어서, 제1d도는 비등방성 전면식각으로 상기 산화막ㄹ(17)을 식각하여 스페이서 산화막(17')를 형성한 상태를 나타낸 것으로, 스페이서 형성시 오버식각을 통해서 잔류 폴리실리콘(14')상의 산화막을 완전히 제거한다.Next, FIG. 1d illustrates a state in which the spacer oxide layer 17 'is formed by etching the oxide layer 17 by anisotropic front etching. An oxide layer on the residual polysilicon 14' is formed through overetching during spacer formation. Remove it completely.
끝으로, 제1e도는 산화막(또는 질화막) 대 폴리실리콘의 식각선택비(etch selectivity)가 매우 높은 습식식각용액인 암모니아수(NH4OH + H2O)용액을 사용하여 하부층인 산화막(13)에 손상을 주지않고 잔류 폴리실리콘(14')을 제거한 상태를 나타낸다. 이때, 폴리실리콘막(14) 상부 및 측벽은 산화막ㄹ(15) 및 산화막 스페이서(17')가 보호하게 된다.Finally, FIG. 1E is a bottom layer of the oxide layer 13 using ammonia water (NH 4 OH + H 2 O) solution, which is a wet etching solution having a very high etch selectivity of an oxide film (or nitride film) to polysilicon. It shows the state which removed the residual polysilicon 14 'without damaging. At this time, the oxide film 15 and the oxide film spacer 17 'are protected on the upper and sidewalls of the polysilicon film 14.
암모니아수를 이용한 습식식각공정에서 산화막 또는 질화막과 폴리실리콘의 식각선택비는 공정조건에 따라 변화하는데 주로 NH4OH와 H2O의 혼합비율 그리고 사용 온도에 따라서 변화한다. 일예로 5NH4OH + H2O 혼합액일 경우 85℃의 온도에서는 산화막 대 폴리실리콘막의 식각선택비는 1:100 정도가 된다.In the wet etching process using ammonia water, the etching selectivity of the oxide film or the nitride film and the polysilicon varies depending on the process conditions, and mainly depends on the mixing ratio of NH 4 OH and H 2 O and the operating temperature. For example, in the case of the 5NH 4 OH + H 2 O mixed solution, the etching selectivity of the oxide film to the polysilicon film is about 1: 100 at a temperature of 85 ° C.
따라서, 사용하는 용도에 따라서 NH4OH와 H2O 용액의 혼합비율과 사용 온도를 선택하면 된다.Thus, according to the using purpose may be selected for the mixing ratio and the temperature of the NH 4 OH and H 2 O solution.
이상, 상기 설명한 바와같이 이루어지는 본 발명은 산화막(또는 질화막)을 폴리실리콘막 패턴은 보호한 상태에서, 산화막(또는 질화막)과 폴리실리콘간의 높은 습식식각공정을 이용해서 잔류 폴리실리콘막을 제거하는 것으로, 공정이 간단하고, 식각선택비가 높기 때문에 게이트 산화막과 같은 폴리실리콘막의 하부층에 손상을 주는 것을 방지하여 소자의 신뢰성 향상 및 제조 수율을 향상시키는 효과가 있다.As described above, the present invention made as described above removes the residual polysilicon film by using a high wet etching process between the oxide film (or nitride film) and polysilicon while the oxide film (or nitride film) is protected by the polysilicon film pattern. Since the process is simple and the etching selectivity is high, it is possible to prevent damage to the lower layer of the polysilicon film such as the gate oxide film, thereby improving the reliability of the device and the manufacturing yield.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950019154A KR0150751B1 (en) | 1995-06-30 | 1995-06-30 | Method for removing remaining polysilicon |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950019154A KR0150751B1 (en) | 1995-06-30 | 1995-06-30 | Method for removing remaining polysilicon |
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| Publication Number | Publication Date |
|---|---|
| KR970003641A KR970003641A (en) | 1997-01-28 |
| KR0150751B1 true KR0150751B1 (en) | 1998-12-01 |
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| KR1019950019154A KR0150751B1 (en) | 1995-06-30 | 1995-06-30 | Method for removing remaining polysilicon |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100489519B1 (en) * | 2002-09-07 | 2005-05-16 | 동부아남반도체 주식회사 | Method for manufacturing control gate etch in semiconductor device |
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1995
- 1995-06-30 KR KR1019950019154A patent/KR0150751B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100489519B1 (en) * | 2002-09-07 | 2005-05-16 | 동부아남반도체 주식회사 | Method for manufacturing control gate etch in semiconductor device |
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| KR970003641A (en) | 1997-01-28 |
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