KR100929625B1 - Method for forming damascene pattern of semiconductor device - Google Patents

Method for forming damascene pattern of semiconductor device Download PDF

Info

Publication number
KR100929625B1
KR100929625B1 KR1020020027007A KR20020027007A KR100929625B1 KR 100929625 B1 KR100929625 B1 KR 100929625B1 KR 1020020027007 A KR1020020027007 A KR 1020020027007A KR 20020027007 A KR20020027007 A KR 20020027007A KR 100929625 B1 KR100929625 B1 KR 100929625B1
Authority
KR
South Korea
Prior art keywords
pattern
forming
insulating film
semiconductor device
mixed solution
Prior art date
Application number
KR1020020027007A
Other languages
Korean (ko)
Other versions
KR20030089564A (en
Inventor
최재성
Original Assignee
매그나칩 반도체 유한회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 매그나칩 반도체 유한회사 filed Critical 매그나칩 반도체 유한회사
Priority to KR1020020027007A priority Critical patent/KR100929625B1/en
Publication of KR20030089564A publication Critical patent/KR20030089564A/en
Application granted granted Critical
Publication of KR100929625B1 publication Critical patent/KR100929625B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Abstract

본 발명은 포토 재공정을 용이하게 할 수 있는 반도체 소자의 다마신 패턴 형성방법에 관한 것으로, 반도체 기판상에 배리어막과 절연막을 순차로 형성하는 단계; 상기 절연막을 선택적으로 제거하여 절연막 패턴1을 형성하는 단계; 상기 절연막 패턴1의 내면을 포함한 절연막 패턴1 상면에 보호막을 형성하는 단계; 상기 절연막 패턴1을 선택적으로 제거하여 절연막 패턴2를 형성하는 단계; 상기 보호막을 제거하는 단계를 포함하며, 별도의 막으로 절연막을 보호하므로 트렌치 형성 공정중 포토 재공정(Photo Rework)을 용이하게 실시할 수 있게 되고, 이로 인해 유전상수의 열화 현상을 제거할 수 있어 소자의 특성 저하를 미연에 방지할 수 있는 효과가 있는 것이다.The present invention relates to a method for forming a damascene pattern of a semiconductor device that can facilitate a photo reprocessing process, the method comprising: sequentially forming a barrier film and an insulating film on a semiconductor substrate; Selectively removing the insulating film to form an insulating film pattern 1; Forming a protective film on an upper surface of the insulating film pattern 1 including the inner surface of the insulating film pattern 1; Selectively removing the insulating film pattern 1 to form an insulating film pattern 2; It includes the step of removing the protective film, and since the insulating film is protected by a separate film it is possible to easily perform the Photo Rework during the trench forming process, thereby eliminating the deterioration of the dielectric constant There is an effect that can prevent the deterioration of the device characteristics in advance.

Description

반도체 소자의 다마신 패턴 형성방법{METHOD FOR FORMING DAMASCENE PATTERN IN SEMICONDUCTOR DEVICE}Method for forming damascene pattern of semiconductor device {METHOD FOR FORMING DAMASCENE PATTERN IN SEMICONDUCTOR DEVICE}

도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 다마신 패턴 형성방법을 설명하기 위한 공정별 단면도.1A to 1D are cross-sectional views illustrating processes for forming a damascene pattern of a semiconductor device according to the related art.

도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 다마신 패턴 형성방법을 설명하기 위한 공정별 단면도.2A to 2E are cross-sectional views for each process for explaining a method for forming a damascene pattern of a semiconductor device according to the present invention.

- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-

100; 반도체 기판 110; 배리어막100; A semiconductor substrate 110; Barrier film

120; 절연막 120a; 절연막 패턴1120; Insulating film 120a; Insulation pattern 1

120b; 절연막 패턴2 140; 보호막120b; Insulating film pattern 2 140; Shield

200; 비아홀 220; 트렌치200; Via hole 220; Trench

본 발명은 반도체 소자의 다마신 패턴 형성방법에 관한 것으로, 보다 상세하게는 트렌치 포토 공정중 포토 재공정을 용이하게 할 수 있는 반도체 소자의 다마신 패턴 형성방법에 관한 것이다. The present invention relates to a method for forming a damascene pattern of a semiconductor device, and more particularly, to a method for forming a damascene pattern of a semiconductor device capable of facilitating a photo reprocessing process in a trench photo process.                         

최근 반도체 소자가 집적화되고 공정 기술력이 향상되면서 소자의 동작속도나 저항, 금속간의 기생용량 등의 특성을 개선시키기 위한 일환으로 기존의 알루미늄(Al) 배선 대신에 구리(Cu) 배선 공정이 제안되었다. 또한, 절연막으로 기존의 산화막 대신 저유전 상수(Low-k) 물질이 차세대 소자의 배선 공정으로 각광을 받고 있다. Recently, as semiconductor devices have been integrated and process technology has been improved, copper (Cu) wiring processes have been proposed in place of conventional aluminum (Al) wiring as part of improving characteristics of device operation speed, resistance, and parasitic capacitance between metals. In addition, a low dielectric constant (Low-k) material instead of the conventional oxide film as the insulating film is in the spotlight as the wiring process of the next generation device.

하지만, 이러한 구리와 저유전 상수 물질을 이용한 배선 공정의 경우 구리(Cu)의 식각 특성이 매우 열악하다는 문제가 있다. 따라서, 기존의 공정 방식 대신 미합중국특허 제5,635,423호에 개시된 바와 같은 이중 다마신(Dual Damascene) 공정이 구리 배선에 적합한 공정으로 알려져 있다.However, in the wiring process using the copper and low dielectric constant material, there is a problem that the etching characteristics of copper (Cu) are very poor. Therefore, a dual damascene process as disclosed in US Pat. No. 5,635,423 is known as a suitable process for copper wiring instead of the conventional process method.

종래 기술에 따른 반도체 소자의 다마신 패턴 형성방법을 도 1a 내지 도 1d를 참조하여 설명하면 다음과 같다.A method of forming a damascene pattern of a semiconductor device according to the prior art will be described with reference to FIGS. 1A to 1D.

종래 기술에 따른 반도체 소자의 다마신 패턴 형성방법은, 도 1a에 도시된 바와 같이, 먼저 반도체 기판(10)상에 제1절연막(12), 식각 정지층(14) 및 제2절연막(16)을 순차로 형성한다.In the method for forming a damascene pattern of a semiconductor device according to the related art, as shown in FIG. 1A, a first insulating layer 12, an etch stop layer 14, and a second insulating layer 16 are first formed on a semiconductor substrate 10. Are formed sequentially.

그런다음, 도 1b에 도시된 바와 같이, 상기 제2절연막(16)상에 d1의 폭을 가진 제1포토레지스트 패턴(18)을 형성한다. 이어서, 상기 제1포토레지스트 패턴(18)을 마스크로 하는 식각공정으로 상기 식각정지층(14)이 노출될 때까지 제2절연막(16)을 선택적으로 제거하여 제2절연막 패턴(16a)을 형성한다.Then, as shown in FIG. 1B, a first photoresist pattern 18 having a width of d1 is formed on the second insulating layer 16. Subsequently, in the etching process using the first photoresist pattern 18 as a mask, the second insulating layer 16 is selectively removed until the etch stop layer 14 is exposed to form a second insulating layer pattern 16a. do.

이어서, 도 1c에 도시된 바와 같이, 상기 제1포토레지스트 패턴(18)을 제거하고 d2의 폭(d1 폭보다 크다)을 갖는 제2포토레지스트 패턴(20)을 상기 제2절연막 패턴(16a) 상에 형성한다. Subsequently, as shown in FIG. 1C, the first photoresist pattern 18 is removed and a second photoresist pattern 20 having a width of d2 (greater than d1 width) is removed from the second insulating film pattern 16a. Form on the phase.

그다음, 도 1d에 도시된 바와 같이, 상기 제2포토레지스트 패턴(20)을 마스크로 하는 식각공정으로 상기 식각정지층(14)과 제1절연막(12)을 선택적으로 제거한다. Next, as shown in FIG. 1D, the etch stop layer 14 and the first insulating layer 12 are selectively removed by an etching process using the second photoresist pattern 20 as a mask.

상기와 같은 공정, 즉 이중 다마신 공정에 의하여 상기 기판(10)상에는 d1의 폭을 갖는 비아홀(22)과, d2의 폭을 갖는 트렌치(24)가 형성된다.The via hole 22 having a width of d1 and the trench 24 having a width of d2 are formed on the substrate 10 by the above process, that is, a dual damascene process.

그러나, 종래 기술에 따른 반도체 소자의 다마신 패턴 형성방법에 있어서는 다음과 같은 문제점이 있다.However, the method of forming a damascene pattern of a semiconductor device according to the prior art has the following problems.

종래 기술에 있어서는, 비아홀을 형성하기 위한 식각공정 이후 트렌치를 형성하기 위한 포토(Photo) 공정을 실시하는데, 이때 트렌치 형성 공정중 재공정(Rework)을 해야 할 사유가 발생할 경우 절연막이 손상되어 절연막의 유전상수가 열화되는 현상(k-value degradation)이 발생될 수 있다. 따라서, 포토 재공정(Photo Rework)을 실시하기 곤란하게 되는 문제점이 있다.In the prior art, a photo process for forming a trench is performed after an etching process for forming a via hole, and when the reason for reworking occurs during the trench formation process, the insulating film is damaged and the The k-value degradation of the dielectric constant may occur. Therefore, there is a problem that it becomes difficult to perform photo rework.

이에, 본 발명은 상기한 종래 기술상의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 목적은 비아홀 패터닝후 비아홀 측벽에 별도의 보호막을 형성함으로써 트렌치 형성 공정중 포토 재공정(Photo Rework)을 용이하게 할 수 있는 반도체 소자의 다마신 패턴 형성방법을 제공함에 있다.Accordingly, the present invention has been made to solve the above-mentioned problems in the prior art, an object of the present invention is to facilitate photo rework during the trench formation process by forming a separate protective film on the sidewalls of the via holes after via hole patterning. The present invention provides a method for forming a damascene pattern of a semiconductor device.

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 다마신 패턴 형성 방법은, 반도체 기판상에 배리어막과 절연막을 순차로 형성하는 단계; 상기 절연막을 선택적으로 제거하여 절연막 패턴1을 형성하는 단계; 상기 절연막 패턴1의 내면을 포함한 절연막 패턴1 상면에 보호막을 형성하는 단계; 상기 절연막 패턴1을 선택적으로 제거하여 절연막 패턴2를 형성하는 단계; 상기 보호막을 제거하는 단계를 포함하는 것을 특징으로 한다.A method for forming a damascene pattern of a semiconductor device according to the present invention for achieving the above object comprises the steps of sequentially forming a barrier film and an insulating film on a semiconductor substrate; Selectively removing the insulating film to form an insulating film pattern 1; Forming a protective film on an upper surface of the insulating film pattern 1 including the inner surface of the insulating film pattern 1; Selectively removing the insulating film pattern 1 to form an insulating film pattern 2; It characterized in that it comprises the step of removing the protective film.

또한, 본 발명에 따른 반도체 소자의 다마신 패턴 형성방법은 절연막을 포토 재공정으로부터 보호할 수 있도록 SiO2, SiN, SiON, Ti 및 TiN으로 이루어진 군으로부터 선택된 어느 하나로 보호막을 형성하는 것을 특징으로 한다.In addition, the method for forming a damascene pattern of a semiconductor device according to the present invention is characterized in that the protective film is formed of any one selected from the group consisting of SiO 2 , SiN, SiON, Ti, and TiN to protect the insulating film from photo reprocessing. .

또한, 본 발명에 따른 반도체 소자의 다마신 패턴 형성방법은 HNO3 + HF + CH3COOH 혼합용액, HF + NH4F 혼합용액, H3PO4 용액, H3 PO4 + HNO3 + CH3COOH + H2O 혼합용액, NH4OH + H2O2 혼합용액, HCl + H2O2 혼합용액 및 H2SO4 + H2O2 혼합용액으로 구성된 군으로부터 선택된 어느 하나의 용액을 사용한 습식 식각 공정으로 보호막을 제거하는 것을 특징으로 한다.In addition, the method for forming a damascene pattern of a semiconductor device according to the present invention is HNO 3 + HF + CH 3 COOH mixed solution, HF + NH 4 F mixed solution, H 3 PO 4 solution, H 3 PO 4 + HNO 3 + CH 3 COOH + H 2 O mixed solution, NH 4 OH + H 2 O 2 mixed solution, HCl + H 2 O 2 mixed solution and H 2 SO 4 + H 2 O 2 mixed solution using any one selected from the group consisting of The protective film is removed by a wet etching process.

본 발명에 의하면, 비아홀 패터닝후 비아홀 측벽에 보호막을 별도로 형성함으로써 트렌치 형성 공정중 포토 재공정(Photo Rework)을 용이하게 실시할 수 있게 된다.According to the present invention, after the via hole patterning, a protective film is separately formed on the sidewalls of the via holes to facilitate photo rework during the trench forming process.

이하, 본 발명에 따른 반도체 소자의 다마신 패턴 형성방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a method for forming a damascene pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명에 따른 반도체 소자의 다마신 패턴 형성방법을 설명하기 위한 공정별 단면도이다.2A to 2E are cross-sectional views illustrating processes for forming a damascene pattern of a semiconductor device according to the present invention.

본 발명에 따른 반도체 소자의 다마신 패턴 형성방법은, 도 2a에 도시된 바와 같이, 먼저 실리콘(Si)과 같은 반도체 원소 등으로 구성된 반도체 기판(100) 상에 예를 들어 구리(Cu) 등으로 배리어막(110)을 형성한다. 그런다음, 상기 배리어막(110) 상에 절연막(120)을 형성한다. 이때, 충분한 절연 역할을 다하기 위하여 바람직하게는 저유전상수 물질, 더욱 바람직하게는 유전상수가 3이하인 물질로 절연막(120)을 형성한다.In the method for forming a damascene pattern of a semiconductor device according to the present invention, as shown in FIG. 2A, first, for example, copper (Cu) or the like is formed on a semiconductor substrate 100 composed of a semiconductor element such as silicon (Si). The barrier film 110 is formed. Then, an insulating film 120 is formed on the barrier film 110. In this case, in order to fulfill a sufficient insulating role, the insulating film 120 is preferably formed of a low dielectric constant material, more preferably, a material having a dielectric constant of 3 or less.

그다음, 도 2b에 도시된 바와 같이, 상기 절연막(120) 상에 L1 길이의 폭을 가진 포토레지스트 패턴(130)을 형성한다. 그런다음, 상기 포토레지스트 패턴(130)을 마스크로 하는 식각 공정으로 상기 배리어막(110)이 노출되도록 상기 절연막(120)을 선택적으로 제거한다. 그결과, L1길이의 폭을 가진 절연막 패턴1 (120a)이 형성된다.Next, as shown in FIG. 2B, a photoresist pattern 130 having a width of L1 length is formed on the insulating layer 120. Thereafter, the insulating layer 120 is selectively removed to expose the barrier layer 110 by an etching process using the photoresist pattern 130 as a mask. As a result, insulating film pattern 1 120a having a width of L1 length is formed.

이어서, 도 2c에 도시된 바와 같이, 상기 절연막 패턴1(120a) 내면을 포함한 절연막 패턴1(120a) 상면에 SiO2, SiN, SiON, Ti 및 TiN으로 이루어진 군으로부터 선택된 어느 하나를 이용하여 보호막(140)을 형성한다. 상기 보호막(140)은 절연막의 유전상수의 열화(Degradation) 없이 포토 재공정(Photo Rework)이 가능하도록 하기 위한 것으로, 약 50Å~500Å 두께로 증착하여 형성한다. Subsequently, as shown in FIG. 2C, the protective layer may be formed by using any one selected from the group consisting of SiO 2 , SiN, SiON, Ti, and TiN on the upper surface of the insulating film pattern 1 120a including the inner surface of the insulating film pattern 1 120a. 140). The passivation layer 140 is intended to enable photo rework without deterioration of the dielectric constant of the insulating layer. The passivation layer 140 is formed by depositing a thickness of about 50 μs to 500 μs.

이와 같이 상기 보호막(140)의 존재로 인하여 상기 절연막 패턴1 (120a)을 손상시키지 않으면서 트렌치 형성을 위한 포토 공정을 필요에 따라 재실시할 수 있게 된다. As such, the photo process for forming the trench may be re-implemented as necessary without damaging the insulating layer pattern 1 120a due to the presence of the protective layer 140.                     

그런다음, 도 2d에 도시된 바와 같이, 소정 형태의 포토레지스트 패턴(미도시)을 마스크로 하는 식각공정으로 절연막 패턴1 (120a)을 선택적으로 제거한다. 이때, 상기 L1 길이의 폭을 가진 절연막 패턴1 (120a) 상부에 L2 길이의 폭이 형성되도록 하여 하부는 L1 길이의 폭을 가지며, 상부는 L2 길이의 폭을 갖는 절연막 패턴2 (120b)를 형성한다. Next, as shown in FIG. 2D, the insulating film pattern 1 120a is selectively removed by an etching process using a photoresist pattern (not shown) of a predetermined type as a mask. At this time, the width of the L2 length is formed on the upper portion of the insulating film pattern 1 (120a) having the width of the L1 length, the lower portion has a width of the L1 length, the upper portion of the insulating film pattern 2 (120b) having a width of the L2 length is formed. do.

한편, 상기 절연막 패턴2 (120b)를 형성하기 위한 식각공정에 의해서 상기 보호막(140)은 그 일부가 제거되어 도면부호 140a로 도시된 바와 같이 상기 절연막 패턴2 (120b) 내측벽에 잔존하게 된다.Meanwhile, a portion of the passivation layer 140 is removed by an etching process for forming the insulation layer pattern 2 (120b), and remains on the inner sidewall of the insulation layer pattern 2 (120b) as shown by reference numeral 140a.

이어서, 도 2e에 도시된 바와 같이, 상기 잔존하는 보호막(140a)을 제거하여 L1 길이의 폭을 갖는 비아홀(200)과 L2 길이의 폭을 갖는 트렌치(220)를 포함하는 패턴, 구체적으로는 이중 다마신(Dual Damascene) 패턴을 완성한다.Subsequently, as shown in FIG. 2E, the remaining protective layer 140a is removed to include a via hole 200 having a width of L1 length and a trench 220 having a width of L2 length. Complete the Damascene pattern.

이때, 상기 보호막(140a)을 제거하는 단계는 소정의 용액을 이용한 습식 식각 공정을 실시한다. 상기 습식 식각 공정에 사용되는 용액은 HNO3 + HF + CH3COOH 혼합용액, HF + NH4F 혼합용액, H3PO4 용액, H3PO4 + HNO3 + CH3COOH + H2O 혼합용액, NH4OH + H2O2 혼합용액, HCl + H2O2 혼합용액 및 H2SO4 + H2O2 혼합용액으로 구성된 군으로부터 어느 하나의 용액을 선택하여 사용한다.In this case, the removing of the protective layer 140a may be performed by a wet etching process using a predetermined solution. The solution used in the wet etching process is HNO 3 + HF + CH 3 COOH mixed solution, HF + NH 4 F mixed solution, H 3 PO 4 solution, H 3 PO 4 + HNO 3 + CH 3 COOH + H 2 O mixed Any one solution is selected from the group consisting of a solution, a NH 4 OH + H 2 O 2 mixed solution, a HCl + H 2 O 2 mixed solution, and a H 2 SO 4 + H 2 O 2 mixed solution.

본 발명의 원리와 정신에 위배되지 않는 범위에서 여러 실시예는 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명할 뿐만 아니라 용이하게 실시할 수 있다. 따라서, 본원에 첨부된 특허청구범위는 이미 상술된 것에 한정되 지 않으며, 하기 특허청구범위는 당해 발명에 내재되어 있는 특허성 있는 신규한 모든 사항을 포함하며, 아울러 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해서 균등하게 처리되는 모든 특징을 포함한다.Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the present invention, and are generally available in the art to which the invention pertains. Includes all features that are treated equally by those with knowledge of

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 다마신 패턴 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the method for forming a damascene pattern of a semiconductor device according to the present invention has the following effects.

본 발명에 있어서는, 별도의 막으로 절연막을 보호하므로 트렌치 형성 공정중 포토 재공정(Photo Rework)을 용이하게 실시할 수 있게 되고, 이로 인해 유전상수의 열화 현상을 제거할 수 있어 소자의 특성 저하를 미연에 방지할 수 있는 효과가 있다.In the present invention, since the insulating film is protected by a separate film, it is possible to easily perform photo rework during the trench formation process, thereby eliminating the deterioration of the dielectric constant, thereby reducing the characteristics of the device. There is an effect that can be prevented in advance.

이와 아울러, 안정적인 공정 재현성 유지를 통하여 반도체 소자 개발과 생산 수율을 향상시킬 수 있는 효과도 있다.In addition, the semiconductor device development and production yield can be improved by maintaining stable process reproducibility.

Claims (11)

반도체 기판상에 배리어막과 절연막을 순차로 형성하는 단계;Sequentially forming a barrier film and an insulating film on the semiconductor substrate; 상기 절연막을 선택적으로 제거하여 절연막 패턴1을 형성하는 단계;Selectively removing the insulating film to form an insulating film pattern 1; 상기 절연막 패턴1의 내면을 포함한 절연막 패턴1 상면에 보호막을 형성하는 단계;Forming a protective film on an upper surface of the insulating film pattern 1 including the inner surface of the insulating film pattern 1; 상기 절연막 패턴1을 선택적으로 제거하여 절연막 패턴2를 형성하는 단계; 및Selectively removing the insulating film pattern 1 to form an insulating film pattern 2; And 상기 보호막을 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 다마신 패턴 형성방법.Removing the protective layer; and forming a damascene pattern of the semiconductor device. 제1항에 있어서,The method of claim 1, 상기 절연막은 저유전상수 물질로 형성되는 것을 특징으로 하는 반도체 소자의 다마신 패턴 형성방법.The insulating layer is a damascene pattern forming method of the semiconductor device, characterized in that formed of a low dielectric constant material. 제2항에 있어서,The method of claim 2, 상기 절연막의 유전상수는 3이하인 것을 특징으로 하는 반도체 소자의 다마신 패턴 형성방법.The dielectric constant of the insulating film is a method of forming a damascene pattern of a semiconductor device, characterized in that less than three. 제1항에 있어서,The method of claim 1, 상기 보호막은 SiO2, SiN, SiON, Ti 및 TiN으로 이루어진 군으로부터 선택된 어느 하나로 형성되는 것을 특징으로 하는 반도체 소자의 다마신 패턴 형성방법.The protective film is a damascene pattern forming method of a semiconductor device, characterized in that formed of any one selected from the group consisting of SiO 2 , SiN, SiON, Ti and TiN. 제1항에 있어서,The method of claim 1, 상기 보호막은 50Å~500Å 두께로 형성되는 것을 특징으로 하는 반도체 소자의 다마신 형성방법.The protective film is a damascene method for forming a semiconductor device, characterized in that formed in 50 ~ 500Å thickness. 제1항에 있어서,The method of claim 1, 상기 보호막을 제거하는 단계는 HNO3 + HF + CH3COOH 혼합용액, HF + NH4F 혼합용액, H3PO4 용액, H3PO4 + HNO3 + CH3COOH + H2O 혼합용액, NH4OH + H2O2 혼합용액, HCl + H2O2 혼합용액 및 H2SO4 + H2O2 혼합용액으로 구성된 군으로부터 선택된 어느 하나의 용액을 사용한 습식 식각 공정으로 진행하는 것을 특징으로 하는 반도체 소자의 다마신 형성방법.Removing the protective layer is a mixture of HNO 3 + HF + CH 3 COOH, HF + NH 4 F mixed solution, H 3 PO 4 solution, H 3 PO 4 + HNO 3 + CH 3 COOH + H 2 O mixed solution, The wet etching process using any one selected from the group consisting of NH 4 OH + H 2 O 2 mixed solution, HCl + H 2 O 2 mixed solution and H 2 SO 4 + H 2 O 2 mixed solution A damascene formation method of a semiconductor device. 반도체 기판상에 배리어막과 절연막을 순차로 형성하는 단계;Sequentially forming a barrier film and an insulating film on the semiconductor substrate; 상기 절연막을 선택적으로 제거하여 비아홀 패턴을 형성하는 단계;Selectively removing the insulating layer to form a via hole pattern; 상기 비아홀 패턴 내면에 SiO2, SiN, SiON, Ti 및 TiN으로 이루어진 군으로부터 선택된 어느 하나로 보호막을 형성하는 단계;Forming a protective film on the inner surface of the via hole pattern using any one selected from the group consisting of SiO 2 , SiN, SiON, Ti, and TiN; 상기 절연막을 선택적으로 제거하여 트렌치 패턴을 형성하는 단계; 및Selectively removing the insulating layer to form a trench pattern; And 상기 보호막을 소정의 화학용액을 사용한 습식 식각 공정으로 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 다마신 패턴 형성방법.Removing the protective film by a wet etching process using a predetermined chemical solution. 제7항에 있어서,The method of claim 7, wherein 상기 절연막은 저유전상수 물질로 형성되는 것을 특징으로 하는 반도체 소자의 다마신 패턴 형성방법.The insulating layer is a damascene pattern forming method of the semiconductor device, characterized in that formed of a low dielectric constant material. 제8항에 있어서,The method of claim 8, 상기 절연막의 유전상수는 3이하인 것을 특징으로 하는 반도체 소자의 다마신 패턴 형성방법.The dielectric constant of the insulating film is a method of forming a damascene pattern of a semiconductor device, characterized in that less than three. 제7항에 있어서,The method of claim 7, wherein 상기 보호막은 50Å~500Å 두께로 형성되는 것을 특징으로 하는 반도체 소자의 다마신 형성방법.The protective film is a damascene method for forming a semiconductor device, characterized in that formed in 50 ~ 500Å thickness. 제7항에 있어서,The method of claim 7, wherein 상기 화학용액은 HNO3 + HF + CH3COOH 혼합용액, HF + NH4F 혼합용액, H 3PO4 용액, H3PO4 + HNO3 + CH3COOH + H2O 혼합용액, NH4OH + H2O2 혼합용액, HCl + H2O2 혼합용액 및 H2SO4 + H2O2 혼합용액으로 구성된 군으로부터 선택된 어느 하나인 것을 특징으로 하는 반도체 소자의 다마신 형성방법.The chemical solution is HNO 3 + HF + CH 3 COOH mixed solution, HF + NH 4 F mixed solution, H 3 PO 4 solution, H 3 PO 4 + HNO 3 + CH 3 COOH + H 2 O mixed solution, NH 4 OH + H 2 O 2 mixed solution, HCl + H 2 O 2 mixed solution and H 2 SO 4 + H 2 O 2 mixed solution is a method for forming a damascene semiconductor device, characterized in that any one selected from the group consisting of.
KR1020020027007A 2002-05-16 2002-05-16 Method for forming damascene pattern of semiconductor device KR100929625B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020020027007A KR100929625B1 (en) 2002-05-16 2002-05-16 Method for forming damascene pattern of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020020027007A KR100929625B1 (en) 2002-05-16 2002-05-16 Method for forming damascene pattern of semiconductor device

Publications (2)

Publication Number Publication Date
KR20030089564A KR20030089564A (en) 2003-11-22
KR100929625B1 true KR100929625B1 (en) 2009-12-03

Family

ID=32383083

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020020027007A KR100929625B1 (en) 2002-05-16 2002-05-16 Method for forming damascene pattern of semiconductor device

Country Status (1)

Country Link
KR (1) KR100929625B1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100875057B1 (en) * 2002-07-10 2008-12-19 매그나칩 반도체 유한회사 How to form a dual damascene pattern
KR100824623B1 (en) * 2006-12-05 2008-04-25 동부일렉트로닉스 주식회사 Method for forming semiconductor device
KR100935196B1 (en) * 2008-01-18 2010-01-06 주식회사 하이닉스반도체 Method of manufacturing metal wiring of semiconductor device
KR101029391B1 (en) 2009-06-17 2011-04-14 주식회사 하이닉스반도체 Method for forming patterns of semicondoctor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010098409A (en) * 2000-04-17 2001-11-08 포만 제프리 엘 Protective hardmask for producing interconnect structures

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010098409A (en) * 2000-04-17 2001-11-08 포만 제프리 엘 Protective hardmask for producing interconnect structures

Also Published As

Publication number Publication date
KR20030089564A (en) 2003-11-22

Similar Documents

Publication Publication Date Title
KR100433091B1 (en) Method for forming metal line using damascene process
US6913994B2 (en) Method to form Cu/OSG dual damascene structure for high performance and reliable interconnects
JP3501280B2 (en) Manufacturing method of semiconductor device
KR940012660A (en) Manufacturing Method of Semiconductor Device
US6274471B1 (en) Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask technique
KR100929625B1 (en) Method for forming damascene pattern of semiconductor device
US5994779A (en) Semiconductor fabrication employing a spacer metallization technique
KR100325600B1 (en) a manufacturing method of contact holes of semiconductor devices
US6703297B1 (en) Method of removing inorganic gate antireflective coating after spacer formation
US6555397B1 (en) Dry isotropic removal of inorganic anti-reflective coating after poly gate etching
KR100596899B1 (en) Method for manufacturing semiconductor device
KR20060122578A (en) Method for forming hard mask in semiconductor memory device
KR100587036B1 (en) Contact formation method of semiconductor device
KR0150751B1 (en) Method for removing remaining polysilicon
KR100191708B1 (en) Forming method for metal wiring in semiconductor device
KR20000045442A (en) Fabrication method of contacts for semiconductor device
KR0168120B1 (en) Forming method of tungsten plug
KR100597090B1 (en) Method for fabricating gate electrode of semiconductor device
KR100680420B1 (en) Method for forming metal line
KR100539447B1 (en) Method of forming a metal line in semiconductor device
KR100846991B1 (en) Fabrication method of semiconductor device
KR100456421B1 (en) Method of manufacturing a semiconductor device
KR100917099B1 (en) Method of forming a dual damascene pattern
KR0154190B1 (en) Formation method of tungsten plug in semiconductor device
KR20070064965A (en) Method for forming micro-pattern of semiconductor device

Legal Events

Date Code Title Description
N231 Notification of change of applicant
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application
J201 Request for trial against refusal decision
S901 Examination by remand of revocation
GRNO Decision to grant (after opposition)
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20121022

Year of fee payment: 4

FPAY Annual fee payment

Payment date: 20131017

Year of fee payment: 5

FPAY Annual fee payment

Payment date: 20141020

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee