JPS62113421A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62113421A
JPS62113421A JP25262585A JP25262585A JPS62113421A JP S62113421 A JPS62113421 A JP S62113421A JP 25262585 A JP25262585 A JP 25262585A JP 25262585 A JP25262585 A JP 25262585A JP S62113421 A JPS62113421 A JP S62113421A
Authority
JP
Japan
Prior art keywords
film
titanium
oxide film
formation
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25262585A
Other languages
Japanese (ja)
Inventor
Shigeya Mori
森 重哉
Toshinobu Araki
新木 俊宣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP25262585A priority Critical patent/JPS62113421A/en
Publication of JPS62113421A publication Critical patent/JPS62113421A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To allow electrodes to remain stable in their electric characteristics during a high-temperature treatment by a method wherein a high-melting metal film is formed on an insulating film and a contact hole provided therein, a high-melting metal nitride film is formed on the high-melting metal film, heat treatment is accomplished in an oxygen atmosphere for the formation of a thin oxide film on the metal nitride film, and then wiring metal is provided on the thin oxide film. CONSTITUTION:A prescribed impurity is diffused into a P-type silicon substrate 1 for the formation of an N<+> type diffusion layer 2, and then a silicon oxide film 3 is formed by selectively removing the silicon oxide film 3 from the diffusion layer 2 for the formation of a contact hole in the silicon oxide film 3. Next, titanium is deposited on the entire surface for the formation of a titanium film 4, whereon a titanium nitride film 5 is deposited. The substrate 1 is then subjected to heating in an oxygen atmosphere for the formation of an titanium oxide film 6 on the surface of the titanium nitride film 5. Next, an aluminum wiring film 7 is formed to cover the entirely of the titanium oxide film 6. A wiring pattern is formed when the aluminum wiring film 7, oxide film 6, titanium nitride film 5, and then titanium film 4 are subjected in succession to etching.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置の製造方法に係り、特に配線層の
形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a wiring layer.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

一般に、半導体基体上に形成される配線金属としては、
アルミニウム又はアルミニウムーシリコン合金が用いら
れている。しかし、アルミニウムを配線金属として用い
た場合1通常の素子製造工程における熱処理にともなう
温度上昇により、浅い不純物拡散層を有するトランジス
タまたはICにおいては、アルミニウムと基板シリコン
と反応によるアルミニウムの基板シリコンへの侵入がこ
の浅い拡散層による接合を破壊する恐れがある。
In general, wiring metals formed on semiconductor substrates include:
Aluminum or aluminum-silicon alloys are used. However, when aluminum is used as a wiring metal, 1. Due to the temperature rise associated with heat treatment in the normal device manufacturing process, in transistors or ICs with shallow impurity diffusion layers, aluminum may react with the substrate silicon, causing aluminum to invade the substrate silicon. There is a risk that the junction formed by this shallow diffusion layer will be destroyed.

また、アルミニウムーシリコンを配線金属として用いた
場合、アルミニウム中に固溶限界以上含まれている過剰
シリコンが、素子製造工程中の昇温、冷却により、配線
中やコンタクトホール内に析出してくる。析出シリコン
は高抵抗であり、特にN型のコンタクトホールの場合、
析出シリコンはアルミ、ニウムがドープされたP型であ
るため非常に高抵抗となる。
In addition, when aluminum-silicon is used as a wiring metal, excess silicon contained in aluminum exceeding the solid solubility limit precipitates in the wiring and contact holes due to temperature rise and cooling during the element manufacturing process. . Precipitated silicon has high resistance, especially for N-type contact holes.
Since the precipitated silicon is P-type doped with aluminum and nium, it has extremely high resistance.

上記の如き問題を解決する手段として、従来アルミニウ
ム配線層と基板シリコンとの間に、アルミニウムと基板
シリコンとの反応を抑えるために、チタン、モリブデン
、タングステン等の高融点金属又はその窒化物又は硅化
物層を設けることが行なわれている。
As a means to solve the above problems, conventionally, in order to suppress the reaction between aluminum and the substrate silicon, high melting point metals such as titanium, molybdenum, tungsten, or their nitrides or silicides are used between the aluminum wiring layer and the substrate silicon. It is practiced to provide a material layer.

しかし、この方法においても素子製造工程における熱処
理により配線材料であるアルミニウムと、高融点金属お
よび基板シリコンとの反応を十分押えることはできず、
電極特性の安定性に対して依然問題があった。
However, even with this method, it is not possible to sufficiently suppress the reaction between the wiring material aluminum and the high melting point metal and substrate silicon due to heat treatment in the element manufacturing process.
There were still problems with the stability of electrode properties.

〔発明の目的〕[Purpose of the invention]

本発明は上記の様な従来技術の欠点を改良したもので、
安定で低抵抗のコンタクト電極を有する半導体装置を提
供することを目的とする。
The present invention improves the drawbacks of the prior art as described above.
An object of the present invention is to provide a semiconductor device having a stable and low-resistance contact electrode.

〔発明の概要〕[Summary of the invention]

上記目的を達成せしめるため、本発明の半導体装置の製
造方法によれば、絶縁膜上およびコンタクト開孔部表面
上に高融点金属膜を、さらにその上部に窒化高融点金属
層を形成後、酸素雰囲気(1〜3X10’″”Torr
)中で熱処理(400℃)して窒化金属表面を薄く酸化
し、次に上記酸化膜上に配線金属を形成して配線路を形
成する。
In order to achieve the above object, according to the method of manufacturing a semiconductor device of the present invention, after forming a high melting point metal film on the insulating film and the surface of the contact opening, and further forming a nitride high melting point metal layer on top of the high melting point metal film, Atmosphere (1~3X10'''”Torr
) to thinly oxidize the surface of the metal nitride in a chamber (400° C.), and then a wiring metal is formed on the oxide film to form a wiring path.

〔発明の効果〕 本発明により、アルミニウムと窒化高融点金属及び基板
シリコンとの反応が抑えられ高温熱処理においても安定
した電極特性を維持できる信頼性の高い電極を実現でき
る。
[Effects of the Invention] According to the present invention, it is possible to realize a highly reliable electrode that can suppress the reaction between aluminum, high melting point metal nitride, and substrate silicon, and maintain stable electrode characteristics even during high-temperature heat treatment.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の詳細を一実施例に従って説明する。第1
図〜第4図は1本発明による半導体装置の製造方法の一
実施例を示す工程断面図である。
Hereinafter, details of the present invention will be explained according to one embodiment. 1st
4 to 4 are process cross-sectional views showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

先ず通常の方法によりP型シリコン基体1にP。First, P is applied to a P-type silicon substrate 1 by a conventional method.

As等の所定不純物を拡散してn形の拡散層2を形成す
る0次にシリコン基板1の表面にシリコン酸化膜3を設
け、更にフォトレジスト法により拡散層2上のシリコン
酸化膜3を選択的に除去してシリコン酸化膜3にコンタ
クトホールを設ける。
A predetermined impurity such as As is diffused to form an n-type diffusion layer 2. Next, a silicon oxide film 3 is provided on the surface of the silicon substrate 1, and the silicon oxide film 3 on the diffusion layer 2 is further selected by a photoresist method. A contact hole is provided in the silicon oxide film 3 by removing the contact hole.

(第1図) 次に1通常のスパッタリング装置で全面にチタンをスパ
ッタリングにより堆積し、100〜500人のチタン膜
4を形成する。その後連続して1反応性スパッタリング
によりチタンナイトライド膜5(1000〜2000人
)をチタン膜4の上に堆積する。
(FIG. 1) Next, titanium is deposited on the entire surface by sputtering using an ordinary sputtering device to form a titanium film 4 of 100 to 500 layers. Thereafter, a titanium nitride film 5 (1,000 to 2,000 layers) is successively deposited on the titanium film 4 by one-reactive sputtering.

(第2図) 次に、 この基板1を400℃で約1公租度、酸素雰囲
気(1〜3mTorr)中で加熱処理を行ない、チタン
ナイトライド膜5の表面にTiの酸化膜6(20〜50
人)を形成せしめる。(第3図)次にこの酸化膜上全面
に通常のスパッタリング法により、厚さ8000人のア
ルミニウム配線金属膜7を形成する。その後通常のエツ
チング法によりアルミニウム配線金属膜7とその下の酸
化膜6゜チタンナイトライド膜5.チタン膜4を連続的
にエツチングし配線パターンを形成する。(第4図)こ
のようにシリコン基板上にチタン層4.チタンナイトラ
イド層5.酸化膜層6.アルミニウム配線金属層7の積
層構造にして、チタンナイトライド層5とアルミニウム
配線金属層との間に非常に薄いTiの酸化膜層6を入れ
ることにより、チタンナイトライドとアルミニウムの反
応が抑えられ、さらにはアルミニウムと基板シリコンと
の反応が抑えられることになった。また、この実施例の
様に配線金属として、純アルミニウムを使用することも
可能となった。その場合は、アルミニウムーシリコン合
金を配線に用いたよりも配線が低抵抗となる。
(FIG. 2) Next, this substrate 1 is heat-treated at 400° C. in an oxygen atmosphere (1 to 3 mTorr) to form a Ti oxide film 6 (20 to 3 mTorr) on the surface of the titanium nitride film 5. 50
people). (FIG. 3) Next, an aluminum wiring metal film 7 having a thickness of 8,000 wafers is formed on the entire surface of this oxide film by a conventional sputtering method. Thereafter, the aluminum wiring metal film 7 and the underlying oxide film 6° titanium nitride film 5. The titanium film 4 is continuously etched to form a wiring pattern. (Fig. 4) In this way, a titanium layer 4. Titanium nitride layer 5. Oxide layer 6. By creating a laminated structure of the aluminum wiring metal layer 7 and inserting a very thin Ti oxide film layer 6 between the titanium nitride layer 5 and the aluminum wiring metal layer, the reaction between titanium nitride and aluminum is suppressed. Furthermore, the reaction between aluminum and the silicon substrate was suppressed. Furthermore, it has become possible to use pure aluminum as the wiring metal as in this embodiment. In that case, the wiring will have a lower resistance than when an aluminum-silicon alloy is used for the wiring.

なお、実施例中に用いた高融点金属はチタンに限る必要
がなく、モリブデン、タングステン、タンタル等を用い
ても同様の効果が期待できる。また実施例においてはn
拡散層の場合を例に取ったが、pの場合にも適用できる
。また、配線層もアルミニウムに限らず、アルミニウム
ーシリコン合金であってもよい。また基板1はシリコン
に限らすG a A sで構成してもよいし、SO8構
造であってもよい。
Note that the high melting point metal used in the examples is not limited to titanium, and similar effects can be expected even if molybdenum, tungsten, tantalum, etc. are used. In addition, in the embodiment, n
Although the case of a diffusion layer is taken as an example, it can also be applied to the case of a p layer. Further, the wiring layer is not limited to aluminum, but may also be an aluminum-silicon alloy. Further, the substrate 1 is not limited to silicon, but may be made of GaAs, or may have an SO8 structure.

その他、本発明の主旨を逸脱しない限り種々変形して実
施することができる。
In addition, various modifications can be made without departing from the spirit of the present invention.

以上説明した如く、本発明は基板と配線金属の反応が抑
えられ、低抵抗の配線が実現できる。
As explained above, according to the present invention, the reaction between the substrate and the wiring metal is suppressed, and wiring with low resistance can be realized.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図、第3図及び第4図は本発明の一実施例
を示す製造工程断面図である。図において、 1・・・シリコン半導体基板、2・・・不純物拡散層、
3・・・二酸化シリコン膜、4・・・チタン膜、5・・
・チタンナイトライド膜、6・・・酸化高融点金属膜、
7・・・アルミニウム配線金属膜。 代理人 弁理士 則 近 憲 佑 同  竹花喜久男
FIGS. 1, 2, 3, and 4 are sectional views showing manufacturing steps of an embodiment of the present invention. In the figure, 1... silicon semiconductor substrate, 2... impurity diffusion layer,
3... Silicon dioxide film, 4... Titanium film, 5...
・Titanium nitride film, 6... Oxidized high melting point metal film,
7...Aluminum wiring metal film. Agent Patent Attorney Noriyuki Chika Yudo Kikuo Takehana

Claims (1)

【特許請求の範囲】[Claims] 半導体基板表面に絶縁膜が形成され、その開口部に配線
層が拡散層にコンタクトする半導体装置の製造方法にお
いて、絶縁膜に開口を形成した後、高融点金属膜、次い
で窒化高融点金属膜を被着する工程と、その表面を酸化
して酸化高融点金属膜を形成する工程と、この酸化高融
点金属膜上にアルミニウム系の配線層を形成する工程と
を備えた事を特徴とする半導体装置の製造方法。
In a method for manufacturing a semiconductor device in which an insulating film is formed on the surface of a semiconductor substrate and a wiring layer contacts a diffusion layer in an opening of the semiconductor device, after forming an opening in the insulating film, a high melting point metal film and then a nitride high melting point metal film are formed. A semiconductor characterized by comprising a step of adhering it, a step of oxidizing its surface to form an oxidized high-melting point metal film, and a step of forming an aluminum-based wiring layer on the oxidized high-melting point metal film. Method of manufacturing the device.
JP25262585A 1985-11-13 1985-11-13 Manufacture of semiconductor device Pending JPS62113421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25262585A JPS62113421A (en) 1985-11-13 1985-11-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25262585A JPS62113421A (en) 1985-11-13 1985-11-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62113421A true JPS62113421A (en) 1987-05-25

Family

ID=17239962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25262585A Pending JPS62113421A (en) 1985-11-13 1985-11-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62113421A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0346323A (en) * 1989-07-14 1991-02-27 Mitsubishi Electric Corp Manufacture of highly heat-resistant titanium silicide
US5130274A (en) * 1991-04-05 1992-07-14 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
EP0499249A2 (en) * 1991-02-14 1992-08-19 Fujitsu Limited Method of producing a semiconductor device including a barrier layer
JPH05121357A (en) * 1991-04-29 1993-05-18 Philips Gloeilampenfab:Nv Manufacture of semiconductor device
US5238872A (en) * 1990-12-11 1993-08-24 Samsung Semiconductor, Inc. Barrier metal contact architecture
US5243222A (en) * 1991-04-05 1993-09-07 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
US5290731A (en) * 1991-03-07 1994-03-01 Sony Corporation Aluminum metallization method
US6051490A (en) * 1991-11-29 2000-04-18 Sony Corporation Method of forming wirings
US6197686B1 (en) * 1992-03-03 2001-03-06 Sony Corporation Aluminum metallization by a barrier metal process
US6268290B1 (en) * 1991-11-19 2001-07-31 Sony Corporation Method of forming wirings

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0346323A (en) * 1989-07-14 1991-02-27 Mitsubishi Electric Corp Manufacture of highly heat-resistant titanium silicide
US5238872A (en) * 1990-12-11 1993-08-24 Samsung Semiconductor, Inc. Barrier metal contact architecture
EP0499249A2 (en) * 1991-02-14 1992-08-19 Fujitsu Limited Method of producing a semiconductor device including a barrier layer
US5236869A (en) * 1991-02-14 1993-08-17 Fujitsu Limited Method of producing semiconductor device
US5290731A (en) * 1991-03-07 1994-03-01 Sony Corporation Aluminum metallization method
US5130274A (en) * 1991-04-05 1992-07-14 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
US5243222A (en) * 1991-04-05 1993-09-07 International Business Machines Corporation Copper alloy metallurgies for VLSI interconnection structures
JPH05121357A (en) * 1991-04-29 1993-05-18 Philips Gloeilampenfab:Nv Manufacture of semiconductor device
US6268290B1 (en) * 1991-11-19 2001-07-31 Sony Corporation Method of forming wirings
US6051490A (en) * 1991-11-29 2000-04-18 Sony Corporation Method of forming wirings
US6197686B1 (en) * 1992-03-03 2001-03-06 Sony Corporation Aluminum metallization by a barrier metal process

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