JP2003045983A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To constitute a semiconductor integrated circuit capable of reducing contact resistant of a resistant element and a wiring layer using a cermet based material and assembling an accurate minute thin film high resistant element or the like of a stable resistant value. SOLUTION: A semiconductor device is provided with a semiconductor substrate 11, an SiO2 film 12 provided on the semiconductor substrate 11, a thin film resistant layer 13 provided on the whole face or a part of the SiO2 film 12, and the wiring layer 17 formed selectively on a thin film resistant layer 13. The thin film resistant layer 13 has a resistant element area A used as a resistant element R1 and wiring connection areas B1, B2 connecting the resistant element R1 and the wiring layer 17. The wiring connection areas B1, B2 include the whole formation area of the wiring layer 17 on a thin film resistant layer except for the resistant element area A. Since contact resistance r of the resistant element R1 and the wiring layer 17 can be suppressed very low, influence of the contact resistance r can be excluded from the resistant value of the high resistant element R1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high resistance element incorporated in an integrated circuit and a method of manufacturing the same.
Specifically, a thin film resistance layer having a resistance element region used as a resistance element and a wiring connection region connecting the resistance element and a wiring layer is provided, and a wiring layer formation region on the thin film resistance layer other than the resistance element region. , The contact resistance between the resistance element and the wiring layer can be reduced, and a highly reliable semiconductor device in which a high resistance element having a stable resistance value is incorporated in a transistor circuit can be provided. It was done like this.

[0002]

2. Description of the Related Art In recent years, various metal thin film resistance elements have come to be used in low frequency circuits, high frequency circuits and the like with the multi-functionalization and versatility of semiconductor integrated circuits. In this technical field, it is necessary to reduce the area occupied by the thin film resistance element itself as the semiconductor integrated circuit is reduced in size, and it is easy to process with high resistivity over time or with little temperature dependence and with high accuracy. There is a demand for stable thin film resistance elements.

The types of resistance elements used in the manufacturing process of this kind of semiconductor integrated circuit are roughly classified into diffusion resistance elements, field effect resistance elements, thin film polycrystalline silicon (polySi) resistors, and thin film metals (alloys). ) Resistance elements, thin film metal compound resistance elements, etc.

Diffused resistors and field effect resistors, in particular, have the same parameters that control the resistance value as those that must be optimized for device performance.
It becomes a constraint on the resistance value. Therefore, only a low resistance value can be obtained with a practical diffusion structure of a semiconductor integrated circuit or a field effect resistor. Diffused resistors also have the disadvantage of requiring too much space on the semiconductor integrated circuit, a significant disadvantage if the size of the semiconductor integrated circuit continues to shrink.

The thin film polycrystalline silicon (PolySi) resistance material has a surface energy (level), an interface energy with a bonding layer, the presence of Si dangling bonds (hydrogen adsorption), a crystal defect density, a crystal grain property, and a crystal. There are many factors that constitute the carrier conduction mechanism in polycrystalline silicon, such as grain boundary energy, and the higher the resistance (20 × 10 ³ μΩcm or more), the less stable and reproducible the resistance element becomes.

Further, the thin film polycrystalline silicon resistance material undergoes great fluctuations due to the effects of heat treatment in a plurality of steps. In particular, this kind of resistance material tends to be remarkable on the high resistance side,
It is also known that the resistance accuracy and the temperature coefficient of resistance are as large as 2000 ppm / ° C.

In a thin film metal resistance element, a CrSi-based material (C
Most widely used are rSi, CrSi ₂ , CrSiN, etc., but this CrSi-based material is very easily oxidized, and the patterned resistance film is exposed to an oxygen atmosphere or oxygen plasma in the manufacturing process of the CrSi-based resistor. There are many processes. For this reason, oxidation or deterioration occurs on the surface of the reference resistance film. When the wiring is formed on the reference resistance film whose surface is oxidized or deteriorated, the contact resistance becomes large and becomes unstable.

For example, in a CrSi ₂ type thin film resistance element, the resistance value of CrSi ₂ largely changes at a temperature near 360 ° C., and a heat treatment step is performed after the thin film resistance element is formed until the semiconductor device is completed. Therefore, it is known that the resistance value fluctuates significantly.

Further, the metal / alloy thin film resistance element includes
NiCr alloy resistance and thin-film metals such as Ta, Ti, W, Mo are used, but the resistance is small and the resistance film must be thin to increase the resistivity, resulting in poor thermal stability. It has been known.

A TaN film or T
In many cases, iN film, TiON film, WN film, etc. are used.
A forming method using a chemical reaction (oxidation, nitriding) during film formation is overwhelming, and therefore, it is often impossible to obtain a stable high resistance element with good reproducibility.

Next, a method of forming a resistance element using these resistance materials will be described. FIG. 15 is a cross-sectional view showing a configuration example of the first semiconductor device 10 according to the conventional example.

A semiconductor device 10 shown in FIG. 15 has a thin film resistance element 3 on an insulating film 2 of a semiconductor substrate 1.
The thin film resistance element 3 is formed as follows. First,
A resistance layer such as a TiN film is formed on the entire surface of the insulating film 2 of the semiconductor substrate 1. This is because the thin film resistance element 3 is formed of a metal compound.

Then, the resistance layer is patterned to form TiN.
A film type thin film resistance element 3 is formed. Then, the insulating film 4 for protection is formed on the insulating film 2 including the thin film resistance element 3 (insulating film coating step). After that, the insulating film 4 is selectively opened to form the contact holes 5 and 6 (connection hole forming step). The contact holes 5 and 6 are for connecting the thin film resistance element 3 and the wiring layer 7.

After that, a conductive film is formed on the insulating film 4 including the contact holes 5 and 6. Then, the conductive film is patterned to form the wiring layer 7 (wiring layer film forming step). As a result, the semiconductor device 10 having the thin film resistance element 3 on the semiconductor substrate 1 shown in FIG. 15 is completed. With the TaN film-based thin film resistance element 3, a low resistivity can be obtained with good reproducibility.

In recent years, high resistance elements using a cermet-based resistance material based on a silicon-based insulating material are being introduced into semiconductor devices. Cermet-based resistance material is a composite material of refractory metal material and silicon-based insulating material, and has excellent heat resistance and oxidation resistance, and its ratio makes it possible to achieve high resistance and excellent low resistance. It also has a temperature coefficient of resistance, and it has excellent adhesion and compatibility with silicon-based insulators that are widely used in semiconductor integrated circuits at present, and is one of the most effective materials as a resistance element material to be mounted in semiconductor devices. Is one.

FIG. 16 shows a second semiconductor device 2 according to a conventional example.
It is sectional drawing which shows the structural example of 0. A semiconductor device 20 shown in FIG. 16 has a high resistivity thin film high resistance element 8. The thin film high resistance element 8 is formed as follows.
First, a thin film high resistance layer using a cermet resistance material is formed on the entire surface of the insulating film 2 of the semiconductor substrate 1. This is because the thin film high resistance element 8 is formed. After that, a conductive film is formed on the thin film high resistance layer (wiring layer film formation). Then, the conductive film is patterned to form the wiring layer 7 and the resistance element region A. As a result, the semiconductor device 20 having the thin film high resistance element 8 on the semiconductor substrate 1 shown in FIG. 16 is completed.

FIG. 17 is a sectional view showing a problem of the second semiconductor device 20. Reference numeral 8A in the broken line circle diagram shown in FIG. 17 denotes an uneven portion formed on the thin film high resistance layer in the resistance element region A. The uneven portion 8A is formed by being exposed to anisotropic etching such as RIE when the conductive film is patterned using the resist film 9 as a mask, and is also over-etched. FIG. 18 is a sectional view showing another problem of the second semiconductor device 20. The length L shown in FIG. 18 is the designed length of the resistance element, and the length L + ΔL is the length of the resistance element extended by wet etching.

[0018]

The semiconductor device and the method of manufacturing the same according to the prior art have the following problems. According to the first semiconductor device 10 and the manufacturing method thereof,
As the resistance of the thin film resistance layer shown in FIG. 15 becomes higher, the contact resistance in the contact holes 5 and 6 becomes higher depending on the resistance value (sheet resistance value) of the resistance layer itself. Intervenes in the connection resistance (parasitic resistance) between the wiring layer and the wiring layer, and exerts an influence as one of the unstable factors.

Therefore, the existence and instability of the contact resistance having a high resistance value has a great influence on the precision of the precision fine thin film high resistance element. This fluctuation of the resistance value causes deterioration of frequency characteristics in a high frequency circuit or the like.

According to the second semiconductor device 20 and the manufacturing method thereof, the cermet-based resistance material is a material very similar to the silicon-based oxide, and is directly used as an etching stopper during anisotropic etching by the RIE method. Therefore, there is a possibility that the resistance value may change due to over-etching of the resistance element region shown in FIG. 17 and its surface damage. Therefore, the film thickness is 10 to 150 nm
R on the insulating film on the thin film high resistance layer that needs to be formed to some extent
It makes extremely difficult to form a contact hole by the IE method.

Further, the semiconductor device 20 shown in FIG.
Then, when the wet etching method is adopted instead of the anisotropic etching by the RIE method, the processing accuracy thereof deteriorates. That is, the length L of the resistance element that defines the resistance value is
The conductive layer such as the Ti film, the Pt film, and the Au film is spread to L + ΔL by overetching.

Therefore, it is difficult to manufacture a semiconductor integrated circuit device incorporating a high resistance element having a stable resistance value. In addition, there are many difficult processes in the manufacturing process, which inevitably increases the number of processes and costs.
This is an obstacle to increasing the precision of the resistance element.

Therefore, the present invention solves the conventional problems as described above, and makes it possible to use a cermet-based resistance material and reduce the contact resistance between the resistance element and the wiring layer. An object of the present invention is to provide a semiconductor device capable of forming a semiconductor integrated circuit incorporating a precision fine thin film high resistance element having a stable resistance value, and a manufacturing method thereof.

[0024]

SUMMARY OF THE INVENTION The above-mentioned problems include a semiconductor substrate, an insulating film provided on the semiconductor substrate,
A thin film resistance layer provided on the entire surface or a part of the insulating film and a wiring layer selectively formed on the thin film resistance layer are provided, and the thin film resistance layer is used as a resistance element region. And a wiring connection region for connecting the resistance element and the wiring layer, and a region for forming the wiring layer on the thin film resistance layer other than the resistance element region is the wiring connection region. Solved by the device.

According to the semiconductor device of the present invention, the thin film resistance layer having the resistance element region used as the resistance element and the wiring connection region for connecting the resistance element and the wiring layer is provided, and the wiring connection region is provided. Includes all the formation area of the wiring layer on the thin film resistance layer other than the resistance element area.

Therefore, the contact resistance between the resistance element and the wiring layer can be suppressed to an extremely low level, so that when a high resistance element is formed, the influence of the contact resistance can be removed from the resistance value of the high resistance element. . This makes it possible to provide a highly reliable semiconductor device in which a precision fine thin film high resistance element having a stable resistance value is incorporated in a semiconductor integrated circuit.

A first method of manufacturing a semiconductor device according to the present invention comprises a step of forming a thin film resistance layer on the entire surface or a part of an insulating film on a semiconductor substrate, and selectively forming a predetermined region of the thin film resistance layer. A step of forming a mask member, a step of forming a conductive film on the thin film resistance layer on which the mask member is formed, and a step of selectively removing the conductive film to expose the mask member. The method is characterized by including a step of separating the conductive film and a step of removing the mask member exposed between the separated conductive films.

According to the first method of manufacturing a semiconductor device of the present invention, a semiconductor device having a thin film resistance layer in which a resistance element region and a wiring connection region are defined on a semiconductor substrate can be formed by a lift-off method. it can.

Moreover, since the wiring connection region includes the entire region for forming the wiring layer on the thin film resistance layer other than the resistance element region, even when the cermet-based resistance material is used, the resistance element and the wiring layer are not separated from each other. The contact resistance can be kept extremely low. The influence of contact resistance can be removed from the resistance value of the resistance element. Therefore, it is possible to manufacture a highly reliable semiconductor device in which a high resistance element having a stable resistance value is incorporated in a transistor circuit without adopting a complicated and difficult manufacturing process.

A second method of manufacturing a semiconductor device according to the present invention comprises a step of forming a thin film resistance layer on the whole surface or a part of the insulation film on a semiconductor substrate, and forming an insulation film on the thin film resistance layer. A step of selectively removing the insulating film to define a film for protecting the thin film resistance layer, and a step of forming a film for protecting the thin film resistance layer and a conductive film on the thin film resistance layer. A step of selectively removing the conductive film to isolate the conductive film so as to expose the film for protecting the thin film resistance layer.

According to the second method of manufacturing a semiconductor device of the present invention, a portion having a thin film resistance layer in which a resistance element region and a wiring connection region are defined on a semiconductor substrate and used as a resistance element It is possible to form a semiconductor device having a protective film on the thin film resistance layer.

Moreover, similar to the first manufacturing method, even when a cermet-based resistance material is used, the contact resistance between the resistance element and the wiring layer can be suppressed to a very low level, and a high resistance element or the like can be incorporated. A reliable semiconductor device can be manufactured.

A third method of manufacturing a semiconductor device according to the present invention comprises a step of forming a thin film resistance layer on the entire surface or a part of an insulating film on a semiconductor substrate, and an insulation property on a predetermined region of the thin film resistance layer. Step of sequentially laminating the film and the mask member, a step of forming a conductive film on the insulating film, the mask member and the thin film resistance layer, and the mask member by selectively removing the conductive film. And a step of separating the conductive film so as to expose the conductive film, and a step of removing the mask member exposed between the separated conductive films.

According to the third method of manufacturing a semiconductor device of the present invention, a portion having a thin film resistance layer in which a resistance element region and a wiring connection region are defined on a semiconductor substrate and used as a resistance element A semiconductor device having a protective film on the thin film resistance layer can be formed by a lift-off method.

Moreover, similar to the first and third manufacturing methods, even when a cermet-based resistance material is used, the contact resistance between the resistance element and the wiring layer can be suppressed to an extremely low level, and a high resistance element or the like can be obtained. It is possible to manufacture an incorporated high reliability semiconductor device or the like.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a semiconductor device and a method of manufacturing the same according to the present invention will be described with reference to the drawings. (1) First Embodiment FIG. 1A is a sectional view showing a configuration example of a semiconductor device 100 according to a first embodiment of the present invention, and FIG. 1B is a circuit diagram of its resistance element R1. In this embodiment, a thin film resistance layer having a resistance element region used as a resistance element and a wiring connection region for connecting the resistance element and a wiring layer is provided, and a wiring layer on the thin film resistance layer other than the resistance element region By using the formation region as a wiring connection region, the contact resistance between the resistance element and the wiring layer can be reduced, and a highly reliable semiconductor device in which a high resistance element having a stable resistance value is incorporated in a transistor circuit. Is provided.

The semiconductor device 100 shown in FIG. 1A has a semiconductor substrate 11. As the semiconductor substrate 11, a P-type or N-type Si substrate, a high-speed / high-dielectric constant GaAs compound-based semiconductor substrate, or the like is used. A silicon oxide film (hereinafter referred to as a SiO ₂ film 12) which is an example of an insulating film is provided on the semiconductor substrate 11. A thin film resistance layer 13 is provided on the entire surface or a part of the SiO ₂ film 12. The thin film resistance layer 13 is suitable for application to a high resistance element for microwaves.

The thin film resistance layer 13 is, for example, a resistance element R1.
It has a resistance element region A to be used as, and wiring connection regions B1 and B2 for connecting the resistance element R1 and the wiring layer 17. The thin-film resistance layer 13 serves as the resistance element R1 and part of the wiring layer 17.

In the semiconductor device 100, the resistance value R [Ω] of the resistance element R1 shown in FIG. 1B is set to ρ [μΩ / cm] as the specific resistance (resistivity) of the resistance material of the thin film resistance layer 13, and the resistance element R16. The length of the thin film resistance layer 13 used as
[Μm], its thickness is d [μm], and its width is w
When [μm] is satisfied, it is obtained by the equation (1), that is, R = ρ · l / (100d · w) ... (1). Sheet resistance ρs [Ω / □] is (2)
Formula, that is, ρs = ρ / 100d (2)

The thin film resistance layer 13 other than the resistance element region A
The formation regions of the upper wiring layer 17 are wiring connection regions B1 and B2. That is, the thin-film resistance layer 13 and the wiring layer 17 have a laminated structure, and the entire lower layer of the wiring layer 17 is the resistance element R1.
It is a connection area with.

The contact resistances r between the thin film resistance layer 13 and the wiring layer 17 in the wiring connection regions B1 and B2 are all distributed in parallel. Therefore, the contact resistance r between the wiring layer 17 and the thin film resistance layer 13 is extremely small as compared with the case where the wiring layer 17 and the thin film resistance layer 13 are connected via an opening for a connection hole, that is, a contact hole. can do.

That is, the contact resistance r between the resistance element R1 and the wiring layer 17 becomes more dependent on the resistance value (sheet resistance value) of the resistance layer itself as the resistance of the thin film resistance layer 13 becomes higher. The higher the resistance, the higher the contact resistance r, but the lower layer of the wiring layer 17 is entirely resistive element R.
The contact resistance r is extremely small because the contact resistance r is distributed in parallel.

The thin film resistance layer 13 has, for example, a film thickness of 30.
A high resistance material having a sheet resistance value of 0 nm or less and / or a sheet resistance value of 500 Ω / □ or more is used. The thin film resistance layer 13 has an insulating compound (SiO 2) composed of any element of silicon (Si), oxygen (O), nitrogen (N), and / or carbon (C).
₂ , SiN, SiC).

For this insulating compound, tantalum (T
a), niobium (Nb), titanium (Ti), molybdenum (Mo), tungsten (W), nickel (Ni), vanadium (V), hafnium (Hf), lanthanum (L)
A material containing at least one element selected from a) and zirconium (Zr) is used.

Alternatively, the thin film resistance layer 13 is made of Si, O,
SiO ₂ , SiN, or SiC, which is an insulating compound composed of N or / and C, is used as a base,
A compound containing at least one element selected from iridium (Ir), ruthenium (Ru), and platinum (Pt) is used for this insulating compound.

A wiring layer 17 is selectively formed on the thin film resistance layer 13. The wiring layer 17 includes a conductive layer formed by laminating a metallic film and / or a refractory metal. In this example, the Ti film 14 and the Pt film 15 are arranged from the lower layer to the upper layer.
And Au (gold) film 16 are laminated in this order to form a conductive layer. Hereinafter, the wiring layer 17 and the conductive layer will be treated equally.

The wiring layer 17 and the connection portion of the wiring layer 17 and the thin film resistance layer 13 are simultaneously processed in the same mask pattern in a self-aligned manner. The wiring process can be simplified by omitting the step of forming a connection hole between the wiring layer 17 and the thin film resistance layer 13.

Next, a method of manufacturing the semiconductor device 100 will be described. 2A to 2C are process diagrams showing a formation example (No. 1) of the semiconductor device 100 and FIGS. 3A to 3C are process diagrams showing the formation example (No. 2). In this example, it is assumed that the semiconductor device 100 having the resistance element R1 shown in FIG. 1 is manufactured by the lift-off method.

First, in FIG. 2A, a thin film resistance layer 13 is formed on the entire surface of an insulating film (hereinafter referred to as a SiO ₂ film) 12 on a semiconductor substrate 11. The thin film resistance layer 13 is SiO ₂
It may be formed in a partial region on the film 12. Thin film resistance layer 1
3 is formed by applying any one of the CVD method, the sputtering method and the vapor deposition method.

At this time, based on any one of the insulating compounds of SiO ₂ , SiN or SiC, Ta, Nb,
The thin film resistance layer 1 is made of a composite material (hereinafter referred to as a cermet resistance material) in which one or more elements are selected and combined from metals such as Ti, Mo, W, Ni, V, Hf, La and Zr.
3 is formed.

At this point, if it is necessary to form a connection hole (contact hole) with the semiconductor substrate 11, the thin film resistance layer 1
After forming a resist pattern for forming a contact hole on the substrate 3, the thin film resistance layer 13 and the lower insulating layer are continuously etched by the RIE method to form a contact hole with the semiconductor substrate 11. .

Thereafter, in order to define the resistance element region A, a first resist film 18 as an example of a mask member is selectively formed on a predetermined region of the thin film resistance layer 13 shown in FIG. 2B. For example, a resist is applied on the thin film resistance layer 13, and the resist is exposed using a reticle or the like as a mask. A pattern defining the resistance element region A is printed on this reticle. Then, the resist film 18 can be patterned by developing the resist (photoresist method).

The resist film 18 has the function of defining the shape of the thin film resistance layer portion used as the resistance element R1 and the function of protecting the thin film resistance layer 13 in that portion from damage due to etching during element separation in a later step. have.

After that, the first resist film 1 shown in FIG. 2C is formed.
8 and a conductive film is formed on the thin film resistance layer 13. As for the conductive film, a metallic conductive layer 17 'composed of at least one layer is formed. For example, the Ti film 14, the Pt film 15, and the Au (gold) film 16 are sequentially stacked from the lower layer to the upper layer to form the conductive layer 17 '.

Thereafter, in order to form a wiring pattern of the conductive layer 17 'and to define a joint portion between the conductive layer 17' and the thin film resistance layer 13, a selective pattern is formed on the conductive layer 17 'shown in FIG. 3A. The second resist film 19 is formed. Resist film 1
9 is also patterned by the photoresist method.

For example, a resist is applied on the conductive layer 17 ', and the resist is exposed using a reticle or the like as a mask. At this time, the reticle is printed with wirings that connect the elements and patterns that define the joints between these wirings and the thin film resistance layer 13. Then, the resist film 19 can be patterned by developing the resist.

After that, the conductive layer 17 'is selectively removed by using the resist film 19 as a mask, and the first resist film 18 is formed.
The conductive layer 17 'is separated into elements so as to expose. At this time, the conductive layer 17 'is removed by the RIE method or the like (anisotropic etching method). At this time, since the resistance element region A is covered with the resist film 18, the resist film 18 serves as a barrier and protects the thin film resistance layer 13 even when exposed to etching. The flat state of the surface of the thin film resistance layer 13 and a predetermined film thickness can be maintained. It is possible to eliminate fluctuations in resistance value.

By the same mask pattern formed by the second resist film 19, the element isolation of the conductive layer 17 'and the connection portion of the conductive layer 17' and the thin film resistance layer 13 can be simultaneously processed in a self-aligned manner. The conductive layer 17 'after the element isolation becomes the wiring layer 17.

Further, in order to continuously process the thin film resistance layer 13, the first resist film 18 exposed between the wiring layers 17 shown in FIG. 3B is removed. The resist film 18 is removed with a predetermined chemical solution. As a result, the semiconductor device 100 having the resistance element R1 shown in FIG. 1 can be manufactured.

As described above, according to the semiconductor device 100 of the first embodiment of the present invention, the resistance element region A used as the resistance element R1 and the wiring connecting the resistance element R1 and the wiring layer 17 are formed. The thin film resistance layer 13 having the connection regions B1 and B2 is provided, and the formation regions of the wiring layer 17 on the thin film resistance layer 13 other than the resistance element region A are the wiring connection regions B1 and B2.

Therefore, the contact resistance r between the resistance element R1 and the wiring layer 17 can be suppressed to an extremely low value. Therefore, when a high resistance circuit is constructed, the influence of the contact resistance r from the resistance value of the high resistance element R1. Can be excluded. Thereby, the formation of the contact hole connecting the high resistance element R1 and the wiring layer 17 can be omitted. Moreover, it is possible to provide the highly reliable semiconductor device 100 in which the high resistance element R1 or the like having a stable resistance value is incorporated in the transistor circuit.

Further, according to the method of manufacturing the semiconductor device 100 of the present invention, the thin film resistance layer 13 in which the resistance element region A and the wiring connection regions B1 and B2 are defined on the semiconductor substrate 11.
The semiconductor device 100 having the structure can be formed by a lift-off method.

Therefore, a semiconductor device in which a high resistance element R1 or the like using a cermet-based resistance material is incorporated in a transistor circuit without depending on a wet etching method and without employing a complicated and highly difficult manufacturing process. 100 can be manufactured with good reproducibility.

(2) Second Embodiment FIG. 4A is a sectional view showing a structural example of a semiconductor device 200 according to a second embodiment of the present invention, and FIG. 4B is a circuit diagram of its resistance element R2. In this embodiment, the resistance element region A
An insulative protective film is provided on the thin film resistance layer 13 in order to protect the surface of the thin film resistance layer in the resistance element region A from etching such as RIE in the wiring layer separation step and subsequent steps. Resistance element R2 of resistance element region A
The wiring layer 17 is designed so as not to come into direct contact therewith. Others are the same as those in the first embodiment, and those having the same name and the same reference numeral have the same function, and thus the description thereof will be omitted.

The semiconductor device 200 shown in FIG. 4A has a semiconductor substrate 11. SiO is formed on the semiconductor substrate 11.
_Two membranes 12 are provided. A thin film resistance layer 13 is provided on the entire surface or a part of the SiO ₂ film 12. The thin film resistance layer 13 is made of a cermet resistance material. The thin film resistance layer 13 has, for example, a resistance element region A used as a resistance element R2 and wiring connection regions B1 and B2 connecting the resistance element R2 and the wiring layer 17. The thin-film resistance layer 13 serves as the resistance element R2 and a part of the wiring layer 17.

Also in this semiconductor device 200, the formation regions of the wiring layer 17 on the thin film resistance layer 13 other than the resistance element region A shown in FIG. 4B are the wiring connection regions B1 and B2. Therefore, the contact resistance r between the wiring layer 17 and the thin film resistance layer 13 can be extremely reduced.

An insulating protective film 22 is provided on the thin film resistance layer 13 in the resistance element region A. As the protective film 22, a SiO ₂ film or a SiN film is used. This protective film 22
During the wiring layer separation process and subsequent processes, RIE
This is to protect the surface of the thin film resistance layer in the resistance element region A from etching such as.

A wiring layer 17 is selectively formed on the thin film resistance layer 13. The end portion of the wiring layer 17 is provided so as to rise so as to hold down the end portion of the protective film 22. This is because the wiring layer 17 is prevented from directly contacting the resistance element R2 in the resistance element region A. The wiring layer 17 includes a conductive layer formed by laminating a metallic film and / or a refractory metal. In this example, from the lower layer to the upper layer, the Ti film 14,
The Pt film 15 and the Au (gold) film 16 are laminated in this order to form a conductive layer.

The wiring layer 17 and the connection portion of the wiring layer 17 and the thin film resistance layer 13 are simultaneously processed in the same mask pattern by the same mask pattern as in the first embodiment. Wiring layer 17 and thin film resistance layer 13
It is possible to simplify the wiring process, such as omitting the connection hole forming process.

Next, a method of manufacturing the semiconductor device 200 will be described. 5A to 5C are process diagrams showing a formation example (No. 1) of the semiconductor device 200, and FIGS. 6A to 6C are process diagrams showing the formation example (No. 2). In this example, it is assumed that the semiconductor device 200 having the resistance element R2 shown in FIG. 4A is manufactured by the reactive ion etching (RIE) method.

First, in FIG. 5A, the thin film resistance layer 13 is formed on the entire surface of the SiO ₂ film 12 on the semiconductor substrate 11.
The thin film resistance layer 13 may be formed in a partial region on the SiO ₂ film. The thin film resistance layer 13 is formed by applying any one of the CVD method, the sputtering method and the vapor deposition method. At this time, based on SiO ₂ , SiN or SiC as an insulating compound,
Ta, Nb, Ti, Mo, W, Ni, V, Hf, La,
The thin film resistance layer 13 is formed of a cermet-based resistance material obtained by selecting one or more elements from Zr and combining them.

Then, in FIG. 5B, the thin film resistance layer 13
SiO as an example of an insulating film ₂Forming a membrane 22 '
It SiO₂The film 22 'is formed by the CVD method or the like,
After separation of the child, it becomes the protective film 22. So the smell in Figure 5C
And SiO₂The film 22 'is selectively removed to protect the thin film resistance layer.
Define a protective film. At this time, the resistive element region A is defined
In order to do₂The first resist film 2 is formed on the film 22 '.
8 is selectively formed.

For example, a resist is applied on the thin film resistance layer 13, and the resist is exposed using a reticle or the like as a mask. A pattern defining the resistance element region A is printed on this reticle. After that, the resist film 28 can be patterned by developing the resist (photoresist method). This resist film 28
Has a function of defining the shape of the thin film resistance layer portion used as the resistance element R2.

Then, in FIG. 6A, the SiO ₂ film 22 'is etched using the resist film 28 as a mask. S
The iO ₂ film 22 'is anisotropically etched by the RIE method. As a result, the resistive element region A can be defined and the protective film 22 can be formed in the region A.

Then, after removing the resist film 28 used as the mask, a conductive layer 17 'is formed on the protective film 22 and the thin film resistance layer 13 in FIG. 6B. Regarding the conductive film, similar to the first embodiment, the Ti film 14, the Pt film 15, and the Au (gold) film 1 are formed from the lower layer toward the upper layer.
6 is sequentially stacked to form a conductive layer 17 '.

Then, in FIG. 6C, the conductive layer 17 ′ is selectively removed to isolate the conductive layer 17 ′ so as to expose the protective film 22. At this time, the wiring pattern of the conductive layer 17 ′ and the conductive layer 17 ′ and the thin film resistance layer 13 are formed.
A second resist film 29 is selectively formed on the conductive layer 17 ′ in order to define the junction portion of the second resist film 29. Resist film 2
9 is also patterned by the photoresist method.

For example, a resist is applied on the conductive layer 17 ', and the resist is exposed by using a reticle or the like as a mask. At this time, the reticle is printed with wirings that connect the elements and patterns that define the joints between these wirings and the thin film resistance layer 13. After that, the resist film 29 can be patterned by developing the resist.

Then, the conductive layer 17 ′ is selectively removed by using the resist film 29 as a mask, and the conductive layer 17 ′ is isolated so that the auxiliary G film 22 is exposed. At this time, the conductive layer 17 'is removed by the RIE method or the like (anisotropic etching method). Since the resistance element region A is covered with the protective film 22, even if exposed to etching, the protective film 2
2 serves as a barrier to protect the thin film resistance layer 13. The flat state of the surface of the thin film resistance layer 13 and a predetermined film thickness can be maintained. It is possible to eliminate fluctuations in resistance value.

With the same mask pattern formed by the second resist film 29, the element isolation of the conductive layer 17 'and the connecting portion of the conductive layer 17' and the thin film resistance layer 13 can be simultaneously processed in a self-aligned manner. The conductive layer 17 'after the element isolation becomes the wiring layer 17. As a result, the thin film resistance layer 13 having the resistance element region A and the wiring connection regions B1 and B2 defined on the semiconductor substrate 11 shown in FIG. 4A is provided, and the thin film resistance layer of the portion used as the resistance element R2 is formed. Thirteen
The semiconductor device 200 having the protective film 22 thereon can be formed.

As described above, according to the semiconductor device 200 as the second embodiment of the present invention, the insulating protective film 22 is provided on the thin film resistance layer 13 in the resistance element region A, and the wiring layer separation step is performed. The surface of the thin film resistance layer in the resistance element region A can be protected from etching such as RIE at the time or in subsequent steps.

At the same time, the resistance element R in the resistance element region A is
The wiring layer 17 can be raised so as not to directly contact the wiring layer 2. Moreover, similarly to the first embodiment, the formation regions of the wiring layer 17 on the thin film resistance layer 13 other than the resistance element region A are the wiring connection regions B1 and B2.

Therefore, since the contact resistance r between the resistance element R2 and the wiring layer 17 can be suppressed to an extremely low level, the influence of the contact resistance r can be eliminated from the resistance element R2. As a result, it is possible to provide the highly reliable semiconductor device 200 in which the high resistance element R2 and the like having a stable resistance value are incorporated in the transistor circuit.

Further, according to the method of manufacturing the semiconductor device 200 of the present invention, as in the first embodiment, the high resistance element R2 and the like using the cermet-based resistance material is used without depending on the wet etching method. It is possible to manufacture a highly reliable semiconductor device 200 incorporating the above.

(3) Third Embodiment FIG. 7A is a sectional view showing a structural example of a semiconductor device 300 according to a third embodiment of the present invention, and FIG. 7B is a circuit diagram of its resistance element R3. In this embodiment, the resistance element region A
An insulating protective film is provided on the thin-film resistance layer 13 of FIG. 1 to enable the lift-off method to protect the surface of the thin-film resistance layer in the resistance element region A from a chemical solution or the like at the time of resist removal and an etching treatment in a later step. The wiring layer 17 does not directly contact the resistance element R3 in the resistance element region A. Others are the same as those in the first embodiment, and those having the same name and the same reference numeral have the same function, and thus the description thereof will be omitted.

The semiconductor device 300 shown in FIG. 7A has a semiconductor substrate 11. SiO is formed on the semiconductor substrate 11.
_Two membranes 12 are provided. A thin film resistance layer 13 is provided on the entire surface or a part of the SiO ₂ film 12. The thin film resistance layer 13 is made of a cermet resistance material. The thin film resistance layer 13 has, for example, a resistance element region A used as a resistance element R3 and wiring connection regions B1 and B2 connecting the resistance element R3 and the wiring layer 17. The thin-film resistance layer 13 serves as the resistance element R3 and a part of the wiring layer 17.

Also in this semiconductor device 300, the formation regions of the wiring layer 17 on the thin film resistance layer 13 other than the resistance element region A shown in FIG. 7B are the wiring connection regions B1 and B2. Therefore, the contact resistance r between the wiring layer 17 and the thin film resistance layer 13 can be extremely reduced.

An insulating protective film 32 is provided on the thin film resistance layer 13 in the resistance element region A. This protective film 3
A SiN film is used for 2. The protective film 32 is for protecting the surface of the thin film resistance layer in the resistance element region A from etching such as RIE in the wiring layer separation step and the subsequent steps.

A wiring layer 17 is selectively formed on the thin film resistance layer 13. The end of the wiring layer 17 is provided so as to hold down the end of the protective film 32. This is the resistance element area A
This is because the wiring layer 17 is prevented from directly contacting the resistance element R3. The wiring layer 17 includes a conductive layer formed by laminating a metallic film and / or a refractory metal. In this example, a Ti film 14, a Pt film 15, and an Au (gold) film 16 are stacked in this order from the lower layer to the upper layer to form a conductive layer.

Further, the wiring layer 17 and the connection portion of the wiring layer 17 and the thin film resistance layer 13 are simultaneously processed in the same mask pattern by the same mask pattern as in the first embodiment. Wiring layer 17 and thin film resistance layer 13
It is possible to simplify the wiring process, such as omitting the connection hole forming process.

Next, a method of manufacturing the semiconductor device 300 will be described. 8A to 8C are process diagrams showing a formation example (No. 1) of the semiconductor device 300, and FIGS. 9A to 9C are process diagrams showing the formation example (No. 2). In this example, it is assumed that the semiconductor device 300 having the resistance element R3 shown in FIG. 7A is manufactured by the lift-off method.

First, in FIG. 8A, the thin film resistance layer 13 is formed on the entire surface of the SiO ₂ film 12 on the semiconductor substrate 11.
The thin film resistance layer 13 is formed by applying any one of the CVD method, the sputtering method and the vapor deposition method. At this time, the insulating compound S
Based on either iO ₂ , SiN or SiC,
Ta, Nb, Ti, Mo, W, Ni, V, Hf, La,
The thin film resistance layer 13 is formed of a cermet-based resistance material obtained by selecting one or more elements from Zr and combining them.

In order to sequentially form an insulating film and a mask member on a predetermined region of the thin film resistance layer 13, first, as an example of an insulating film, an S film is formed on the entire surface of the thin film resistance layer 13.
An iN film 32 'is formed. Then, in order to define the resistance element region A, a first resist film 38 as an example of a mask member is selectively formed on a predetermined region of the SiN film 32 'shown in FIG. 8B.

For example, a resist is applied on the SiN film 32 ', and the resist is exposed using a reticle or the like as a mask. A pattern defining the resistance element region A is printed on this reticle. After that, the resist film 38 can be patterned by developing the resist (photoresist method).

The resist film 38 defines the shape of the thin film resistance layer portion used as the resistance element R3, and protects the thin film resistance layer 13 from that portion due to the damage caused by the chemical during the resist removal at the time of element separation in the subsequent process. It has a function to protect. After that, the resist film 38 shown in FIG.
Is used as a mask to remove the SiN film 32 'outside the resistive element region A. The SiN film 32 'is removed by the RIE method.
Si remaining in the resistance element region A due to this etching
The N film 32 ′ becomes the protective film 32.

After that, the first resist film 3 shown in FIG. 9A is formed.
8 and a conductive film is formed on the thin film resistance layer 13. As for the conductive film, a metal conductive layer composed of at least one layer is formed. For example, T from the lower layer to the upper layer
The i film 14, the Pt film 15, and the Au (gold) film 16 are sequentially stacked to form a conductive layer 17 '.

Thereafter, in order to pattern the wiring of the conductive layer 17 'and to define the joint portion of the conductive layer 17' and the thin film resistance layer 13, the conductive layer 17 'shown in FIG. 9B is selectively patterned on the conductive layer 17'. The second resist film 39 is formed. Resist film 3
9 is also patterned by the photoresist method.

For example, a resist is applied on the conductive layer 17 ', and the resist is exposed using a reticle or the like as a mask. At this time, the reticle is printed with wirings that connect the elements and patterns that define the joints between these wirings and the thin film resistance layer 13. After that, the resist film 39 can be patterned by developing the resist.

After that, the conductive layer 17 'is selectively removed by using the resist film 39 as a mask, and the first resist film 38 is formed.
The conductive layer 17 'is separated into elements so as to expose. At this time, the conductive layer 17 'is removed by the RIE method or the like (anisotropic etching method). At this time, since the resistance element region A is covered with the resist film 38 and the protective film 32,
Even when exposed to etching, the upper resist film 38 serves as a barrier to protect the thin film resistance layer 13.

By the same mask pattern by the second resist film 39, the element isolation of the conductive layer 17 'and the connection portion of the conductive layer 17' and the thin film resistance layer 13 can be simultaneously processed in a self-aligned manner. The conductive layer 17 'after the element isolation becomes the wiring layer 17.

Further, in order to continuously process the thin film resistance layer 13, the first resist film 38 exposed between the wiring layers 17 shown in FIG. 9C is removed. The resist film 38 is removed with a predetermined chemical solution. At this time, since the resistance element region A is covered with the protective film 32, even if the resistive element region A is exposed to the resist removing chemical, the protective film 32 serves as a barrier to protect the thin film resistive layer 13. The flat state of the surface of the thin film resistance layer 13 and a predetermined film thickness can be maintained. It is possible to eliminate fluctuations in resistance value. As a result, the semiconductor device 300 having the protective film 32 on the resistance element R3 shown in FIG. 7A can be manufactured.

As described above, according to the semiconductor device 300 of the third embodiment of the present invention, the insulating protective film 32 is provided on the thin film resistance layer 13 in the resistance element region A, and the wiring layer separation step is performed. At the time or in subsequent steps, the surface of the thin film resistance layer in the resistance element region A can be protected from a chemical solution used in etching such as RIE and resist removal.

At the same time, the resistance element R in the resistance element region A is
The wiring layer 17 can be set up so as not to come into direct contact with the wiring layer 3. Moreover, similarly to the first embodiment, the formation regions of the wiring layer 17 on the thin film resistance layer 13 other than the resistance element region A are the wiring connection regions B1 and B2.

Therefore, since the contact resistance r between the resistance element R3 and the wiring layer 17 can be suppressed to an extremely low level, the influence of the contact resistance r can be eliminated from the resistance element R3. As a result, it is possible to provide a highly reliable semiconductor device 300 in which the high resistance element R3 or the like having a stable resistance value is incorporated in a transistor circuit.

Further, according to the method of manufacturing the semiconductor device 300 of the present invention, as in the first embodiment, the high resistance element R3 or the like using the cermet type resistance material is used without depending on the wet etching method. It is possible to manufacture a highly reliable semiconductor device 300 incorporating the above.

(4) Embodiments FIGS. 10 to 14 are process diagrams showing formation examples (Nos. 1 to 5) of a semiconductor device 400 as an embodiment according to the present invention.
In this example, a GaAs semiconductor substrate 21 is used as a semiconductor wafer.
Is prepared and the n-type field effect transistor and the thin film resistance layer 13 described in the first embodiment are formed on the substrate 21.

First, the GaAs semiconductor substrate 21 having the n-type field effect transistor shown in FIG. 10A is prepared. The GaAs semiconductor substrate 21 is made of S as the insulating film 12.
The elements are separated by the iO ₂ films 12A and 12B.
A gate electrode (gate metal) 23 is formed on the substrate 21, and a p-type buried layer (p-well) 2 is formed.
4 are formed. An ohmic metal (high melting point metal silicide film) 23A is formed on the substrate 21 below the gate electrode 23.

A pair of N ⁺ impurity diffusion layers 25A, 25 are formed in the buried layer 23 on both sides of the gate electrode 23.
B is formed. For example, the N ⁺ impurity diffusion layer 25A constitutes a source, and the N ⁺ impurity diffusion layer 25B constitutes a drain. Further, an ohmic metal (high melting point metal silicide film) 26A is formed in the contact portion of the source extraction electrode region, and an ohmic metal (high melting point metal silicide film) 26B is formed in the contact portion of the drain extraction electrode region. Has been done.
After that, an insulating layer made of a plasma silicon nitride film (SiN film) 27 is formed on the GaAs semiconductor substrate 21 to form the GaAs semiconductor substrate 21 having the n-type field effect transistor shown in FIG. 10A. .

Then, in FIG. 10B, the SiN film 27 is formed.
A resist film 28 for air bridge to the uneven portion on the GaAs semiconductor substrate 21 covered with is patterned.
This is because the resist film 28 eliminates the uneven portion on the gate electrode 23 during the formation of the thin film resistance layer and temporarily flattens the portion.

Then, the thin film resistance layer 13 is formed on the GaAs semiconductor substrate 21 having the SiN film 27 and the resist film 28 shown in FIG. 11A. A cermet-based resistance material is used for the thin film resistance layer 13, and for example, a thin film metal resistance TaS is used.
A film of iO ₂ is formed. The film formation at this time is performed by a multi-source sputtering method of Ta atoms and an insulating compound such as SiO ₂ using a sputtering device. For example, the thin film resistance layer 13 outputs DC from a Ta target by high frequency magnetron sputtering.
250 W, an SiO ₂ target RF output by RF sputtering = 850W, Ar flow rate = 45 sccm, pressure =
It can be obtained by forming a film at a temperature of 0.55 Pa and a temperature of the semiconductor substrate 21 (wafer stage temperature) of 40 ° C. The thin film resistance layer 13 obtained under such film forming conditions has a sheet resistance of 4.5 kΩ / □ and an evaluation value of in-plane uniformity of σ / A.
The verage is 2.5% and the film thickness is about 105 nm.

After forming the thin film resistance layer 13, a resist film 29 for forming a contact hole is formed in FIG. 11B. For example, a resist is applied on the thin film resistance layer 13, and the resist is exposed using a reticle or the like as a mask. A pattern defining a contact hole is printed on the reticle. Then, the resist film can be patterned by developing the resist (photoresist method).

After that, a contact hole is formed by RIE using the resist film 29 shown in FIG. 12A as a mask. At this time, the thin film resistance layer 13 on the source region and SiN
An opening 31A exposing the ohmic metal 26A is formed by selectively removing the film 27. At the same time, the thin film resistance layer 13 and the SiN film 27 on the drain region are selectively removed to form an opening 31B exposing the ohmic metal 26B. The opening 31A serves as a contact hole for drawing out the source, and the opening 31B serves as a contact hole for drawing out the drain.

Thereafter, in FIG. 12B, the resist film 29 for forming the contact hole is entirely removed, and the resist film (first resist film) 18 for defining the resistance element region, which is an example of the mask member, is selectively formed. To do. This resist film 18 is for defining the region A where the thin film resistance layer 13 is used as a resistance element. For example, thin film resistance layer 1
3 is coated with a resist, and the resist is exposed using a reticle or the like as a mask. A pattern that defines a resistance element region is printed on the reticle. Then, the resist film 18 can be patterned by developing the resist.

The film thickness of the resist film 18 at this time is 300 n.
m, and preferably the shoulder portion of the resist film 18 is formed gently. This gentle shape is obtained by baking the semiconductor substrate 21 at 130 ° C. The thickness of the resist film 18 and the shoulders are formed gently
This is because the lift-off method is adopted, and for example, in the subsequent step, it is easy to remove the resist film existing in the lateral direction under the wiring layer.

Thereafter, a Ti film 14, a Pt film 15, and an Au film 16 are sequentially laminated and formed as a first wiring layer (1st metal layer) on the thin film resistance layer 13 including the resist film 18 shown in FIG. 13A. . Ti film 14, Pt film 15 and Au
The film 16 constitutes a conductive film 17 '. Ti film 14 is 50n
m, the Pt film 15 is 30 nm, and the Au film 1
6 is 600 nm, and all are formed by a sputtering method.

Then, the first conductive layer 1 shown in FIG. 13B is formed.
A resist film (second resist film) 19 is formed on 7 '. This resist film 19 is for carrying out the wiring patterning of the conductive layer 17 'and defining the joint portion of the conductive layer 17' and the thin film resistance layer 13. For example, a resist is applied on the conductive layer 17 ', and the resist is exposed using a reticle or the like as a mask. A wiring pattern and a device isolation pattern are printed on this reticle. Then, the resist film 19 can be patterned by developing the resist.

Then, the conductive layer 17 'is selectively removed by using the resist film 19 shown in FIG. 14A as a mask, and the conductive layer 17' is separated into elements so that the resist film 18 is exposed. At this time, the conductive layer 17 'is ion-milled and cut by the RIE method or the like (anisotropic etching method).
At this time, since the resistance element region A is covered with the resist film 18, the resist film 18 serves as a barrier and protects the thin film resistance layer 13 even when exposed to etching. The flat state of the surface of the thin film resistance layer 13 and a predetermined film thickness can be maintained. It is possible to eliminate fluctuations in resistance value.

With the same mask pattern formed by the resist film 19, the element isolation of the conductive layer 17 'and the connection portion of the conductive layer 17' and the thin film resistance layer 13 can be simultaneously processed in a self-aligned manner. Conductive layer 1 after element isolation
7'becomes the wiring layer 17.

Then, in order to continuously process the thin film resistance layer 13 shown in FIG. 14B, the resist film 18 exposed between the wiring layers 17 is removed. The resist film 18 is removed with a predetermined chemical solution. Then, the semiconductor substrate 21 is annealed. The processing conditions at this time are heating temperature of 400 ° C., H
₂ Atmosphere for about 10 minutes. By this annealing treatment, the Ti film 1 as the thin film resistance layer 13 and the wiring layer 17 is formed.
4, the stress of the Pt film 15 and the Au film 16 is relieved,
The thermal stability of the thin film resistance layer 13 is ensured. As a result, the semiconductor device 400 including the n-type field effect transistor Tr and the resistance element R1 on the GaAs semiconductor substrate 21 is completed.

As described above, according to the method of manufacturing the semiconductor device 400 as the example of the present invention, the method of manufacturing the semiconductor device according to the first embodiment is applied, and therefore n
The semiconductor device 400 having the field effect transistor Tr of the type and the resistance element R1 can be formed by the lift-off method.

Therefore, a semiconductor device in which the high resistance element R1 or the like using a cermet-based resistance material is incorporated in a transistor circuit without depending on the wet etching method and without employing a complicated and highly difficult manufacturing process. 400 can be manufactured with good reproducibility.

In this example, the case of applying the first embodiment has been described, but the present invention is not limited to this.
The thin-film resistance layer manufacturing method according to the second and third embodiments is applied to apply an n-type field effect transistor and a thin-film resistance layer 13.
It is also possible to form the semiconductor device 400 having the above.

The present invention is not limited to the first embodiment, but a semiconductor integrated circuit device having a logic circuit function which requires mounting of a high resistance element R (R> 0.5 kΩ / □), or , A semiconductor integrated circuit device having an analog circuit function composed of a bipolar transistor (BipTr) element or the like which requires high accuracy, or an analog / digital circuit function composed of a BipTr element and a field effect transistor (MOSTr) element. BiCOM with
The present invention can be applied to an S semiconductor integrated circuit device or an MMIC (Microwave Monolithic IC) type GaAs semiconductor device having a high frequency integrated circuit function.

Besides, according to the method of manufacturing a semiconductor device of the present invention, the following effects can be obtained. A cermet-based resistance material can be adopted for the thin-film resistance layer 13, and the parameter for controlling the resistance value must be optimized for device performance as compared with the conventional diffusion resistance element, field effect resistance element, and the like. There is no limitation on the resistance value that also serves as a parameter that must be used, and the desired resistivity can be obtained by independently changing the composition ratio of the cermet-based resistance material.

Further, by adopting a cermet resistance material for the thin film resistance layer 13, the thin film resistance material formed by the conventional reactive sputtering method, TaN, Ti.
It is possible to form a high-resistance element with good reproducibility and stability as compared with the case where a resistance material is formed by utilizing a chemical reaction such as N, TaON, TiON, WN, etc. during the film formation such as a nitriding atmosphere or an oxidizing atmosphere. it can.

Similarly, a high resistivity (20 × 10 ³ μΩcm), which cannot be obtained by a thin film metal resistance material such as Ta, W, or Ti, or a NiCr type thin film alloy resistance material, can be obtained by a cermet type resistance material. Became. As a result, the cermet resistance material can be easily used in the semiconductor integrated circuit.

When the cermet-based resistance material is used, there is no need for a special step, a manufacturing method or an additional step for suppressing the oxidation of the thin film resistance element, as compared with a thin film resistance element such as CrSi ₂ or CrSiN. It is possible to form a thin film resistance element having more excellent heat resistance / oxidation resistance without increasing the manufacturing cost and without involving a complicated element structure or complicated manufacturing steps.

By using a cermet-based resistance material in a semiconductor integrated circuit, silicon unbonded, which causes a change in resistance value and influences the operation of conduction carriers, as compared with a diffusion resistance element, a polysilicon resistance element, or the like. Presence of hands (hydrogen adsorption), crystal defect density, surface energy rank,
It is possible to avoid all the factors that suddenly and significantly change the resistance value, such as the properties of crystal grains and the state of crystal grain boundaries.

This is because the metal material in the cermet-based resistance material is rich in heat resistance and oxidation resistance and is chemically stable, and in the thin film resistance element, thermal shock, oxidation, chemical, This is because it has a very high effect of suppressing the electrochemical reaction.

With the cermet-based resistance material, a good high resistance element having a sheet resistance of 10 kΩ / □, which could not be obtained with a polysilicon resistance or a diffusion resistance, is formed extremely stably with good reproducibility and reliability. I was able to.

Further, according to the thin film resistance layer 13 using the cermet-based resistance material, a high resistance element exhibiting excellent temperature characteristics (resistance temperature coefficient <± 200 ppm / ° C.), extremely small change over time, and high reliability. Can be provided,
It has become possible to manufacture a semiconductor device that simultaneously utilizes the above-mentioned oxidation resistance and heat resistance. In particular, it is possible to provide a semiconductor device that can sufficiently withstand a heat treatment process such as formation of an active element (transistor or the like) in a semiconductor manufacturing process and has no added value in the manufacturing process.

[0131]

As described above, according to the semiconductor device of the present invention, the thin film resistance layer having the resistance element region used as the resistance element and the wiring connection region connecting the resistance element and the wiring layer. Is provided, and an area where the wiring layer is formed on the thin film resistance layer other than the resistance element area is a wiring connection area.

With this structure, the contact resistance between the resistance element and the wiring layer can be suppressed to an extremely low level. Therefore, when a high resistance element is formed, the influence of the contact resistance should be excluded from the resistance value of the high resistance element. You can It is possible to provide a highly reliable semiconductor device in which a high resistance element or the like having a stable resistance value is incorporated in a transistor circuit.

According to the first manufacturing method of the semiconductor device of the present invention, the mask member is selectively formed on a predetermined region of the thin film resistance layer formed on the whole surface or a part of the insulating film on the semiconductor substrate. And further forming a conductive film on the thin-film resistance layer on which the mask member is formed, and then selectively removing the conductive film to expose the mask member. The film is separated, and the mask member exposed between the separated conductive films is removed.

With this structure, a semiconductor device having a thin film resistance layer in which a resistance element region and a wiring connection region are defined on a semiconductor substrate can be formed by a lift-off method. Moreover, since the wiring connection region includes the entire region for forming the wiring layer on the thin film resistance layer other than the resistance element region, the contact resistance between the resistance element and the wiring layer can be suppressed to an extremely low level. The influence of contact resistance can be removed from the resistance value of the resistance element.

As a result, it is possible to manufacture a highly reliable semiconductor device in which a high resistance element or the like having a stable resistance value is incorporated in a transistor circuit without adopting a complicated and highly difficult manufacturing process.

According to the second method of manufacturing a semiconductor device of the present invention, an insulating film is formed on the thin film resistance layer formed on the entire surface or a part of the insulating film on the semiconductor substrate, and then the insulating film is formed. , The insulating film is selectively removed to define a film for protecting the thin film resistance layer, and a conductive film is formed on the film and the thin film resistance layer, and then the conductive film is selected. Elements are removed so that the film for protecting the thin film resistance layer is exposed to separate the elements.

With this structure, the semiconductor device has the thin film resistance layer in which the resistance element region and the wiring connection region are defined on the semiconductor substrate, and has the protective film on the thin film resistance layer of the portion used as the resistance element. Can be formed.
Moreover, similar to the first manufacturing method, the contact resistance between the resistance element and the wiring layer can be suppressed to an extremely low level, and a highly reliable semiconductor device incorporating a high resistance element or the like can be manufactured.

According to the third manufacturing method of the semiconductor device of the present invention, the insulating film and the insulating film are formed on the predetermined region of the thin film resistance layer formed on the entire surface or a part of the insulating film on the semiconductor substrate. A mask member is sequentially laminated and formed, and then a conductive film is formed on the insulating film, the mask member and the thin film resistance layer, and then the conductive film is selectively removed to expose the mask member. Then, the conductive film is separated, and the mask member exposed between the separated conductive films is removed.

With this structure, the semiconductor device has the thin film resistance layer in which the resistance element region and the wiring connection region are defined on the semiconductor substrate, and has the protective film on the thin film resistance layer of the portion used as the resistance element. Can be formed by a lift-off method. Moreover, similar to the first and second manufacturing methods, the contact resistance between the resistance element and the wiring layer can be suppressed extremely low, and a highly reliable semiconductor device incorporating a high resistance element or the like can be manufactured. it can.

The present invention is extremely suitable when applied to a semiconductor device in which a high resistance element is incorporated in an integrated circuit and a manufacturing method thereof.

[Brief description of drawings]

FIG. 1A is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a first embodiment of the present invention, and B is a circuit diagram thereof.

2A to 2C are examples of forming the semiconductor device 100 (No. 1).
FIG.

3A and 3B are process diagrams showing a formation example (No. 2) of the semiconductor device 100.

FIG. 4A is a sectional view showing a configuration example of a semiconductor device 200 according to a second embodiment of the present invention, and B is a circuit diagram thereof.

5A to 5C are examples of forming the semiconductor device 200 (No. 1).
FIG.

6A to 6C are examples of forming the semiconductor device 200 (Part 2).
FIG.

FIG. 7A is a sectional view showing a configuration example of a semiconductor device 300 as a third embodiment according to the present invention, and B is a circuit diagram thereof.

8A to 8C are examples of forming the semiconductor device 300 (No. 1).
FIG.

9A to 9C are examples of forming the semiconductor device 300 (Part 2).
FIG.

10A and 10B are process diagrams showing a formation example (1) of a semiconductor device 400 as an embodiment according to the present invention.

11A and 11B are process diagrams showing a formation example (No. 2) of the semiconductor device 400.

12A and 12B are process diagrams showing a formation example (No. 3) of the semiconductor device 400.

13A and 13B are process diagrams showing a formation example (No. 4) of the semiconductor device 400.

14A and 14B are process diagrams showing a formation example (No. 5) of the semiconductor device 400.

FIG. 15 is a cross-sectional view showing a configuration example of a first semiconductor device 10 according to a conventional example.

FIG. 16 is a cross-sectional view showing a configuration example of a second semiconductor device 20 according to a conventional example.

FIG. 17 is a cross-sectional view showing a problem of the second semiconductor device 20.

FIG. 18 is a cross-sectional view showing another problem of the second semiconductor device 20.

[Explanation of symbols]

11 ... Semiconductor substrate, 12 ... SiO ₂ film (insulating film), 13 ... Thin film resistance layer, 17 ... Wiring layer, 1
7 '... Conductive layer, 18 ... First resist film, 19
... Second resist film, 21 ... GaAs semiconductor substrate, 22 ... Protective film, 32 ... SiN film (protective film), Tr ... Field effect transistors, R1 to R3.
..Resistance elements

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Claims (33)

[Claims] 1. A semiconductor substrate, an insulating film provided on the semiconductor substrate, a thin film resistance layer provided on the entire surface or a part of the insulating film, and selected on the thin film resistance layer. And a wiring connection region connecting the resistance element and the wiring layer, the thin film resistance layer has a resistance element region used as a resistance element and a wiring connection region connecting the resistance element and the wiring layer. A semiconductor device, wherein a wiring layer forming region on the thin film resistance layer other than the above is the wiring connecting region. 2. The semiconductor device according to claim 1, wherein the thin film resistance layer also serves as the resistance element and a part of the wiring layer. 3. The wiring layer and the connection portion of the wiring layer and the thin film resistance layer are simultaneously processed in the same mask pattern in a self-aligned manner.
The semiconductor device according to. 4. The thin-film resistance layer is based on an insulating compound made of any one of silicon, oxygen, nitrogen, and / or carbon, and the insulating compound is selected from iridium, ruthenium, and platinum. The semiconductor device according to claim 1, wherein the semiconductor device is configured to include at least one element selected from the above. 5. The thin-film resistance layer is based on an insulating compound made of any one of silicon, oxygen, nitrogen, and / or carbon, and tantalum, niobium, titanium,
The semiconductor device according to claim 1, comprising at least one element selected from the group consisting of molybdenum, tungsten, nickel, vanadium, hafnium, lanthanum and zirconium. 6. The semiconductor device according to claim 1, wherein the wiring layer includes a conductive layer in which a metallic film and a refractory metal are laminated. 7. The semiconductor device according to claim 1, wherein an insulating protective film is provided on the thin film resistance layer in the resistance element region. 8. The semiconductor device according to claim 1, wherein the protective film is processed into the same shape by a mask member for defining the shape of the resistance element. 9. The thin film resistance layer has a film thickness of 300 nm or less and / or a sheet resistance value of 500Ω.
The semiconductor device according to claim 1, wherein a high resistance layer having a squareness of / □ or more is used. 10. A step of forming a thin film resistance layer on the entire surface or a part of an insulating film on a semiconductor substrate, a step of selectively forming a mask member on a predetermined region of the thin film resistance layer, A step of forming a conductive film on the thin film resistance layer having a mask member formed thereon, and a step of selectively removing the conductive film to separate the conductive film so as to expose the mask member. And a step of removing the mask member exposed between the separated conductive films. 11. The method of manufacturing a semiconductor device according to claim 10, wherein the thin film resistance layer also serves as the resistance element and a part of the wiring layer. 12. The thin film resistance layer is based on an insulating compound made of any one of silicon, oxygen, nitrogen, and / or carbon, and tantalum, niobium, titanium,
11. The method of manufacturing a semiconductor device according to claim 10, wherein the method includes at least one element selected from molybdenum, tungsten, nickel, vanadium, hafnium, lanthanum, and zirconium. 13. The thin-film resistance layer is based on an insulating compound made of any one of silicon, oxygen, nitrogen, and / or carbon, and the insulating compound is selected from iridium, ruthenium, and platinum. 11. The method of manufacturing a semiconductor device according to claim 10, wherein the semiconductor device is configured to include at least one kind of element selected from the above. 14. The method of manufacturing a semiconductor device according to claim 10, wherein the wiring layer includes a conductive layer in which a metallic film and a refractory metal are laminated. 15. The insulating protective film is provided on the thin film resistance layer in the resistance element region.
A method of manufacturing a semiconductor device according to item 1. 16. The protective film is formed into the same shape by a mask member for defining the shape of the resistance element.
A method of manufacturing a semiconductor device according to item 1. 17. The thin film resistance layer has a film thickness of 300 nm or less and / or a sheet resistance value of 500Ω.
11. A method of manufacturing a semiconductor device according to claim 10, wherein a high resistance of /.quadrature. Or more is used. 18. A step of forming a thin film resistance layer on the entire surface or a part of an insulation film on a semiconductor substrate; a step of forming an insulation film on the thin film resistance layer; A step of selectively removing and defining a film for protecting the thin film resistance layer; a step of forming a conductive film on the film for protecting the thin film resistance layer and the thin film resistance layer; and selecting the conductive film And removing the conductive film by element isolation so that the film for protecting the thin film resistance layer is exposed. 19. The method of manufacturing a semiconductor device according to claim 18, wherein the thin film resistance layer also serves as the resistance element and a part of the wiring layer. 20. The thin-film resistance layer is based on an insulating compound made of any one of silicon, oxygen, nitrogen, and / or carbon, and tantalum, niobium, titanium,
19. The method of manufacturing a semiconductor device according to claim 18, wherein the method includes at least one element selected from molybdenum, tungsten, nickel, vanadium, hafnium, lanthanum, and zirconium. 21. The thin film resistance layer is based on an insulating compound made of any one of silicon, oxygen, nitrogen, and / or carbon, and the insulating compound may be one of iridium, ruthenium, and platinum. 19. The method of manufacturing a semiconductor device according to claim 18, wherein the semiconductor device is configured to include at least one kind of element selected from the above. 22. The method of manufacturing a semiconductor device according to claim 18, wherein the wiring layer includes a conductive layer in which a metallic film and a refractory metal are laminated. 23. An insulating protective film is provided on the thin film resistance layer in the resistance element region.
A method of manufacturing a semiconductor device according to item 1. 24. The protective film is formed in the same shape by a mask member for defining the shape of the resistance element.
A method of manufacturing a semiconductor device according to item 1. 25. The thin film resistance layer has a film thickness of 300 nm or less and / or a sheet resistance value of 500 Ω.
The method of manufacturing a semiconductor device according to claim 18, wherein a high resistance of / □ or more is used. 26. A step of forming a thin film resistance layer on an entire surface or a part of an insulation film on a semiconductor substrate, and an insulating film and a mask member are sequentially laminated on a predetermined region of the thin film resistance layer. A step of forming a conductive film on the insulating film, the mask member and the thin film resistance layer; and a step of selectively removing the conductive film to expose the mask member. And a step of removing the mask member exposed between the separated conductive films, the method of manufacturing a semiconductor device. 27. The method of manufacturing a semiconductor device according to claim 26, wherein the thin film resistance layer also serves as the resistance element and a part of the wiring layer. 28. The thin film resistance layer is based on an insulating compound made of any one of silicon, oxygen, nitrogen, and / or carbon, and tantalum, niobium, titanium,
27. The method of manufacturing a semiconductor device according to claim 26, comprising at least one element selected from molybdenum, tungsten, nickel, vanadium, hafnium, lanthanum, and zirconium. 29. The thin film resistance layer is based on an insulating compound made of any one of silicon, oxygen, nitrogen, and / or carbon, and the insulating compound may be one of iridium, ruthenium, and platinum. 27. The method of manufacturing a semiconductor device according to claim 26, comprising at least one kind of element selected from the above. 30. The method of manufacturing a semiconductor device according to claim 26, wherein the wiring layer includes a conductive layer in which a metallic film and a refractory metal are laminated. 31. An insulating protective film is provided on the thin film resistance layer in the resistance element region.
A method of manufacturing a semiconductor device according to item 1. 32. The protective film is formed in the same shape by a mask member for defining the shape of the resistance element.
A method of manufacturing a semiconductor device according to item 1. 33. The thin film resistance layer has a film thickness of 300 nm or less and / or a sheet resistance value of 500 Ω.
27. The method for manufacturing a semiconductor device according to claim 26, wherein a material having a high resistance of / □ or more is used.