JPH01296656A - Polysi resistor and semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the stability of a process and a reduction in an occupation area for forming a poly Si resistor by a method wherein the specific resistance of the poly Si resistor consisting of a poly Si layer formed on a semiconductor substrate and the like are specified. CONSTITUTION:A semiconductor device is constituted in a structure, wherein an Si3N4 film 3 is provided on an Si substrate 1 through an SiO2 film 2, a poly Si film 4 is provided thereon, then an Si3N4 film 5 is provided to wrap the film 4 in a sandwich form with the films 3 and 5. The specific resistance of this poly Si resistor is 0.1OMEGA.cm or lower, the sectional area of the resistor is 1X10<-10>cm<2> or wider, the length of the resistor is 5mum or longer, the width of the resistor is 0.8mum or narrower and moreover, the thickness of the resistor is 125Angstrom or thicker and the resistor is controlled at a resistance value of 40-800kOMEGA. Thereby, the stability of a process and a reduction in an area to monopolize for forming the resistor are contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and in particular to semiconductor devices suitable for realizing high resistance from approximately 40 to 800 Ω, used in bipolar memory circuits, etc. Regarding polysilicon resistors.

[Prior Art] ”Resistors used in semiconductor integrated circuit devices are generally formed in regions for separating elements, called isolation, for the purpose of reducing parasitic capacitance and achieving higher integration. Such resistors are typically made of polysilicon (PLA).
y S, i ) layer, but conventionally it has been used for low resistance of several Ω or less, or for ultra-high resistance of about several 100 Ω or more.

Regarding the former, see, for example, Solid State Electronics, Vol. 20 (1977), pp. 883-8.
Page 89 (Solid-3tate Electronic
cs.

voQ, 20 (1077), pp, 883-8
89). Regarding the latter, see, for example, IEDM, Technical Digest, 1986, pp. 300-303 (Tec
hical Digestof IEDM (1986
), pp 300-303).

By the way, recently, regarding resistance in the range from approximately 40Ω to 800Ω, patent applications No. 128137/1986 and No. 63-1 have been published.
0641 describes measures for improving temperature characteristics.

[Problem that the invention sought to solve]

However, the above-mentioned technology aiming at a resistance value of about 40Ω to 800Ω lacks consideration for process stability (a), area occupied for resistor formation (b), and reliability (c), and is not effective for LSI integration. It became clear that there were still problems in applying the method to circuits.

An object of the present invention is to provide the above-described n
The purpose is to solve three problems of pbpQ.

[Means to solve the problem]

The above object is achieved by forming polysilicon resistors under conditions regulated by each of the eight problems a to c.

Issue a: Process stability Figure 2 shows the relationship between the specific resistance ρ of polysilicon and the doping concentration. The 0 mark is an experimental value. Experimental value is 11,12
．． It can be separated into three regions indicated by tangent lines indicated by 13. Among these, the tangent line 12 is a region where ρ varies by five orders of magnitude when N varies by one order of magnitude, and process stability cannot be obtained. The resistance aimed at by the present technology is achieved in the region indicated by the tangent line 13.

From this, it is a condition for this problem that ρ is 0.1Ω·1 or less. Note that in this region, even if N changes by one order of magnitude, ρ is 1
It only changes by an order of magnitude.

Problem b: Let the width dimension of the occupied area polysilicon resistor be W, and its length dimension be Q.
And so. Now assume that Q/w is 10. At this time, it is assumed that the area occupied for forming the resistor is wXflX3 times. Furthermore, in a memory LSI circuit that uses a resistor, the allowable area occupied by the resistor is 17% of the memory cell area.
Assume 10.

FIG. 3 is a typical memory cell circuit diagram. A polysilicon resistor is used as a resistor denoted RMC. The current cell area of such memory cells is ~500 μm.

Therefore, the allowable exclusive area is 50 μm, but as is clear from Figure 3, normally there are 2
polysilicon resistors. From this, the final condition is that the area of one polysilicon resistor is 25 .mu.- or less.

Based on these conditions, W is limited to 0.8 μm or less.

Issue C: Reliability When a high current is passed through a polysilicon resistor, resistance fluctuations occur. This upper limit is 5 x 10"A/d, but if stability is expected, it is safe to set the upper limit to I x 10"A/cd. 4O used in memory LSI circuits
The current flowing through a polysilicon resistor such as KΩ to 800Ω is at most 50 μA when the resistance is 40Ω. 20μA at 100Ω.

At 200 KO, it is 10 μA. Therefore, 5X1
In order not to exceed the current density J of 0', the cross-sectional area S of the polysilicon resistor is 1X10-''a#, 1 when the current density is 40Ω.
4 X 10-11d at 00 KΩ.

When the resistance is 200Ω, it is determined to be 2×10−11cnf or more.

From problem C, the lower limit of the thickness t of the polysilicon resistor is w = 0.8 μm, and when it is 40Ω, S = I
125 people because it was 10-”cJ or more.

When 100 Ω, S = 4
Since it is 1O-11d or more, it is determined to be 25 Å or more.

Furthermore, since ρ in task a is less than 0.1Ω・1,
The sheet resistance ρS of the polysilicon resistor is automatically determined from the thickness dimension. Considering that the intended resistance R is 800 Ω rather than 40 Ω, and that the QZW ratio is ~10, the preferable pS value is naturally limited. From this point of view, when the upper limit of the thickness dimension t of the resistor is R=40 and Ω, the number of people is determined to be 2,500. Also, Ω to R=100
When R = 200 and Ω, there are 1,000 people, and when R = 200 and Ω, there are 500 people. From this, the upper limit of the cross-sectional area of polysilicon resistor is 2×10''Od or less when R=40Ω or more,
When R = 100 and Ω or more, 8X10-10d or less, R
When it is equal to or greater than Ω=200, it is determined to be equal to or less than 4×10−”Od. However, this value varies depending on the Q/w ratio.

Regarding reliability, in addition to the current density mentioned above, electric field must also be considered. As a result of studying this problem, we found that the ratio of the voltage V (V) applied across polysilicon to the polysilicon length Q [μm], that is, V/Qtt
It was found that the linearity of the resistance could be maintained by controlling the resistance to 4 V/μm or less. The current LSI power supply voltage is 5.2■, and it is not expected that this will increase in the future. However, the voltage actually applied is usually 0.4V, and at most about 2.0V. Therefore, to keep V/Q at 0.4, Q is 2. 5.0 at OV
It is necessary that the thickness is μm or more.

[Effect]

By setting ρ to 0.1Ω・1 or less, LSI
required by the process. Stabilizes resistance fluctuations due to process variations.

When the current density J of the resistor is 5×10δA/cd or less, the optimum value is I.
Since the cross-sectional shape of the resistor is regulated so as to be controlled to X 10'A/a# or less, there is no problem in reliability.

Since the area occupied by the resistor is reduced to a range that maintains balance with respect to the LSI circuit, it does not hinder miniaturization of memory cells and the like.

Furthermore, since the electric field is also controlled to 0.4 V/μm or less, resistance linearity is maintained.

〔Example〕

Example 1 A first embodiment of the present invention will be described below with reference to FIG.

Figure a is a longitudinal cross-sectional view of a polysilicon resistor.

5iaN4 on Si substrate 1 via 5iOz film 2
A polysilicon film 4 with a thickness of 500 μm at a concentration of 7×10” (!
An aN4 film 5 was provided, and the polysilicon 4 was wrapped in a sandwich-like structure with the 5iaNa film. 5iaNa membrane 5
The opening 6 is the connection point of the resistor to other elements.

Figure b is a plan view of the resistor. Resistance width dimension W is 0,8
p m and length Q' were 10.4 pm. Here Q
' = 10.4 μm, the length Q' that structurally acts as a resistance excluding the contact portion is 7 μm, and the length Q that substantially acts as a resistance is 5 μm. This is due to the influence of impurities that enter through the openings 6 in subsequent processes. Therefore, g/w=6.3
becomes. By doping IX1lX10l9δ, as shown in Figure 2, ρ is 0.032.
The exclusive area B shown by the 6-dashed line where Ω・1 is obtained is 0.8μ
mX10.4μmX3 and 25.0μM. However, the actual occupied area A is 16.8 μM. Cross-sectional area S is 0.8
．． umX is 4 for 500 people, and OX is 10-"rm-", so even when 50 μA is applied, the current density J is suppressed to 1.3 x 10"A/cd.

The resistance of this embodiment is as described above *! ga
.

Both b and c were met. Therefore, a single resistor met the conditions for a desirable resistance. Note that the resistance value achieved in this example was 40.3 KΩ, as is clear from (ρxQ)/(txw). Furthermore, FIG. 0 is a cross-sectional view of the resistor of this example in the resistor width direction.

Note that V/Q is 0.4V/μm at 2V/5pm
was secured.

Example 2 In Example 1, ρ was set to 0.1Ω·piece.

Even if 20 μA is applied, J is 5. OX 10'A/dt
It was suppressed. The resistance thus achieved was 126Ω. In Example 1, the stability of J was close to a certain limit value, whereas in Example 2, J
= 5. OX 104A/cd with improved reliability.

Example 3 FIG. 5 shows a third embodiment of the invention.

The feature of this embodiment is that the polysilicon resistors are laid out in lines and spaces with a width of W.
In this example, w=0.5 μm is selected and the dashed line B
The resistance formation area surrounded by is 25μ-1, and the actual dynamic resistance area is ~21μ-1 surrounded by the dashed line A. 21
is a region forming a resistor, and 22 is a connection point to other elements. ρ is 0.033Ω・1, polysilicon thickness t is 50
There were 0 people. In such a resistance Q/w is essentially 3
2 was secured. The resistance achieved by this is 211
It was Ω. Resistance cross section is 2,5 x 10″″10
d, when a current of 10 μA is applied, the current density J is 4, OX
It was No. 10 A/al. Also, V/n is 0.125V
/μm. It is unnecessary to explain that ρ, J, V/, Q, and the resistance area are all conditions that can achieve the object of the present invention.

Embodiment 4 FIG. 6 shows a fourth embodiment of the present invention. This embodiment has the same resistance layout area A as the second embodiment shown in FIG. It has been reduced by miniaturization, and the connection area to the common ground element has a loose layout. That is, in this example, the width dimension W of the poly-Si resistor
is set to 0.25 μm, and the layout is performed using spaces of the same width W. In this example, the polysilicon thickness is 500, and the Q
The lW ratio is 64. Q was 16 μm. ρ to 0.064Ω
・Controlled to G, R achieved 820Ω.

Example 5 FIG. 1 shows a fifth embodiment of the invention.

This embodiment is laid out with the same width W and space w (w=0.25 μm) as the third embodiment shown in FIG. 6, and miniaturization is achieved as a whole. In the case of this embodiment, the occupied area B is 19 μM, and the resistance portion A is 889 μM.

However, the Q/w ratio is 52. Q=13 μm has been secured. In other words, compared to Example 2, the area was reduced by 24%, and the resistance that could be achieved was approximately the same, 675Ω.

Next, the process of this embodiment will be explained based on FIG. 4.

The Si substrate 1 is Sifted to a thickness of 4000 mm using a thermal oxidation method.
Film 2 was formed. After that, 5iaN is applied by CVD method.
A film 3 was formed to a constant thickness of 500 cm at 780° C. using 5i)lzclz and N Hs as a source, and then a polysilicon film 4 was formed by CVD to a constant thickness of 500 cm at 50° C. for 5 iH.
A was formed as a source, photoresist was applied and patterned, and then polysilicon film 4 was locally left by a known dry etching method. Thereafter, a 5iaN4 film 5 was formed by the CVD method, and the region 6 of the film was etched away.

Embodiment 6 FIG. 7 shows an embodiment in which the polysilicon resistor of the present invention is applied in combination with a transistor for an LSI device. SB was formed in a local region 51 of a p-type semiconductor substrate 50 by a thermal diffusion method, and then an epitaxial layer was formed, and further, local regions 52 and 53 of the epitaxial layer were left in a convex shape, and the others were removed by etching. Next, a thick 5ift film 54 was formed on the concave portions, and a thin 5iOz film 55 was formed on the convex sidewalls by a method such as leaving the sidewalls of the 5iaN4 film. After that, follow the process of forming the polysilicon resistor described above.

5iaN number membrane 56. Polysilicon 57, 5iaNa film 5
8 was formed, and a hole was opened in the region 59 of the Si3N4 film 58. Next, openings 60 and 61 were formed in the upper part of the island 52, and a polysilicon layer 2.63 was provided around the island 52, and this was oxidized to form a SiO2 film 65 on the surface of the polysilicon. At this time, the polysilicon 66 is a dummy polysilicon that prevents the polysilicon resistance portion 57 region from becoming a depression compared to the polysilicon for the island 52.

The basics of such a transistor are disclosed in, for example, Japanese Unexamined Patent Publication No. 56-1
556, the feature of this embodiment described here is that the crystal defects that occur during the oxidation of the polysilicon layers 2,63 are
Since it is in contact with the 5iaNa film, oxidation of the bottom surface can be prevented. The effects of this are enormous. In other words, this embodiment is not limited to forming polysilicon resistors, but also leads to process improvements.

In FIG. 7, a base layer and a collector layer, or a collector layer and a base layer are formed on each of the islands 52 and 53.

Although the embodiments described above have been described in relation to bipolar memory cells and LSI circuits, the polysilicon resistor of the present invention is not limited to these, and can be widely applied to linear circuits, analog circuits, etc. Needless to say.

〔Effect of the invention〕

According to the present invention, the process stability that conventionally occurs with polysilicon resistors is improved, the area occupied for resistor formation is reduced, and problems related to current density and electric field are solved.

That is, the specific resistance ρ is suppressed to 0.1□ Ω·G or less, the exclusive area is suppressed to 25μ or less, the current density is suppressed to 5×10 6 A/d or less, and the electric field is suppressed to 0.4V/μm or less.

As described above, the present invention provides a stable resistance value of 40
Polysilicon resistances ranging from Ω to 800 Ω have been realized, and are particularly effective in bipolar memories and SI open circuits.

[Brief explanation of the drawing]

1st. Fifth. FIG. 6 is a plan view showing an embodiment of the present invention. Figure 2 is a graph of experimental values showing the relationship between polysilicon resistivity and doping concentration, Figure 3 is a circuit diagram of a bipolar memory cell, and Figure 4 is for explaining the structure and formation process of polysilicon resistors. FIG. 7 is a vertical cross-sectional view of a semiconductor device according to another embodiment of the present invention. 4.21, 31.41...Polysilicon resistance, 6°2
2.32, 42.59...Open hole, 62...Base contact agent Patent attorney Katsuo Ogawa",' vl1 Figure 7 Figure 41.57 Thurs. 2 Figure ÷ ° conversion "shift °" 4hikoN cc4fL-s,) 3rd
Times Qxsr UJ? r) - Ra〉Disk￥0 4 Fig. 3 Neorisilicon IL, 5 Sε3tJ4 million 粱t KO〉7ri#子mu■ 5 Fig.￥J z Fig. B Resistance register vortex area

Claims (1)

[Claims] 1. A polysilicon resistor made of a polycrystalline silicon layer formed on a semiconductor substrate with an insulating film interposed therebetween, the resistor having a specific resistance of 0.1 Ω·cm or less and a cross-sectional area of the resistor. is 1×
10^-^1^0 cm^2 or more, the resistance length is 5 μm or more, the width of the resistor is 0.8 μm or less, and the thickness of the resistor is 125 Å or more, and the resistance value is controlled from 40 KΩ to 800 KΩ. A polysilicon resistor characterized by: 2. The cross-sectional area of the resistor is 4 x 10^-^1^1cm^2 or more, the thickness of the resistor is controlled to be 50 Å or more, and the resistance is 100K.
The polysilicon resistor according to claim 1, having a resistance value in the range of 800KΩ from Ω. 3. The cross-sectional area of the resistor is 2 x 10^-^1^1 cm^2 or more, the thickness of the resistor is controlled to be 25 Å or more, and the resistance is 200K.
The polysilicon resistor according to claim 1, having a resistance value in the range of 800KΩ to Ω. 4. The polysilicon resistor described in claims 1 to 3 has a surface covered with a nitride film,
A semiconductor device characterized in that the semiconductor device is connected to a base region or a collector region of a transistor via another different polysilicon film through an opening locally formed in the nitride film.