JP2685498B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a polysilicon resistance suitable for realizing a high resistance of about 40 KΩ to 800 KΩ used in a bipolar memory circuit or the like. .

[Conventional technology]

A resistor used in a semiconductor integrated circuit device is generally formed in a region for element isolation called isolation for the purpose of reducing parasitic capacitance and achieving high integration. Such a resistance is usually polysilicon (poly
Although it is realized by using a Si) layer, it has been conventionally used for low resistance of several KΩ or less or for ultra-high resistance of several tens of GΩ or more.

Regarding the former, for example, Solid State Electronics, Volume 20 (1977), pages 883 to 889 (So
lid-State Electronics, vol.20 (1977), pp.883-889)
Are discussed in Regarding the latter, for example, IMD, Technical Digest, 198
6th year, pages 300 to 303 (Technical Digest of IEDM
(1986), pp300-303).

By the way, recently, regarding resistance in the region of approximately 40 KΩ to 800 KΩ, Japanese Patent Application Nos. 62-128137 and 63-10641 describe measures for improving temperature characteristics.

[Problems to be solved by the invention]

However, the technology with a resistance value of about 40 KΩ to 800 KΩ is insufficient in consideration of stability of a process, area dedicated for b resistance formation, and c reliability, and is effectively applied to LSI circuits. Above it became clear that there was a problem.

An object of the present invention is to provide a polysilicon resistor as described above.
It is to solve the three problems of a, b, and c.

[Means for solving the problem]

The above object can be achieved by forming a polysilicon resistor under the conditions controlled by the respective problems a to c.

Problem a: Process stability Fig. 2 shows the relationship between the resistivity ρ of polysilicon and the doping concentration. ○ marks are experimental values. Experimental value is 11, 12, 13
It can be divided into three regions indicated by the tangent lines. Of these,
The tangent line 12 is a region in which ρ changes by 5 digits when N changes by 1 digit, so that process stability cannot be obtained. The target resistance of the present technology is possible in the area indicated by the tangent line 13. From this ρ
Is a condition of this task. In this region, ρ only changes by one digit even if N changes by one digit.

Problem b: Occupied area The width dimension of the polysilicon resistor is w, and its length dimension is l. Now assume that l / w is 10. At this time, it is assumed that the area occupied for forming the resistance is w × l × 3 times. Furthermore, in the memory LSI circuit to which the resistance is applied, the allowable resistance occupation area is assumed to be 1/10 of the memory cell area.

FIG. 3 is a typical memory cell circuit diagram. The polysilicon resistor is used as a resistor represented by RMC. The current cell area of such a memory cell is ˜500 μm ² . Therefore, the occupation area allowed is 50 μm ² , but
As is clear from the figure, normally, one memory cell has two polysilicon resistors. From this, the condition is that the area of one polysilicon resistor is finally 25 μm ² or less.

From such a condition, the limit that w is 0.8 μm or less is determined.

Problem c: Reliability When a high current is applied to a polysilicon resistance, resistance fluctuation occurs. This upper limit is 5 × 10 ⁵ A / cm ² , but if stability is expected, it is safe to set 1 × 10 ⁵ A / cm ² as the upper limit. The maximum current that flows through a polysilicon resistor such as 40KΩ to 800KΩ used in memory LSI circuits is 40μ at 40KΩ.
A. It is 20 μA at 100 KΩ and 10 μA at 200 KΩ. Therefore, the cross-sectional area S of the polysilicon resistor, which does not exceed the current density J of 5 × 10 ⁵ , is 1 × 1 at 40 KΩ.
0 ^-10 cm ^2, 100KΩ sometimes 4 × 10 ^-11 cm ^2, 200KΩ sometimes 2 ×
Determined to be 10 ^-11 cm ² or more.

From the problems b and c, the lower limit of the thickness t of the polysilicon resistor is w = 0.8 μm and S = 1 × 10 ⁻¹⁰ cm ² or more at 40 KΩ, so S = 4 × 10 ^{− at} 125 Å and 100 KΩ. ¹¹ cm
50 Å to be ² or more, S = 2 × 10 ^-11 cm at 200 KΩ
^{To be 2} or more, it is determined to be 25Å or more.

Furthermore, since ρ = 0.1Ω · cm or less in task a,
The sheet resistance ρs of the polysilicon resistor is automatically determined from the thickness dimension. The target resistance R is 800 from 40KΩ.
Considering that it is KΩ and the l / w ratio is ~ 10,
The preferred ρs value is naturally limited. From this perspective,
2500 when the upper limit of thickness t of the resistor is R = 40KΩ
Determined as Å. When R = 100KΩ, 1000Å, R = 200K
When it is Ω, it is determined as 500Å. From this, the upper limit of the cross-sectional area of the polysilicon resistance is 2 × 10 ^-9 c when R = 40 KΩ or more.
8 x 10 ^-10 cm ² or less, R when m ² or less and R = 100 KΩ or more, R
＝ 200KΩ or more, it is determined to be 4 × 10 ^-10 cm ² or less. However, this value varies depending on the l / w ratio.

Regarding reliability, in addition to the above current density, an electric field must be taken into consideration. As a result of studying this problem, the voltage V [V] applied across the polysilicon is shown.
And the polysilicon length l [μm], that is, V / l is 0.4
It has been found that the linearity of the resistance can be maintained by controlling V / μm or less. The power supply voltage of the current LSI is
At 5.2V, this is not expected to rise in the future. However, the voltage actually applied is usually 0.4V, and the maximum voltage is about 2.0V. Therefore, in order to keep V / l at 0.4, l needs to be 5.0 μm or more at 2.0V.

[Action]

By setting ρ to 0.1 Ω · cm or less, it is possible to stabilize resistance fluctuations due to process variations, which are required for LSI processes.

Resistance current density J is 5 × 10 ⁵ A / cm ² or less, optimal is 1 × 10 5.
^Since the cross-sectional shape of the resistor is regulated so as to be controlled to ⁵ A / cm ² or less, there is no problem in reliability.

The area occupied by the resistors is reduced to a range that maintains a balance with the LSI circuit, so it does not hinder the miniaturization of memory cells and the like.

Furthermore, since the electric field is controlled to 0.4 V / μm or less,
The linearity of resistance is maintained.

〔Example〕

Example 1 Hereinafter, a first example of the present invention will be described with reference to FIG.

FIG. 3A is a vertical sectional view of a polysilicon resistor. Si substrate 1
A Si ₃ N ₄ film 3 is provided on the SiO ₂ film 2, a polysilicon film 4 having a concentration of 7 × 10 ¹⁸ cm ^-3 and a thickness of 500 Å is provided thereon, and then a Si ₃ N ₄ film 5 is provided. It is provided with a structure in which the polysilicon 4 is wrapped with a Si ₃ N ₄ film in the form of a sandwich. Si ₃ N ₄ film 5
The opening 6 is a connection point of the resistor to another element.

Figure b is a plan view of the resistor. Resistance width dimension w is 0.8μ
m and the length l ″ are 10.4 μm. Here, l ″ = 10.4 μm, and the length l ′ that acts structurally as a resistance excluding the contact portion is 7 μm, and further acts as substantially resistance. The length l to be performed is 5 μm. This is due to the influence of impurities that enter through the openings 6 in the subsequent process. Therefore, l / w = 6.3. Due to the doping of 1 × 10 ¹⁹ cm ⁻³ , as can be seen from FIG. 2, ρ is 0.032 Ω · cm. Exclusive area B shown by the broken line
Is 0.8 μm × 10.4 μm × 3 and 25.0 μm ² . However, the substantially occupied area A is 16.8 μm ² . Cross-sectional area S is 0.8 μm ×
It is 4.0 × 10 ^-10 cm ^-2 at 500 Å. Therefore, the current density J was suppressed to 1.3 × 10 ⁵ A / cm ² even when 50 μA was applied.

The resistance of this example satisfies all of the problems a, b, and c described above. Therefore, this resistance satisfies the preferable resistance condition. The resistance value realized in this example is 40.3, as is clear from (ρ × l) / (t × w).
It was KΩ. Furthermore, FIG. 7C shows the resistance of this embodiment,
It is sectional drawing of a resistance width direction.

 The V / l was 2V / 5μm and 0.4V / μm was secured.

Example 2 In Example 1, ρ = 0.1 Ω · cm. Even when a current of 20 μA was applied, J was suppressed to 5.0 × 10 ⁴ A / cm ² . The resistance realized by this was 126 KΩ. In Example 1, the limit value of J was close to the limit value, whereas in Example 2, J = 5.0 × 10 ⁴ A / cm ² ,
Reliability has improved.

Embodiment 3 FIG. 5 shows a third embodiment of the present invention. The feature of this embodiment is that the polysilicon resistors are laid out in line and space of width w. In this example, w = 0.5 μm was selected, the resistance formation area surrounded by the broken line B was 25 μm ² , and the effective resistance region was ˜21 μm ² surrounded by the alternate long and short dash line A. Reference numeral 21 is a region forming a resistor, and 22 is a connection point to another element. ρ is 0.03
3Ω · cm, and polysilicon thickness t was set to 500Å. In this resistance, 32 was secured for l / w. The resulting resistance was 211 KΩ. Resistance cross section is 2.5 x 1
At 0 ^-10 cm ² and current of 10 μA, the current density J is 4.0 ×
It was 10 ⁴ A / cm ² . The V / l was 0.125 V / μm.
It is not necessary to explain that ρ, J, V / l, and the resistance area are conditions that can achieve the object of the present invention.

Embodiment 4 FIG. 6 shows a fourth embodiment of the present invention. This embodiment has the same resistance occupation area B as the second embodiment shown in FIG.
Within the conditions, the resistance layout portion A is reduced by miniaturization, and the connection region to other elements is made to have a gentle layout accordingly. That is, in this embodiment, the width dimension w of the poly-Si resistor is
Is 0.25 μm and is laid out in a space of the same width w. In this embodiment, the polysilicon thickness is 500Å, the l / w ratio is 64,
l was 16 μm. ρ is controlled to 0.064Ωcm, R is 820K
Was realized.

Embodiment 5 FIG. 1 shows a fifth embodiment of the present invention. This embodiment is laid out with the same width w and space w (w = 0.25 μm) as the third embodiment shown in FIG. 6, and miniaturization is achieved as a whole. In the case of this embodiment, the occupation area B is 19μ
At m ² , the resistance portion A is 8.9 μm ² . But the l / w ratio is 5
2, l = 13μm is secured. That is, compared with Example 2, the area was reduced by 24%, and the achievable resistance was 675 KΩ, which was almost the same.

Next, the process of this embodiment will be described with reference to FIG.

A SiO ₂ film 2 having a thickness of 4000 Å was formed on the Si substrate 1 by a thermal oxidation method. After that, the Si ₃ N ₄ film 3 was converted into SiH ₂ Cl ₂ ,
Using NH ₃ as a source, a film with a thickness of 500Å is formed at 780 ℃, and then CVD
Method is used to form a polysilicon film 4 at a thickness of 500Å at 650 ° C. using SiH ₄ as a source, a photoresist is applied, this is patterned, and then a polysilicon film is locally formed by a known dry etching method. 4 was left. After that, a Si ₃ N ₄ film 5 was formed by the CVD method and the local region 6 of the Si ₃ N ₄ film 5 was removed by etching.

Embodiment 6 FIG. 7 is an embodiment in which the polysilicon resistor of the present invention is applied in combination with a transistor for an LSI device. Sb was formed in the local region 51 of the p-type semiconductor substrate 50 by a thermal diffusion method, an epitaxial layer was subsequently formed, and the local regions 52 and 53 of the epitaxial layer were left in a convex shape and the others were removed by etching. Then, a thick SiO ₂ film 54 was formed in the recess and a thin SiO ₂ film 55 was formed in the convex side wall by the method of leaving the side wall of the Si ₃ N ₄ film. Then, following the process of forming the polysilicon resistance described above, the Si ₃ N ₄ film 56, the polysilicon 57, and the Si ₃ N ₄ film 58 are formed.
Was formed, and a local region 59 of the Si ₃ N ₄ film 58 was opened. Next, holes 60 and 61 are formed on the island 52, and polysilicon 62 and 63 are formed on the island.
A SiO ₂ film 65 was provided on the surface of the polysilicon by providing it around 52 and oxidizing it. At this time polysilicon 66
Compared with the polysilicon for island 52,
Dummy polysilicon that prevents the 57 area from becoming a recess.

The basics of such a transistor are disclosed in, for example, JP-A-56-155.
Although it is constructed according to the spirit of No. 6, the feature of the present embodiment described here is that the crystal defects generated during the oxidation of the polysilicon 62, 63 are caused by the polysilicon 62, 63 being Si ₃ N ₄ Since it is in contact with the film, the bottom surface of the film is not oxidized and can be prevented. The effect of this is enormous. That is, the present embodiment is not limited to the formation of the polysilicon resistance, and as a result, it leads to the improvement of the process.

In FIG. 7, each of the base layer and the collector layer, or the collector layer and the base layer is formed on the island 52 and the island 53.

Although the embodiments described above have been described in relation to the bipolar memory cell and the LSI circuit, the polysilicon resistor of the present invention is not limited to them and can be widely applied to linear circuits, analog circuits and the like. Needless to say.

〔The invention's effect〕

According to the present invention, the stability of the process that has been conventionally caused by a polysilicon resistor can be measured, the area occupied by the resistor can be reduced, and the problems relating to the current density and the electric field can be solved. That is, the specific resistance ρ can be suppressed to 0.1 Ω · cm or less, the occupied area to 25 μm ² or less, the current density to 5 × 10 ⁵ A / cm ² or less, and the electric field to 0.4 V / μm or less.

As described above, according to the present invention, the stable resistance value 40
Polysilicon resistance from KΩ to 800KΩ has been realized, and it is particularly effective in bipolar memory LSI circuits.

[Brief description of the drawings]

1, 5, and 6 are plan views showing an embodiment of the present invention.
FIG. 2 is a graph of experimental values showing the relationship between the polysilicon specific resistance and the doping concentration, FIG. 3 is a circuit diagram of a bipolar memory cell, and FIG. 4 is a process for forming a structure of a polysilicon resistor. FIG. 7 is a vertical sectional view, a plan view and a horizontal sectional view, and FIG. 7 is a vertical sectional view of a semiconductor device according to another embodiment of the present invention. 4,21,31,41 …… Polysilicon resistance, 6,22,32,42,59 ……
Opening, 62 ... Base connection polysilicon.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toru Nakamura 1-280, Higashi Koikekubo, Kokubunji City, Tokyo Metropolitan Research Laboratory, Hitachi, Ltd. (56) References JP-A-60-9135 (JP, A)

Claims (1)

(57) [Claims] 1. A semiconductor substrate, a polycrystalline silicon resistor formed on the semiconductor substrate via an insulating film and having a resistance value in the range of 40 KΩ to 800 KΩ, and connected to the polycrystalline polysilicon resistor. Comprised of a transistor, the polycrystalline silicon resistor has a specific resistance of 0.1 Ω · cm or less,
The cross-sectional area is 2 × 10 ^-11 cm ² or more, the length is 5 μm or more, and the width is 0.
A semiconductor device having a thickness of 8 μm or less and a thickness of 25 Å to 2500 Å, respectively.