KR920010669B1 - Semiconductor device and its manufacturing method - Google Patents

Abstract

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Description

Semiconductor device and manufacturing method

1 is a cross-sectional view illustrating device steps in a process of manufacturing a semiconductor device according to a first embodiment of the present invention.

2 is a cross-sectional view illustrating device processes according to a process of manufacturing a semiconductor device according to a second exemplary embodiment of the present invention.

3 is a cross-sectional view illustrating device processes according to a process of the method of fabricating the semiconductor device according to the third embodiment of the present invention.

4 is a cross-sectional view illustrating device processes according to a process of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 5 is a device cross-sectional view illustrating processes for manufacturing a semiconductor device in accordance with a fifth embodiment of the present invention. FIG.

FIG. 6 is a device cross-sectional view illustrating processes for fabricating a semiconductor device in accordance with a sixth embodiment of the present invention. FIG.

FIG. 7 is a device cross-sectional view illustrating processes of fabricating a semiconductor device in accordance with a seventh embodiment of the present invention. FIG.

8 is a cross-sectional view illustrating device processes according to a process of fabricating the semiconductor device according to the eighth embodiment of the present invention.

9 is an explanatory diagram for comparing the resistance values in the manufacturing method of the semiconductor device according to the first to eighth embodiments of the present invention with the conventional manufacturing method.

10 is a circuit diagram of a semiconductor device to which the present invention can be applied.

11 is a device cross-sectional view showing a process for manufacturing a conventional semiconductor device.

12 is a circuit diagram of a semiconductor device to which the present invention can be applied.

13 is a device cross-sectional view for each process showing a conventional method for manufacturing a semiconductor device.

* Explanation of symbols for the main parts of the drawings

1 semiconductor substrate 2 gate oxide film

3: field oxide film 4,32,53,65,65a, 65b: polysilicon

5,5a, 34,41,41a, 54,54a, 62,62a: disilicide

6,22,42,52,63 Resist 11,11a, 21,21a, 33,33a Silicon oxide film

12,23 conductor film 31,51,51a, 61 interlayer insulating film

R103, R123, R124: Resistance

[Industrial use]

The present invention relates to a semiconductor device and a manufacturing method thereof.

Conventional Technology and Issues

10 shows a circuit of a semiconductor device having a MOS transistor. Here, a resistor R103 having a relatively high resistance value is used as an input protection circuit on the gate 101a side of the MOS transistor Q101. The resistor R103 is formed in the layer formed at the same level as the gate 101a electrode. 11 is a cross-sectional view for each process in this case.

First, as shown in FIG. 11A, a gate oxide film 2 and a field oxide film 3 are formed on the surface of the semiconductor substrate 1, and polysilicon is deposited on the surface thereof to form a polysilicon film 4. The above-described resistor R103 and the gate 101a are formed in the silicon film 4. In recent years, as shown in FIG. 11B, a high melting point metal silicide such as molybdenum silicon (MoSi ₂ ) or tungsten silicon (WSi ₂ ) is disilicided on the surface of the polysilicon film 4 as shown in FIG. 11B. ) Is often formed as a polyside structure in which splices are laminated by sputtering to form wiring in the disilicide film 111.

However, in the case of forming the wiring in such a structure, since the layer on which the resistor R103 is to be formed also becomes a polyside structure, the resistance value becomes small due to the disilicide film 111 to serve as a protective resistance. There will be no. Therefore, in order to increase the resistance value, the length of the resistor must be increased. In the case of forming a wiring with a polyside structure, the resistance value is reduced to 1/10. Therefore, in order to obtain the resistance value as in the related art, the resistance length must be increased by 10 times. As a result, it is virtually impossible to realize. For this reason, there is a problem that a resistance with sufficient protection cannot be obtained.

Next, a semiconductor device including an enhancement resist type static RAM (E / R type SRAM) will be described. The circuit diagram in this case is shown in FIG.

The illustrated circuit diagram shows a flip-flop using MOS-type FETs Q121 and Q122. Resistors R123 and R124 are connected to the drains of transistors Q121 and Q122. ) Is required to have a high resistance value. 13 is a cross-sectional view for each process at the time of forming the resistors R123 and R124 in this case.

First, as shown in FIG. 13A, an interlayer insulating film 31 is formed on the surface of the semiconductor substrate 1, and polysilicon is deposited thereon to form a polysilicon film 32. As shown in FIG. The polysilicon film 32 is patterned by photolithography to form wiring.

Subsequently, as shown in FIG. 13B, after the resist is applied to the entire surface, the resist film 131 is left only in the region where the resistor R123 or R124 is to be formed. As an impurity, for example, arsenic (As) is used for ion implantation using the resist film 131 as an ion implantation mask, and the resistance value of the region 32a of the remaining portion of the polysilicon film 32 except for the region 32b is lowered. do. The resistors R123 and R124 are formed in the high resistance region 32b thus obtained. In this case, there are the following problems.

An impurity such as arsenic shown in FIG. 13B is heat-treated to activate the impurity in the ion implantation step, and the fine high-resistance region is diffused because the impurity diffuses about 0.5 to 1.0 탆 into the high-resistance region 32b. It is difficult to form the resin with good controllability. In particular, when the length of the region 32b is less than or equal to 3 μm, impurities are diffused and the resistance value decreases as in the state where both ends of the region 32b are short-circuited, thereby making it impossible to function as a resistance element.

As described above, in a semiconductor device having a MOS transistor, when a resistive element for input protection is formed in the same layer as the gate electrode, a resistive element having a sufficient resistance value is formed when the wiring is formed in a polyside structure. There is a problem in that it is virtually impossible to do and cannot play the role of an integrated circuit.

In addition, when forming a resistor connected to the drain in the same layer as the wiring portion in a semiconductor device having an E / M type SARM, there is a problem that it is difficult to form a region having a fine fixed term with good controllability.

[Purpose of invention]

SUMMARY OF THE INVENTION The present invention has been invented to solve the above-mentioned problems. In the semiconductor device with MOS transistors, a region having a high resistance value for forming a resistance element for input protection can be formed and at the same time speeding up circuit operation. In the method of manufacturing the semiconductor device which can be achieved, and also in the semiconductor device having the E / M type SRAM, fine high resistance region for forming the resistance connected to the drain can be formed on the same layer as the wiring section with good controllability. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of achieving a high speed circuit operation and a semiconductor device manufactured by the method.

[Configuration of Invention]

A method of manufacturing a semiconductor device according to the present invention includes the steps of forming a first resistive film made of a material having a first resistance value on a surface of an insulating material layer on a semiconductor substrate, and the first resistor on the surface of the first resistive film. Forming a second resistive film made of a material having a second resistive value lower than the value; patterning the second resistive film to form wiring and a resistive element; and a predetermined portion of the second resistive film including the resistive element The photoresist layer is removed by photolithography to expose the first resistive film.

In addition, a silicon oxide film is formed on the surface of the formed first resistive film, and a predetermined region of the silicon oxide film is etched back to expose the first resistive film, and a second resistive film is formed only on the surface of the exposed portion. The first resistive film may be exposed by removing using a photolithography method leaving only a predetermined region of the formed silicon oxide film, and the second resistive film may be formed only on the exposed portion of the first resistive film.

In addition, after the thickness of the portion of the formed insulating material layer other than the predetermined region is thinned by the photolithography method, a first resistive film is formed on the entire surface of the insulating material layer, and a second resistive film is formed on the entire surface of the first resistive film. It may be formed to etch back and expose a predetermined region in the first resistive film.

In addition, a second resistive film is formed on the entire surface of the formed insulating material layer, and a predetermined region of the second resistive film is removed by photolithography to expose the insulating material layer to form a first resistive film on the entire surface. The resistive film may be removed by a photolithography method so that a portion corresponding to the predetermined region remains, or the thickness of the first resistive film remaining after the removal may be equal to the thickness of the second resistive film.

In addition, the semiconductor device of the present invention is characterized by having the first resistive film and the second resistive film thus formed.

Herein, the material having the first resistance value is at least one material selected from polysilicon, manganese oxide, tungsten oxide, and silicon oxide.

The material having the second resistance value is at least one material selected from molybdenum silicide, tungsten silicide, titanium silicide, tantalum silicide and metal materials.

[Action]

According to the present invention configured as described above, a resistance element having a resistance value necessary as a resistance element is formed by forming a resistance element in a first resistance film made of a material having a first resistance value that is larger than the second resistance value and is relatively large. The circuit operation is speeded up by forming a wiring in the second resistive film made of the second material which is obtained and whose resistance is lower than the first resistive value.

This is also true of either of the two manufacturing methods described above.

Therefore, the resistive element in the semiconductor device thus formed has the necessary resistance value as the resistive element, or the circuit operation is also speeded up.

In the case of forming the second resistive film, when impurity ions are injected into a predetermined region of the first resistive film and thermally diffused to obtain the second resistive film and the first resistive film, impurities are deposited in the predetermined region of the first resistive film by thermal diffusion. In addition, it is difficult to form the second resistive film with good controllability because it diffuses to the region. However, in any of the manufacturing methods described above, the photolithography method is used without going through such a process, so that the fine first and second resistors are used. The film is easily formed.

EXAMPLE

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, in a semiconductor device having a MOS transistor, the first to third embodiments in the case where a resistive element for input protection is formed in the same layer as the gate electrode will be described. 1 is a cross-sectional view of the device for each process of the first embodiment.

First, as shown in FIG. 1A, the surface of the semiconductor substrate 1 is thermally oxidized to form a gate oxide film 2 having a thickness of 100 to 250 kPa on the surface, and an oxidation resistant film such as a nitride film is selectively selected only on the element formation region. After the deposition was carried out in a oxidizing atmosphere, the field oxide film 3 for device isolation was selectively formed to have a thickness of 4000 to 6000 에만 only in the device isolation region, and then polysilicon was deposited on the entire substrate by chemical vapor deposition (CVD). Is deposited to a thickness of about 2000 GPa to form a polysilicon film 4.

Next, as shown in FIG. 1B, disilicide such as molybdenum silicide is laminated on the surface of the polysilicon film 4 by sputtering to form a dissilicide film 5 having a film thickness of 1500 to 2000 GPa. Then, the polysilicon film 4 and the disilicide film 5 are patterned to form wiring and resistance elements.

Then, the resist 6 is applied to the surface of the disilicide film 5, and the disilicide film 5 of the portion corresponding to the region in which the resistive element for input protection is to be formed as shown in FIG. Is removed to form the disilicide film 5a, and the resist film 6 is removed after exposing the surface of the polysilicon film 4 in the predetermined region.

Next, a cross-sectional view for each process of the second embodiment is shown in FIG. As shown in FIG. 2A, the gate oxide film 2 and the field oxide film 3 are formed on the surface of the semiconductor substrate 1, and the polysilicon film 4 is 4000 Å and the silicon oxide film 11 is 4000 to 10000 Å on the surface. Each one is formed by sequentially depositing.

Next, if a resist is applied to the entire surface of the silicon oxide film 11 and the etching is performed slowly while checking the time, the silicon oxide film 11 on the surface of the field oxide film 3 is etched back and removed as shown in FIG. (4) is exposed.

As shown in FIG. 2C, the conductive layer 12 is formed by selectively growing a metal such as tungsten on the surface of the exposed polysilicon 4 selectively by CVD.

Subsequently, a resistance element is formed in the silicon oxide film 11, and wirings are formed in the conductor film 12, respectively.

3 is a cross-sectional view for each process of the third embodiment. As shown in FIG. 3A, a polysilicon film 4 is formed on the surface of the gate oxide film 2 and the field oxide film 3 formed on the semiconductor substrate 1 to a thickness of 2000 microseconds, and the silicon oxide film 21 is 1500 to 2000 microseconds thereon. It is formed to a thickness of.

Subsequently, a resist is applied on the entire surface of the silicon oxide film 21, and other portions are removed while leaving only the silicon oxide film 21a and the resist 22 in a predetermined region as shown in FIG. 3b.

Next, the resist 22 is removed and a metal such as tungsten is selectively grown on the exposed surface of the polysilicon film 4 as shown in FIG. 3C to form the conductor film 23 by CVD.

Then, a resistive element is formed in the silicon oxide film 21a by patterning, and a wiring and a gate coral film are formed in the conductor film 23.

As described above, according to the embodiment of FIGS. 1 to 3, the circuit operation is accelerated by forming wiring in the disilicide film or the conductive film made of metal having low resistance value, and the resistance is higher than that of the disilicide film or the conductor film. A sufficient protection function can be provided by forming a resistance element for a protection circuit in a high-value polysilicon film. Furthermore, in the third embodiment, since the flat surface is formed by the same thickness as the silicon oxide film 21a and the conductor film 23, there is no adverse effect on the step coverage of the wiring layer stacked thereon.

Next, the fourth to eighth embodiments in the case of a semiconductor device having an E / R type SRAM will be described. Here, the formation of the resistance element and the wiring connected to the drain of the MOS type FET is performed at the same level.

First, a semiconductor device and a manufacturing method thereof according to the fourth embodiment will be described with reference to FIG. 4 is a cross-sectional view for each step in the manufacturing method in this case. As shown in FIG. 4A, silicon oxide is deposited 2000 표면 on the surface of the semiconductor substrate 1 by CVD to form an interlayer insulating film 31. Polysilicon is deposited on the surface of the interlayer insulating film 31 by about 500 microseconds by CVD to form a polysilicon film 32.

Next, as shown in FIG. 4B, silicon oxide film 33 is formed on the surface of polysilicon film 32 by CVD to form about 1000 GPa.

Subsequently, a resist is applied on the surface of the silicon oxide film 33, and only the silicon oxide film 33a in a predetermined region remains and the silicon oxide film 33 in another region is removed by photolithography as shown in FIG. 4C. Is exposed.

Subsequently, the conductive film 34 is formed by selectively growing a metal material such as tungsten to have the same thickness as the silicon oxide film 33a by selectively depositing only the surface of the exposed polysilicon film 32 as shown in FIG. 4D.

Then, patterning is performed to form a resistance element in the silicon oxide film 33a and to form a wiring in the conductor film 34.

By this manufacturing method, the semiconductor device according to the present embodiment is obtained.

5 shows a fifth embodiment. First, similarly to the fourth embodiment, as shown in FIG. 5A, polysilicon is deposited on the surface of the interlayer insulating film 31 on the semiconductor substrate 1 by 500 CVD to form a polysilicon film 32. As shown in FIG.

Next, as shown in FIG. 5B, 500 to 1000 Pa is deposited on the surface of the polysilicon film 32 by a disilasiide CVD method such as molybdenum silicide to form a disilicide film 41.

Then, a resist is applied to the surface of the disilicide film 41, and only a predetermined region is removed using a photolithography method to form the disilicide film 41a and the resist 42 as shown in FIG. 5C. The surface of the polysilicon film 32 of is exposed.

Next, as shown in FIG. 5D, the resist 42 is removed and patterned to form a resistance element in the exposed polysilicon film 32, and a wiring is formed in the disilicide film 41a.

Next, an eighth embodiment will be described. Unlike the fourth and fifth embodiments described above, silicon oxide is deposited on the surface of the semiconductor substrate 1 to have a thickness of 4000 kPa as shown in FIG. 6A to form an interlayer insulating film 51.

A resist is applied to the surface of the interlayer insulating film 51, and as shown in FIG. 6B, the thickness of the interlayer insulating film 51 other than the predetermined area is removed by the photolithography method so that the thickness is 500 to 1000 Å thinner than the thickness of the predetermined area. After the resist is formed, the resist 52 is removed.

Subsequently, as shown in FIG. 6C, polysilicon is deposited on the surface of the interlayer insulating film 5a to form a polysilicon film 53. As shown in FIG. Further, a silicide such as molybdenum silicide is deposited thereon to form the disilicide film 54.

Then, as shown in FIG. 6D, the portion corresponding to the predetermined region having a thick thickness of the interlayer insulating film 51a is removed by the etch back method to form the disilicide film 54a. Corresponding polysilicon film 53 is exposed. Then, a resistance is formed in the polysilicon film 53 of the exposed portion by patterning, and a wiring is formed in the dissilicide film 54a.

7 is a cross-sectional view of each process of the seventh embodiment. First, as shown in FIG. 7A, an interlayer insulating film 61 is formed on the semiconductor substrate 1, and disilicide such as molybdenum silicon is deposited on the semiconductor substrate 1 by CVD to form a disilicide film 62.

Next, a resist is applied onto the disilicide film 62, and only a predetermined region is removed by a photolithography method to form the disilicide film 62a as shown in FIG. 7B, and then the resist 63 is removed.

Subsequently, as shown in FIG. 7C, polysilicon is deposited on the entire surface to form a polysilicon film 65. As shown in FIG. 7D, a portion of the polysilicon film 65 corresponding to a predetermined region from which the disilicide film 62 is removed is formed. The remaining portion of the disilicide film 62 is removed using a photolithography method to form a polysilicon film 65a.

Thereafter, the polysilicon film 65a is formed in a resistance element, and a wiring is formed in the disilicide film 62a.

8 is a cross-sectional view for each process of the eighth embodiment. In this embodiment, the steps up to forming the polysilicon film 65 shown in FIG. 7C in the seventh embodiment are the same (FIG. 7A).

Thereafter, the thickness of the polysilicon film 65 coincides with the thickness of the disilicide film 62a so that the polysilicon film 65 remains only in a portion corresponding to the predetermined region from which the silicide film 62 is removed. The polysilicon film 65b is formed using photolithography so as to form the film.

Then, a resistance element is formed in the polysilicon film 65b, and wiring is formed in the disilicide film 62a.

As described above, since impurities are implanted into a predetermined region in a region having a high resistance value and thermally diffused to form a region having a low resistance value at the same level as a region having a high resistance value, the implanted impurity diffuses out of the predetermined region. It was difficult to form a fine high resistance region with good controllability. On the other hand, in the manufacturing method according to the fourth to eighth embodiments, each region is formed using the photolithography method as described above without using the method of ion implantation and thermal diffusion, so that the fine high resistance region can be formed with good controllability. In the semiconductor device according to the fourth embodiment, such a fine high resistance region is formed with good controllability.

In addition, in the eighth embodiment, since the thickness of the disilicide film 62a and the thickness of the polysilicon film 65b coincide with each other, a flat surface is formed, the effect of not adversely affecting the step coverage of the wiring layer formed above this layer. There is.

Next, the resistance value of the region which should have the high resistance value formed for forming the resistance element is compared with the case according to the first to eighth embodiments and the case according to the conventional manufacturing method. 9 shows the change of the resistance value with respect to the length of this resistance element formation region. In the conventional case, when the length of the resistive element forming region is 3 mu m or less, the resistance value is drastically lowered. However, in the present embodiment, the resistance value is almost constant regardless of the length of the resistive element forming region. As a result, in the present embodiment, a high resistance region for forming a fine resistance element can be formed with good controllability.

In addition, in this embodiment, this invention is not limited to either example. For example, polysilicon is used as the material having the first resistance value, but other materials such as manganese oxide, tungsten oxide, and silicon oxide suitable for forming the resistance element may be used. In addition, although molybdenum silicide and a metal material are used as the material having the second resistance value, other disulfides such as tungsten silicide, titanium silicide, and tantalum silicide may be used as materials that can form wiring and achieve high speed of circuit operation. You may use it.

[Effects of the Invention]

As described above, according to the method of manufacturing a semiconductor device according to the present invention, when the MOS transistor is provided, a first resistive film is formed on the insulating material layer, and a predetermined area of the surface is removed to remove the resistive value of the first resistive film. These low second resistive films are formed so that a resistive element for input protection is formed in each of the first resistive films, and a resistive element having a high resistance value necessary for input protection is formed to form a wiring in the second resistive film, and furthermore, High speed circuit operation can be achieved.

In the case of the E / R type SRAM, a first resistive film is formed on the insulating material layer, and a predetermined area of the surface is removed to form a second resistive film having a lower resistance value than the first resistive film or on the insulating material layer. Two resistive films are formed, and a predetermined region on the surface thereof is removed to form a first resistive film having a higher resistance value than the second resistive film, each having a resistive element connected to the drain of the MOS type FET; By forming a wiring in the two resistive films, a region for forming a fine resistive element can be formed with good controllability, and at the same time, the speed of circuit operation can be achieved.

In addition, the semiconductor device manufactured by this method has a region having a fine high resistance value and can perform a circuit operation at a high speed.

Claims (9)

A first resistive film 4 formed on the surfaces of the insulating films 2 and 3 and made of a material having a first resistance value, a silicon oxide film 21a formed only in a predetermined region on the surface of the first resistive film, and A second resistive film 23 formed of a material having a second resistivity lower than the first resistive value and formed in a region other than the predetermined region on the surface of the first resistive film is provided, and the silicon oxide film 21a is provided. A semiconductor device, characterized in that a resistance element is formed and a wiring is formed in the second resistance film (23). Forming a first resistive film 4 made of a material having the first resistive value on the surfaces of the insulating material layers 2 and 3 on the semiconductor substrate 1; and forming the first resistive film 4 on the surface of the first resistive film. Forming a second resistive film 5 made of a material having a second resistive value lower than the first resistive value, patterning the second resistive film 5 to form wiring and a resistance element; 2. A method of manufacturing a semiconductor device, comprising the step of removing a predetermined region of a resistive film (5) by photolithography to expose the first resistive film (4). Forming a first resistive film 4 made of a material having a first resistance value on the surfaces of the insulating material layers 2 and 3 on the semiconductor substrate 1, and the surface of the first resistive film 4. Forming a silicon oxide film 11 on the substrate, etching a predetermined region of the silicon oxide film 11 to expose the first resistive film 4, and exposing the first resistive film 4 Forming a second resistive film 12 made of a material having a second resistive value lower than the first resistive value only in the portion where it is formed, and forming a wiring in the second resistive film by patterning to resist the silicon oxide film. A method of manufacturing a semiconductor device, comprising the step of forming an element. Forming a first resistive film 4 made of a material having a first resistance value on the surfaces of the insulating material layers 2 and 3 on the semiconductor substrate 1, and a surface of the first resistive film 4. Forming a silicon oxide film 21 made of silicon oxide on the surface and exposing the first resistive film 4 by removing other portions using a photolithography method leaving only a predetermined region 21a of the silicon oxide film. And forming a second resistance film 23 made of a material having a second resistance value lower than the first resistance value only in the exposed portion of the first resistance film, and by patterning the second resistance film 23. And forming a resistor in the silicon oxide film (21). Forming an insulating material layer 51 by depositing an insulating material on the semiconductor substrate 1, and using a photolithography method for the film thickness of the portion 51a of the insulating material layer 51 except for a predetermined region. Thinning, depositing a material having a first resistance value on the entire surface of the insulating material layer 51 to form a first resistive film 53, and forming the first resistive film 53 on the entire surface of the first resistive film 53. Depositing a material having a second resistance value lower than the first resistance value to form a second resistance film 54, etching a predetermined region of the first resistance film 53 to expose it, and patterning Forming a resistive element in the exposed portion of the first resistive film and forming a wiring in the second resistive film (54). Depositing an insulating material on the semiconductor substrate 1 to form the insulating material layer 61; depositing a material having a second resistance value on the entire surface of the insulating material layer 61 to form a second resistive film 62; ), Exposing the insulating material layer 61 by removing a predetermined region of the second resistive film using a photolithography method, and applying a first resistive value higher than the second resistive film to the entire surface. Depositing a material to have a first resistive film 65, removing the photoresist process so that a portion 65a of the first resistive film 65 corresponding to the predetermined region remains; And forming a resistance element in said first resistive film (65) left by patterning and forming a wiring in said second resistive film (62). Depositing an insulating material 61 on the semiconductor substrate 1 to form an insulating material layer 61, and depositing a material having a second resistance value on the entire surface of the insulating material layer 61 to form a second resistance. Forming a film 62, removing a predetermined region of the second resistive film 62 using a photolithography method, and exposing the insulating material layer 61; Depositing a material having a higher first resistance value to form a first resistive film 65, and leaving only a portion of the first resistive film 65 corresponding to the predetermined region, and leaving the remaining first Removing by using photolithography so that the thickness of the resistive film 65 matches the thickness of the second resistive film 62, and forming a resistive element on the first resistive film 65b left by patterning; A process for forming a wiring in the second resistive film 62 is provided. . 7. The semiconductor device according to any one of claims 1 to 6, wherein the material having the first resistance value is at least one material selected from polysilicon, manganese oxide, tungsten oxide, and silicon oxide. Way. The semiconductor according to any one of claims 1 to 6, wherein the material having the second resistance value is at least one material selected from molybdenum silicide, tungsten silicide, titanium silicide, tantalum silicide, and metal materials. Method of manufacturing the device.

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