JPS59112641A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS59112641A JPS59112641A JP57221933A JP22193382A JPS59112641A JP S59112641 A JPS59112641 A JP S59112641A JP 57221933 A JP57221933 A JP 57221933A JP 22193382 A JP22193382 A JP 22193382A JP S59112641 A JPS59112641 A JP S59112641A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline silicon
- metal
- resistance
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 238000000034 method Methods 0.000 claims description 18
- 229910021332 silicide Inorganic materials 0.000 claims description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 13
- 150000002500 ions Chemical class 0.000 abstract description 4
- 229910020968 MoSi2 Inorganic materials 0.000 abstract description 3
- 239000010408 film Substances 0.000 abstract 4
- 229920005591 polysilicon Polymers 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 50
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 238000002844 melting Methods 0.000 description 7
- 230000008018 melting Effects 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910004217 TaSi2 Inorganic materials 0.000 description 2
- 229910008814 WSi2 Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 101150114751 SEM1 gene Proteins 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8221—Three dimensional integrated circuits stacked in different levels
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体装置及びその製造方法に係り、特に、
半導体素子の信号入出力端となる電極及びこの電極と外
部回路との間をつなぐ接続線となる配線と高抵抗負荷素
子とを同一基板上に集積してなる半導体装置とその製造
方法に関するもので、例えばＭ ＯＳ （Ｍｅｔａｌ
０ｘｉｄｅ Ｓｅｍ１ｃｏｎｄｕｃｔｏｒ）型電界効果
トランジスタに高抵抗負荷素子を一体的に結合する方式
の半導体装置に適用することができる。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular,
This invention relates to a semiconductor device in which an electrode serving as a signal input/output terminal of a semiconductor element, wiring serving as a connection line connecting this electrode to an external circuit, and a high resistance load element are integrated on the same substrate, and a method for manufacturing the same. , for example, MOS (Metal
The present invention can be applied to a semiconductor device in which a high resistance load element is integrally coupled to a field effect transistor (Oxide Sem1 conductor) type field effect transistor.
従来、半導体集積回路は素子数を減少させる回路上の工
夫に加えて、素子を微細化することによって素子性能の
向上と高密度集積化とを達成してきた。しかしながら、
高密度化に伴なって、配線抵抗が増大してくることから
、配線を伝わる信号の遅延時間が大きくなり、高速化を
妨げる要因の０゛とつとなっている。これに対処して、
上記配線抵抗を低減する方法として、配線材料に低抵抗
多結晶シリコン膜に比べて小さな抵抗率を有する金属を
用いるものが提案されている。金属の４適用方法として
は、金属そのものを用いる方法と金属シリサイド（珪化
物ンを用いる方法とがある。また・構造的には単層で用
いる方法もあるが、現在のシリコン電極ｉ配−線プロセ
スとの互換性が最も良いことから、金属もしくは金属シ
リサイド層と多結晶シリコン層との２層構造が最も多く
用いられる二しかし、この２層構造では、配線は全て低
抵抗となってし甘うため、例えば、スタティック型ＲＡ
Ｍ（Ｒ，ａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ ）
のメモリ素子に用いられる高抵抗負荷素子を同一基板面
上に一体的に形成することが困難である。さらに、あえ
て、スタティック型ＲＡＭの高密度集積化に大きな威力
を発揮する積層型高抵抗多結晶シリコン買置素子を形成
するには、再度多結晶シリコン層を形成しなければなら
ないが、しかしこれで憾、その後の熱処理によって金属
もしくは金属シリサイド層の表面′が酸化されやすく、
製造工程上からも素子構成上からも不安定性が大きくな
るという問題が生じる。Conventionally, semiconductor integrated circuits have achieved improved element performance and higher density integration by miniaturizing the elements in addition to circuit techniques to reduce the number of elements. however,
As the density increases, the wiring resistance increases, which increases the delay time of signals transmitted through the wiring, which is one of the factors that impede higher speeds. To deal with this,
As a method of reducing the wiring resistance, it has been proposed to use a metal having a smaller resistivity than a low-resistance polycrystalline silicon film as the wiring material. There are four ways to apply metal: a method using the metal itself and a method using metal silicide.Also, there is a method using a single layer structure, but the current silicon electrode i-wiring A two-layer structure consisting of a metal or metal silicide layer and a polycrystalline silicon layer is most often used because it has the best compatibility with the process. However, in this two-layer structure, all interconnections have low resistance and are not easy to use. For example, static type RA
M(R,andom Access Memory)
It is difficult to integrally form high resistance load elements used in memory elements on the same substrate surface. Furthermore, in order to form a multi-layered high-resistance polycrystalline silicon element, which is highly effective for high-density integration of static RAM, it is necessary to form a polycrystalline silicon layer again. Unfortunately, the surface of the metal or metal silicide layer is easily oxidized by subsequent heat treatment.
This poses a problem of increased instability both in terms of the manufacturing process and the element configuration.
本発明の目的は、従来技術での上記した問題点を解決し
、高速化のための低抵抗の電極キ配線と高密度集積化の
ための高抵抗の負荷素子とを同一基板面上に同時に堆積
される多結晶シリコン層から形成させることのできる半
導体装置及びその製造方法を提供することにある。An object of the present invention is to solve the above-mentioned problems in the prior art, and to simultaneously provide low-resistance electrode wiring for speeding up and high-resistance load elements for high-density integration on the same substrate. An object of the present invention is to provide a semiconductor device that can be formed from a deposited polycrystalline silicon layer and a method for manufacturing the same.
本発明の特徴は、上記目的を達成するだめに、基板表面
上に堆積させた多結晶シリコン層に選択的に不純物拡散
を行なって同一層内に高抵抗部と低抵抗部とを形成する
工程と、この多結晶シリコン層上に全面にわたって金属
もしくは金属シリサイド層を形成する工程と、上記高抵
抗部の多結晶／１ノコン層上に形成された上記金属もし
くは金属シリサイド層だけを選択的に除去して上層に金
属もしくは金属シリサイド層の無い多結晶ンリコン層か
ら高抵抗負荷素子を形成し上層に金属もしくは金属シリ
サイド層を持つ多結晶ンリコン層から電極・配線を形成
する工程とを含んでなる製造方法とすること、及びこの
ようにして形成さ九た。In order to achieve the above object, the present invention is characterized by a step of selectively diffusing impurities into a polycrystalline silicon layer deposited on the surface of a substrate to form a high resistance part and a low resistance part in the same layer. A step of forming a metal or metal silicide layer over the entire surface of the polycrystalline silicon layer, and selectively removing only the metal or metal silicide layer formed on the polycrystalline/1-contact layer in the high resistance part. A high resistance load element is formed from a polycrystalline silicon layer with no metal or metal silicide layer on the upper layer, and electrodes and wiring are formed from the polycrystalline silicon layer with a metal or metal silicide layer on the upper layer. and how it was formed.
２層構造の電極・配線と単層の高抵抗多結晶７１ノコン
の負荷素子とで構成される半導体装置とするにある。な
お、この場合の金属としては１例えばＭｏ （モリブデ
ン）、Ｗ（タングステン）、Ｔａ（タンタル）、Ｎｂに
オブ）等のひとつが、また金属シ＋Ｕ ”）−イＭトＬ
、 テｉｊ：ＭｏＳｉ２． ＷＳｉ２ 、 ＴａＳｉ２
．Ｎｂ５Ｉ、、 。A semiconductor device is constructed of a two-layer structure of electrodes/wirings and a single-layer high-resistance polycrystalline 71-layer load element. The metal in this case is one such as Mo (molybdenum), W (tungsten), Ta (tantalum), Nb, etc.
, Teij:MoSi2. WSi2, TaSi2
．． Nb5I, .
ＴｉＳｉ□（チタンソリサイド）ｔＰｔｓ＋（白金ソリ
ザイド）等のひとつが使用できる。One of TiSi□ (titanium solicide), tPts+ (platinum solicide), etc. can be used.
以下１本発明の第１の実施例を第１図〜第４図り示す断
面図により説明する。捷ず、第１図に示・すように、シ
リコン基板１の表面に湿式熱酸化法によシ、厚いシリコ
ン酸化膜２と薄いシ１）コン酸化膜６をそれぞれ選択的
に形成する。次に、第２図に示すように、薄いシリコン
酸℃ヒ膜乙の一部分に窓を開け、その後に堆積した多結
晶シリコン層４及び５に対して、例えば、ＣＶ Ｄ （
ＣｈｅｍｉｃａｌＶａｐｏｒ Ｄｅｐｏｓ山ｏｎ）法に
より形成したＳ ｉｏ２膜７をマスクにして、ヒ素など
のｎ形不純物イオン８を打込むことにより、低抵抗多結
晶シリコン層４と高抵抗多結晶シリコン層５とを選択的
に形成する。A first embodiment of the present invention will be described below with reference to sectional views shown in FIGS. 1 to 4. As shown in FIG. 1, a thick silicon oxide film 2 and a thin silicon oxide film 6 are selectively formed on the surface of a silicon substrate 1 by wet thermal oxidation. Next, as shown in FIG. 2, a window is opened in a portion of the thin silicon acid arsenal film A, and the subsequently deposited polycrystalline silicon layers 4 and 5 are coated with, for example, CV D (
The low resistance polycrystalline silicon layer 4 and the high resistance polycrystalline silicon layer 5 are selected by implanting n-type impurity ions 8 such as arsenic using the SIO2 film 7 formed by the Chemical Vapor Deposits method as a mask. to form.
なお、以後の熱処理工程により、低抵抗多結晶シリコン
層４中に導入された不純物は、上記薄いシリコン酸化膜
乙に開けた窓を通してシリコン基板１中にも導入され、
計形拡散層６を形成する。次に、第６図に示すように、
低抵抗多結晶シリコン層４と、高抵抗多結晶シリコン層
５の形成に用いたＳｉＯ２膜７との上面全体にわたって
、例えば、ＭｏＳｉ２． ＷＳｉ２ 、 ＴａＳｉ２．
ＮｂＳｉ。のうちのひとつの高融点金属シリサイド９
を堆積させた後、ホトリソグラフィ法により、低抵抗電
極や低抵抗配線の加（工形酸を行ない、その後、ＭＯ８
型トランジスタ素子とその高抵抗負荷素子とを一体的に
集積する場合であれば、ＭＯ８型トランジスタのドツィ
７ソースとなる低抵抗拡散層６′、６′を形成するため
に、ヒ素などのｎ形不純物イオン８の打込みを行なう。In addition, in the subsequent heat treatment process, the impurities introduced into the low resistance polycrystalline silicon layer 4 are also introduced into the silicon substrate 1 through the window opened in the thin silicon oxide film B.
A meter-shaped diffusion layer 6 is formed. Next, as shown in Figure 6,
For example, MoSi2. WSi2, TaSi2.
NbSi. High melting point metal silicide 9
After depositing, low-resistance electrodes and low-resistance wiring are processed using photolithography, and then MO8
When integrating a MO8 type transistor element and its high resistance load element, it is necessary to use an n-type material such as arsenic to form the low resistance diffusion layers 6', 6' which will become the dots7 source of the MO8 type transistor. Impurity ions 8 are implanted.
最後に、第４図に示すように、高抵抗多結晶シリコン層
５上の高融点金属シリサイド層９だけを選択的に、ホト
リソグラフィ法により除去する。この、上層の高融点金
属シリサイド層７９が除去された高抵抗多結晶シリコン
層５を高抵抗負荷素子として用いることにより、ドレイ
ン、ノースとしてろ、６′を備え、低抵抗多結晶シリコ
ン層４と高融点金属シーリザイド層９との２層構造を有
する低抵抗のゲート電極と、同じく低抵抗多結晶シリコ
ン層４と高融点金属シリサイド層９どの２層構造を有す
る低抵抗の配線とを備えたＭＯ８型トランジスタ素子と
高抵抗多結晶シリコン負荷素子とが同一基板上に形成さ
れることになる。Finally, as shown in FIG. 4, only the high melting point metal silicide layer 9 on the high resistance polycrystalline silicon layer 5 is selectively removed by photolithography. By using this high-resistance polycrystalline silicon layer 5 from which the upper layer high-melting point metal silicide layer 79 has been removed as a high-resistance load element, it is provided with a drain and a north electrode 6', and the low-resistance polycrystalline silicon layer 4 and An MO8 comprising a low resistance gate electrode having a two-layer structure with a high melting point metal silicide layer 9, and a low resistance wiring having a two layer structure such as a low resistance polycrystalline silicon layer 4 and a high melting point metal silicide layer 9. A type transistor element and a high resistance polycrystalline silicon load element are formed on the same substrate.
本発明ｐ第２の実施例を、第５図〜第１１図に示す断面
図により、説明する。これは、シリコン基板に形成した
ＭＯＳ）ランジスタ上に高抵抗多結晶シリコン負荷素子
を形成する場合であえ。まず、第５図に示すように、シ
リコン基板１の表面に、湿式熱酸化法により、厚いシリ
コン酸化膜２と薄いシリコン酸化膜ろをそれぞれ選択的
に形成する。A second embodiment of the present invention will be described with reference to sectional views shown in FIGS. 5 to 11. This is true when a high resistance polycrystalline silicon load element is formed on a MOS transistor formed on a silicon substrate. First, as shown in FIG. 5, a thick silicon oxide film 2 and a thin silicon oxide film 2 are selectively formed on the surface of a silicon substrate 1 by wet thermal oxidation.
次に、第６図に示すように、薄いシリコン酸化膜乙の一
部分の面上に、ＭＯＳ）ランジスタのゲート電極となる
低抵抗多結晶シリコン層４を形成した後、薄いシリコン
酸化膜６を形成し直す。次に、第７図に示すように、Ｃ
ＶＤ法により形成したシリコン窒化膜１０を選択的に一
部分除去した後、ＭＯＳ）ランジスタのドレイン、ソー
スとなるｎ＋型型数散層第８図の６，６〕を形成するた
めに、ヒ素イオン８の打込みを行なう。次に、第８図に
示すように、ＣＶＤ法によりシリコン酸化膜７を堆積さ
せた後、シリコン窒化膜１０上及びＭＯＳトランジスタ
のドレインとなるｎ＋型型数散層６上シリコン酸化膜７
を選択的に除去する。この時、上記ドレインとなる計型
拡散層６上の薄いシリコン酸化膜６も同時にエツチング
されて除去される。その後、シリコン窒化膜１０もウェ
ット・エツチング法により除去する。その後は、第９図
以降に示すように、前記第１図実施例の第２図以降と同
様に、まず、２層構造の下層となる低抵抗多結晶シリコ
ン層４′及び高抵抗多結晶シリコン層５を５ｉｎ２膜７
上に形成（７′１づ、この時に高抵抗多結晶シリコン層
５を形成するためにマスクとして用いた５ｉｎ２膜であ
るりし、その上面全体にわたって、第１ｏ図に示すよう
に、高融点金属シリサイド９を堆積、させた後、ホトリ
ソグラフィ法により、低抵抗電極や低抵抗配線の加工形
成を行ない、上記ＭＯＳ型：・ランジスタに直列の、第
２のトランジスタを同時に集積する場合であれば、この
第２のトランジスタのソースとなるｎ生型拡散層６′（
第１１図９を形成するために、ヒ素イオン８０打込みを
行なう・最後に、第１１図に示すように、高抵抗多結晶
シリコン層５上の高融点金属シリサイド層９だけを、ホ
トリングラフィによシ選択的に除去する。。Next, as shown in FIG. 6, a low-resistance polycrystalline silicon layer 4 that will become the gate electrode of a MOS transistor is formed on a part of the surface of the thin silicon oxide film B, and then a thin silicon oxide film 6 is formed. Try again. Next, as shown in FIG.
After selectively removing a portion of the silicon nitride film 10 formed by the VD method, arsenic ions 8 are added to form an n+ type scattering layer 6, 6 in FIG. Do the typing. Next, as shown in FIG. 8, after depositing a silicon oxide film 7 by the CVD method, the silicon oxide film 7 is deposited on the silicon nitride film 10 and on the n+ type scattering layer 6 which becomes the drain of the MOS transistor.
selectively remove. At this time, the thin silicon oxide film 6 on the meter-shaped diffusion layer 6, which will become the drain, is also etched and removed at the same time. Thereafter, the silicon nitride film 10 is also removed by wet etching. Thereafter, as shown in FIG. 9 and subsequent figures, as in the case of FIG. 2 and subsequent figures of the embodiment in FIG. Layer 5 is 5in2 film 7
A 5in2 film was formed on the top (7'1), which was used as a mask to form the high resistance polycrystalline silicon layer 5, and the high melting point metal was formed over the entire upper surface of the film, as shown in Figure 1o. After depositing the silicide 9, process and form low resistance electrodes and low resistance wiring using photolithography, and if a second transistor in series with the above MOS type transistor is to be integrated at the same time, The n-type diffusion layer 6' (
11 In order to form the structure shown in FIG. 9, arsenic ions 80 are implanted.Finally, as shown in FIG. Remove selectively. .
、以上説明したように、本発明によれば、高速化のため
の低抵抗の電極・配線と高密度集積化のだめの積層型高
抵抗多結晶シリコン負荷素子とを。As explained above, according to the present invention, low-resistance electrodes and wiring for high-speed operation and a laminated high-resistance polycrystalline silicon load element for high-density integration are provided.
同時に堆積した多結晶シリコン層を用いて形成する方式
であることがら、従来技術による高抵抗多結晶シリコン
負荷素子の形成方式に比較して、製造工程を大幅に減縮
させることが可能となり、これにより、安定した製造工
程及び素子構成とすることができ、半導体集積回路の高
速化と高密度化とを同時に実現することができる。Since this method uses a polycrystalline silicon layer deposited at the same time, it is possible to significantly reduce the manufacturing process compared to the method of forming high-resistance polycrystalline silicon load elements using conventional technology. , a stable manufacturing process and element configuration can be achieved, and high speed and high density semiconductor integrated circuits can be realized at the same time.
第１図、第２図、第６図、第４図は本発明の第１の実施
例を説明するだめの断面図、第５図、第６図・第７図、
第８図、第９図、第１０図、第１１図は本発明の第２の
実施例を説明するための断面図である。
符 号 の 説 明
１・・・シリコン基板 ２，３・・・シリコン酸化
膜４・・・低抵抗多結晶シリコン層
５・・・高抵抗多結晶シリコン層 ６，６′・・・ｎ＋
型型数散層７７′・・・ＣＶＤ法によるＳｉＯ□膜
８山ヒ素イオン９・・・高融点金属シリサイド層
１０・・シリコン窒化膜
代理人弁理士 中 村 純之助
４・１ 図
ｔ２図
’ｉ４’４ 図
才５図
十６図
十８図1, 2, 6, and 4 are cross-sectional views for explaining the first embodiment of the present invention; FIGS. 5, 6, and 7;
FIG. 8, FIG. 9, FIG. 10, and FIG. 11 are sectional views for explaining a second embodiment of the present invention. Explanation of symbols 1...Silicon substrate 2, 3...Silicon oxide film 4...Low resistance polycrystalline silicon layer 5...High resistance polycrystalline silicon layer 6,6'...n+
Type type scattering layer 77'...SiO□ film by CVD method
8 Mountain arsenic ion 9... High melting point metal silicide layer 10... Silicon nitride film Patent attorney Junnosuke Nakamura 4.1 Figure t2 Figure 'i4' 4 Figure 5 Figure 16 Figure 18
Claims (2)
くは金属ソリサイド層からなる２層構造の電極・配線と
、上記下層の、低抵抗多結晶シリコン層と同一層内に形
成される高抵抗多結晶シリコン層からなる高抵抗負荷素
子とを備えだことを特徴とする半導体装置。(1) Two-layer electrode/wiring structure consisting of a low-resistance polycrystalline silicon layer as the lower layer and a metal or metal solicide layer as the upper layer, and a high-resistance layer formed in the same layer as the lower layer of the low-resistance polycrystalline silicon layer. A semiconductor device comprising a high resistance load element made of a polycrystalline silicon layer.
的に不純物拡散を行なって同一層内に高抵抗部と低抵抗
部とを形成する工程と、この多結晶シリコン層上に全面
にわたって金属もしくは金属イリザイド層を形成する工
程と、上記高抵抗部の多結晶ンリコン層上に形成された
上記金属もしくは金属シリサイド層だけを選択的に除去
して上層に金属もしくは金属シリサイド層の無い多結晶
シリコン層から前記高抵抗負荷素子を形成し上層に金属
もしくは金属シリサイド層を持つ多結晶シリコン層から
前記電極・配線を形成する工程とを含んでなる半導体装
置の製造方法。(2) A process of selectively diffusing impurities into a polycrystalline silicon layer deposited on the substrate surface to form a high resistance part and a low resistance part in the same layer, and A process of forming a metal or metal iridide layer, and selectively removing only the metal or metal silicide layer formed on the polycrystalline silicon layer of the high resistance part to form a polycrystalline layer with no metal or metal silicide layer on the upper layer. A method for manufacturing a semiconductor device comprising the steps of forming the high resistance load element from a silicon layer and forming the electrodes and wiring from a polycrystalline silicon layer having a metal or metal silicide layer as an upper layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57221933A JPS59112641A (en) | 1982-12-20 | 1982-12-20 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57221933A JPS59112641A (en) | 1982-12-20 | 1982-12-20 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59112641A true JPS59112641A (en) | 1984-06-29 |
Family
ID=16774430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57221933A Pending JPS59112641A (en) | 1982-12-20 | 1982-12-20 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59112641A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63141349A (en) * | 1986-11-18 | 1988-06-13 | シーメンス、アクチエンゲゼルシヤフト | Integrated semiconductor circuit and manufacture of the same |
| JPS6467942A (en) * | 1987-09-08 | 1989-03-14 | Nec Corp | Formation of resistance circuit of semiconductor device |
| JPH02165666A (en) * | 1988-12-20 | 1990-06-26 | Nec Corp | Manufacture of semiconductor device |
| JPH04237132A (en) * | 1990-07-31 | 1992-08-25 | Internatl Business Mach Corp <Ibm> | Semiconductor structure with polysilicon-land and forming method thereof |
-
1982
- 1982-12-20 JP JP57221933A patent/JPS59112641A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63141349A (en) * | 1986-11-18 | 1988-06-13 | シーメンス、アクチエンゲゼルシヤフト | Integrated semiconductor circuit and manufacture of the same |
| JPS6467942A (en) * | 1987-09-08 | 1989-03-14 | Nec Corp | Formation of resistance circuit of semiconductor device |
| JPH02165666A (en) * | 1988-12-20 | 1990-06-26 | Nec Corp | Manufacture of semiconductor device |
| JPH04237132A (en) * | 1990-07-31 | 1992-08-25 | Internatl Business Mach Corp <Ibm> | Semiconductor structure with polysilicon-land and forming method thereof |
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