JPS60193333A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60193333A JPS60193333A JP4961784A JP4961784A JPS60193333A JP S60193333 A JPS60193333 A JP S60193333A JP 4961784 A JP4961784 A JP 4961784A JP 4961784 A JP4961784 A JP 4961784A JP S60193333 A JPS60193333 A JP S60193333A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- impurity
- heat treatment
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 238000010438 heat treatment Methods 0.000 claims abstract description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000008018 melting Effects 0.000 claims abstract description 6
- 238000002844 melting Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 238000010406 interfacial reaction Methods 0.000 claims description 4
- 150000002736 metal compounds Chemical class 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 abstract description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract description 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 3
- 229910052682 stishovite Inorganic materials 0.000 abstract description 3
- 229910052905 tridymite Inorganic materials 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 12
- 239000003990 capacitor Substances 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910052698 phosphorus Inorganic materials 0.000 description 5
- 239000011574 phosphorus Substances 0.000 description 5
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 206010062717 Increased upper airway secretion Diseases 0.000 description 1
- -1 Mo and W Chemical class 0.000 description 1
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011449 brick Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 208000026435 phlegm Diseases 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000001698 pyrogenic effect Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、金属９合金やそれらの７リサイド等の化合物
からなる膜を含む低抵抗の電極、配線を有する半導体装
置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device having low resistance electrodes and wiring including a film made of a metal 9 alloy or a compound such as a 7 reside thereof.
従来例の構成とその問題点
微細化、高密度化されたＭＯ８集積回路装置では、動作
速度を向上させるため、低抵抗のＭｏ 、 Ｗ等の高融
点金属又はそれらのシリサイド等をゲート電極や配線と
して用いることができる。特にＭＯ５界面における電気
的安定性を維持するために、リン等の不純物を拡散した
ｐｏｌｙ Ｓｉ （多結晶シリコン）膜上に高融点金属
、金属シリサイド等を形成して得た金属−ｐｏｌｙ ｓ
ｉ、高融点金属シリサイド−四ｌｙ Ｓｉという二層の
ゲート電極にすることが一般に行なわれている。ＭＯ８
半導体装置のプロセスにおいては、二層ゲート電極形成
後、必ず高温熱処理工程が入る。特に金属シリサイドを
使うデバイスでは、ゲート自体の抵抗をデバイス特性に
有効な値まで下げるため、約１ｏＯｏ℃の熱処理を必要
とする。しかし、この熱処理によって、ゲート電極とシ
リコン基板間のゲート絶縁膜に著しいリークが生じ、場
合によっては短絡状態になるという欠点が存在した。絶
縁耐圧の劣化を防止するためには、従来二層ゲートの下
層を構成するｐｏｌｙ Ｓｉ膜厚を厚く形成する方法が
とられて米た。例えばＭｏ８１２が２００ｎｍ 、 ｐ
ｏｌｙ Ｓｉがａｏｏｎｍにすれば厚さ３５１１ｍのゲ
ート５ｉ０２膜の耐圧は、１０００ ℃＋ ３０分の熱
処理後も劣化しないようにできる。Conventional configurations and their problems In miniaturized, high-density MO8 integrated circuit devices, low-resistance high-melting-point metals such as Mo and W, or their silicides, etc., are used for gate electrodes and wiring in order to improve operating speed. It can be used as In particular, in order to maintain electrical stability at the MO5 interface, metal-polys is obtained by forming a high melting point metal, metal silicide, etc. on a polySi (polycrystalline silicon) film into which impurities such as phosphorus are diffused.
Generally, the gate electrode is made of two layers: i, high melting point metal silicide-4ly Si. MO8
In the process of semiconductor devices, a high-temperature heat treatment step is always performed after the formation of a two-layer gate electrode. In particular, devices using metal silicide require heat treatment at approximately 100° C. in order to reduce the resistance of the gate itself to a value effective for device characteristics. However, this heat treatment has the disadvantage that significant leakage occurs in the gate insulating film between the gate electrode and the silicon substrate, resulting in a short circuit in some cases. In order to prevent the breakdown voltage from deteriorating, conventional methods have been used to increase the thickness of the polySi film forming the lower layer of the two-layer gate. For example, Mo812 has a thickness of 200 nm, p
If olySi is aoonm, the withstand voltage of the gate 5i02 film with a thickness of 3511 m can be prevented from deteriorating even after heat treatment at 1000° C. for 30 minutes.
しかしなが６．ＭＯＳｉ２ ／ ｐｏｌｙ Ｓｉゲート
において、十分低いシート抵抗を得るためには２００〜
３００ｎｍの厚さのＭｏＳｉ２膜が必要であるから。However, 6. In order to obtain a sufficiently low sheet resistance in a MOSi2/polySi gate, 200~
This is because a MoSi2 film with a thickness of 300 nm is required.
耐圧劣化のない二層ゲートの膜厚は５００〜ｅｏ。The film thickness of the two-layer gate without breakdown voltage deterioration is 500 to eo.
ｎｍになり、従来のｐｏｌｙ Ｓｉゲートの模りより大
きい値となるのである。膜厚が厚い場合、サイドエッチ
等により、二層膜の適用対象となる幅１μｍ〜サブミク
ロンのゲート・配線の精密微細加工性が損なわれ、また
厚い膜厚による段差゛によって。nm, which is a larger value than that of conventional poly-Si gates. If the film is thick, the precision microfabrication of gates and interconnects with a width of 1 μm to submicron, to which the two-layer film is applied, is impaired due to side etching, etc., and also due to the step difference due to the thick film.
二層膜の上層に形成するアルミニウム配線の断線や、そ
の配線を形成するための異方性ドライエツチング不良に
よる配線間のショートが発生する確率が非常に高くなる
。この様な欠点は、集積回路の製造歩留りを大幅に下げ
るものである。There is a very high probability that the aluminum wiring formed on the upper layer of the two-layer film will be disconnected, or that short circuits will occur between the wirings due to defective anisotropic dry etching for forming the wiring. These drawbacks significantly reduce the manufacturing yield of integrated circuits.
発明の目的
本発明は、二層ゲートにおけるｐｏｌｙ Ｓｉ層を薄く
して、ゲート電極の膜厚を減少させ、かつゲート絶縁耐
圧を劣化させない製造方法を提供することによって、上
記従来例の欠点を除去するものである。Purpose of the Invention The present invention eliminates the drawbacks of the conventional example by providing a manufacturing method that reduces the thickness of the gate electrode by thinning the polySi layer in the two-layer gate and does not deteriorate the gate dielectric breakdown voltage. It is something to do.
発明の構成
本発明による二層電極配線の製造方法は、導電型形成不
純物をほとんど含有しな゛いｐｏｌｙ Ｓｉ膜を形成し
た後、その上に導電型形成不純物を含有する金属シリサ
イド、高融点金属等の低抵抗膜を形成して高温で熱処理
を施すことを特徴としている。Structure of the Invention The method for manufacturing a two-layer electrode wiring according to the present invention involves forming a polySi film containing almost no conductivity type forming impurities, and then depositing metal silicide and high melting point metal containing conductivity type forming impurities thereon. It is characterized by forming a low-resistance film such as and subjecting it to heat treatment at a high temperature.
実施例の説明
以下不発ｒｉｌｌの実施例を図面と共に説明する。第１
図は本発明の製造方法を具体的に説明するＭＯＳキャパ
シターの工程断面図である。先ず最初にシリコン基板１
の表面に厚さ３５ ｎｍのゲート酸化膜２をパイロジェ
ニック法を用い９００℃で成長させる（工程ａ）。次に
導電型を形成する不純物を？１とんど含有しないｐｏｌ
ｙ Ｓｉ層３を例えばＬＰＩＣＶＤ法で形成した後、ｃ
ｖｎ法により、リンを１Ｘ １ｏ２０１０Ａ〜３ Ｘ
１０” ７ｃｍの濃度で含有するタングステンシリサイ
ドＷＳｉｚ膜４（！＝２・０〜２．５）を被着する（工
程や）。DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the unexploded rill will be described with reference to the drawings. 1st
The figures are process cross-sectional views of a MOS capacitor specifically explaining the manufacturing method of the present invention. First of all, silicon substrate 1
A gate oxide film 2 with a thickness of 35 nm is grown on the surface of the substrate at 900° C. using a pyrogenic method (step a). Next, what about impurities that form conductivity types? 1 Contains almost no pol
After forming the y Si layer 3 by, for example, the LPICVD method, c
By the vn method, 1X 1o2010A~3X
A tungsten silicide WSiz film 4 (!=2.0 to 2.5) containing a concentration of 10" 7 cm is deposited (step).
この後、ａｃ１４ 、 ｃｃ１４ ＋ｏ２等のガスプラ
ズマで選択的に膜４および３を除去し、２６０μｍｎＸ
２５０／１ｍの寸法をもつゲート電極を形成し、このＷ
Ｓｉ Ｘ膜４の抵抗を下げると同時にリンを四ｌｙ Ｓ
ｉ層３の中へ拡散するために１０００℃、３０分の熱処
理をＮ２等の不活性ガス又はＮ２＋０２等の酸化性ガス
雰囲気中で熱処理する（工程Ｃ）。熱処理したゲート上
Ｆ ＣＶ Ｄ ５ｉｎ２膜５を形成し、９００’Ｃ。After this, films 4 and 3 were selectively removed using gas plasma such as ac14, cc14 + o2, and 260μmnX
A gate electrode with a dimension of 250/1 m is formed, and this W
While lowering the resistance of the Si
In order to diffuse into the i-layer 3, heat treatment is performed at 1000° C. for 30 minutes in an atmosphere of an inert gas such as N2 or an oxidizing gas such as N2+02 (Step C). A FCVD 5in2 film 5 is formed on the heat-treated gate at 900'C.
６０分Ｎ２中で第２の熱処理を施した後、コンタクト窓
を設けてＡ１電極６を形成する（工程ｄ）。After a second heat treatment in N2 for 60 minutes, a contact window is provided to form the A1 electrode 6 (step d).
上記実施例の方法で製造したＭＯＳキャノ（ジターのゲ
ート酸化膜の絶縁耐圧歩留を測定した結果が第２図に示
されている。ｐｏｌｙ Ｓｉ層３の膜早を５０ｎｍに薄
くしても、５ＭＶ／ａｎ以上の耐圧を示すキャパシター
の歩留りは９９チ以上であった。The results of measuring the dielectric breakdown voltage yield of the gate oxide film of the MOS capacitor (Jitter) manufactured by the method of the above embodiment are shown in FIG. The yield of capacitors exhibiting a withstand voltage of 5 MV/an or higher was 99 cm or higher.
これに対し従来のｒＩ＋ｐｏｌｙ Ｓｉ膜を用いた場合
の歩留りは、ｐｏｌｙＳｉの膜厚が１１００ｎ以下にな
ると５０％以下になったから１本方法は大幅なゲート絶
縁膜耐圧歩留改善効果を有する。第１図に示された同一
の工程に従ってＭＯＳキャパ゛シタの製造ｆ：５回行な
い、耐圧を測定したが、すべての場合においてゲート絶
縁膜耐圧歩留りは９５チ以上であった。さらにＷＳｉ
Ｘ膜４の膜厚を１１００ｎからｓｏｏｎｍまで変化させ
ても歩留りの劣化はなく、安定した一定の耐圧が得られ
る。On the other hand, the yield when using the conventional rI+poly Si film was less than 50% when the polySi film thickness was 1100 nm or less, so this method has the effect of significantly improving the gate insulating film breakdown voltage yield. A MOS capacitor was manufactured five times according to the same process shown in FIG. 1, and the breakdown voltage was measured. In all cases, the yield of the gate insulating film breakdown voltage was 95 cm or more. Furthermore, WSi
Even if the thickness of the X film 4 is changed from 1100 nm to soon nm, the yield does not deteriorate, and a stable and constant breakdown voltage can be obtained.
第３図は本発明の第２の実施例であり、ゲート配線とシ
リコン基板との直接コンタクトを有するＭＯ３集積回路
の工程断面図を示すものである。FIG. 3 is a second embodiment of the present invention, and shows a process cross-sectional view of an MO3 integrated circuit having direct contact between a gate wiring and a silicon substrate.
工程ａでは、ｐ型シリコン基板１の一部に素子分離領域
となる厚い５ｉ０２膜７を設け、トランジスタを形成す
べき領域には薄いゲートＳｉＯ２膜２を成長させ、膜２
の下地基板の一部にＮ型拡散層８を設ける。これら工程
を実行した後、拡散層８の表面のゲー） ５ｉ０２膜２
の一部を開口しく開口部９）、導電型を形成する不純物
をほとんど含まないｐｏｌｙ Ｓｉ層３を全面に形成し
、続いてリンを含むＷＳｉｚ膜４を被着する（工程ｂ）
。上記３及び４からなる二層膜をａｃ１４ 、 ｃ ｃ
１４ ＋ ０１２等を用いる異方性エッチで選択的に除
去しゲート電極と配線を形成する。次に９００℃〜１０
００’Ｃの温度範囲で約３０分熱処理し、ＷＳｉｚ膜４
に含有するり’／ ”ｔ Ｉ）Ｏｌｙ Ｓｉ膜３の中へ
拡散してｎ ｐｏｌｙ Ｓｉにすると同時にこの二層膜
の抵抗を下げる。一方配線とｎ型拡散層８との直接コン
タクト窓９の部分では、前記熱処理により、ｐｏｌｙ
Ｓｉ膜３へ拡散層８からのｎ型不純物と、 ＷＳｉｘ膜
４からのリンが同時に拡散して膜３の抵抗、ＷＳｉｚ
−ｐｏｌｙ Ｓｉおよびｐｏｌｙ Ｓニーｎ型拡散層の
コンタクト抵抗を下げ。In step a, a thick 5i02 film 7 is provided on a part of the p-type silicon substrate 1 to serve as an element isolation region, and a thin gate SiO2 film 2 is grown in the region where a transistor is to be formed.
An N-type diffusion layer 8 is provided on a part of the underlying substrate. After performing these steps, the surface of the diffusion layer 8 is coated with 5i02 film 2.
A polySi layer 3 containing almost no impurities forming a conductivity type is formed on the entire surface with an opening 9), and then a WSiz film 4 containing phosphorus is deposited (step b).
. The two-layer film consisting of 3 and 4 above was ac14, cc
The gate electrode and wiring are selectively removed by anisotropic etching using 14 + 012 or the like. Next, 900℃~10
After heat treatment in the temperature range of 00'C for about 30 minutes, the WSiz film 4
It is diffused into the Oly Si film 3 to form n poly Si and at the same time lowers the resistance of this two-layer film. By the heat treatment, the poly
The n-type impurity from the diffusion layer 8 and the phosphorus from the WSix film 4 are simultaneously diffused into the Si film 3, and the resistance of the film 3, WSiz
- Lower contact resistance of poly Si and poly S knee n-type diffusion layers.
この部分にオーミックコンタクトをつくる。次にゲート
電極をマスクとしてＡｓ＋のイオン注入を行ないソース
・ドレイン１ｏを形成する（工程Ｃ）。Make ohmic contact in this part. Next, using the gate electrode as a mask, As+ ions are implanted to form the source/drain 1o (step C).
この後通常の工程によってＣｖＤＳ１０２膜１１の形成
、Ａｌ ／ Ｓｉ電極１２の形成を経て完成するのであ
る。本発明の方法は、第３図の様な直接コンタクトのな
い回路装置やＣＭＯ８集積回路の製造にももちろん適用
できるものである。Thereafter, the CvDS 102 film 11 is formed and the Al/Si electrode 12 is formed through normal steps to complete the process. The method of the present invention can of course be applied to the manufacture of circuit devices without direct contact as shown in FIG. 3 and CMO8 integrated circuits.
本発明の方法はまだ別のデバイスにも適用できる。第４
図は、第３の実施例でありメモリーセル中にｐｏｌｙ
Ｓｉ抵抗負荷を備えたＭＯＳスクチツクＲＡＭの工程断
面図の一部であり、メモリーセル部のみを示している。The method of the invention can also be applied to yet other devices. Fourth
The figure shows the third embodiment, in which poly is used in the memory cell.
This is a part of a process cross-sectional view of a MOS brick RAM equipped with a Si resistive load, and only the memory cell portion is shown.
厚いＳｉ０２膜７．ゲート５ｉ０２膜２を設けたｐ型シ
リコン基板１に、導電型形成不純物−１とんど含″！、
ないｐｏｌｙ Ｓｉ膜３を形成し、この上にリンを含有
するＷＳｉｚ膜４を被着する（工程ａ）。次に３及び４
からなる二層膜を選択的に除去し、ゲート電極と配線を
形成した後、９００’Ｃ〜１０００℃で約３０分間熱処
理する。続いてゲート電極をマスクとしｓＡｓ”５イオ
ン注入してソース・ドレイン１０ｆ、Ｈ形成する（工程
ｂ）。イオン注入の後。Thick Si02 film7. The p-type silicon substrate 1 provided with the gate 5i02 film 2 contains almost all conductivity type forming impurities -1''!
A WSiz film 4 containing phosphorus is deposited thereon (step a). Next 3 and 4
After selectively removing the two-layer film consisting of and forming a gate electrode and wiring, heat treatment is performed at 900'C to 1000C for about 30 minutes. Next, using the gate electrode as a mask, sAs"5 ions are implanted to form the source/drain 10f and H (step b). After the ion implantation.
ＣＶＤ５ｉ０２１３を堆積して再び９００’Ｃ〜１００
０℃の熱処理を施し、ＣＶＤ５ｉＣ）２１３の一部を除
去してコンタクト窓１４を形成し％ １０及び３，４か
ら成る二層配線の一部を露出させる（工程Ｃ）。Deposit CVD5i0213 and heat to 900'C~100C again.
A heat treatment is performed at 0° C. to remove a portion of the CVD5iC) 213 to form a contact window 14 and expose a portion of the two-layer wiring consisting of %10 and 3,4 (Step C).
コンタクト窓１４全含むＣｖＤＳ１０２１３の表面に負
荷抵抗となるｐｏｌｙ Ｓｉ膜１５ ｆ、（Ｌ Ｐ Ｇ
Ｖ Ｄ ヤフラズマＣＶＤ法で堆積し、抵抗パターン
を形成する。この後、９００℃〜１０００℃の熱処理を
行うと、１ｏに含有する人ＳとＷＳＩＸ膜４に含有する
リンが共にｐｏｌｙ Ｓｉ負荷抵抗１５のコンタクト開
口部と重なる部分にのみ拡散し、１６と１０．１５と４
とのコンタクト抵抗を下げることができるのである（工
程ｄ）。工程ｄ以降の製造プロセスは従来のものと同一
である。A poly Si film 15 f, (L P G
V D is deposited by the yahra plasma CVD method to form a resistance pattern. After that, when heat treatment is performed at 900°C to 1000°C, both the S contained in 1o and the phosphorus contained in the WSIX film 4 are diffused only into the portion overlapping with the contact opening of the polySi load resistor 15, and 16 and 10 .15 and 4
This makes it possible to lower the contact resistance with the substrate (step d). The manufacturing process from step d onwards is the same as the conventional one.
上の実施例においては、膜４としてタングステンシリサ
イドＷＳｉｘ ’ｆｒ：用いたが、ＭｏＳｉｘ、 Ｔａ
Ｓｉｘ。In the above example, tungsten silicide WSix'fr: was used as the film 4, but MoSix, Ta
Six.
ＴｉＳｉｘの様な高融点金属シリサイド、Ｍｏ、Ｗ、Ｔ
ａ。Refractory metal silicides such as TiSix, Mo, W, T
a.
Ｔ１等の様な高融点金属や複合膜であっても効果が発揮
される。またこれら材料に含有すべき不純物は、ｐｏｌ
ｙ Ｓｉ ３に拡散して抵抗を下げることができ、ある
場合にはこれと同時に二層膜と、Ｓｉ基板、ｐｏｌｙ
Ｓｉ負荷抵抗とのオーミックコンタクトを形成できる導
電型形成不純物であるならば何でもよ（、Ａｓ、Ｂ、Ｇ
ａ等も可能である。さらにこれら不純物を含む金属膜や
シリサイド膜はｃｖｎ法だけでなくスパッタリング法、
蒸着法も使用することができる。例えばリン金倉むＷＳ
ｉｘ膜は、タングステンシリサイド全ターゲットとして
Ａｒ 中’ｔ：、’ｆ ｐｌ（３を含む雰囲気でスパッ
タリング蒸着すれば１よいのである。Even high-melting-point metals such as T1 and composite films are effective. In addition, the impurities that should be contained in these materials are pol
y can be diffused into Si 3 to lower the resistance, and in some cases, at the same time, the two-layer film, Si substrate, poly
Any conductivity type forming impurity that can form an ohmic contact with the Si load resistor (As, B, G
A etc. are also possible. Furthermore, metal films and silicide films containing these impurities can be prepared not only by CVN method but also by sputtering method.
Vapor deposition methods can also be used. For example, Rin Kanakura WS
The ix film can be deposited by sputtering in an atmosphere containing tungsten silicide as a total target in Ar.
実施し１］においてｐｏｌｙ Ｓｉ膜３は、導電型形成
不純物をほとんど含んでいないが、実験結果では、不純
物濃度が約１×１０／Ｃｄ以下になれば、ゲート酸化膜
の耐圧向上に効果があることが明きらかとなった。熱処
理後のｐｏｌｙ Ｓｉ膜と７リサイドとの界面反応を解
析した結果、ｐｏｌｙ Ｓｉ中の不純物濃度が低下する
と界面反応が平面的に一様となってゲート酸化膜の耐圧
歩留りは１ｏｏ％に近く、上昇すると不均一となって必
ず耐圧の歩留りが低下することがわかった。従って、ｐ
ｏｌｙｓｉ膜３の導電型形成不純物濃度は０に近い必要
はなく、一定値以下の低い値であってもよい。In implementation 1], the poly Si film 3 contains almost no conductivity type forming impurities, but experimental results show that if the impurity concentration is about 1×10/Cd or less, it is effective in improving the breakdown voltage of the gate oxide film. It became clear. As a result of analyzing the interfacial reaction between the poly-Si film and 7-recide after heat treatment, it was found that as the impurity concentration in the poly-Si decreases, the interfacial reaction becomes uniform in a plane, and the breakdown voltage yield of the gate oxide film is close to 10%. It was found that as the voltage increases, it becomes non-uniform and the yield of withstand voltage necessarily decreases. Therefore, p
The conductivity type forming impurity concentration of the olysi film 3 does not need to be close to 0, and may be a low value below a certain value.
発明の効果
以上実施例に説明した様に、本発明による製造方法では
、不純物をほとんど含まない低不純物濃度のｐｏｌｙ
Ｓｉ膜上に不純物を含む金属やその／り丈イドよりなる
導電成金被着した膜を電極にするという簡単な方法によ
って、熱処理によるｐｏｌｙＳｉ膜および導電膜との界
面反応を平面的にほぼ一様に起こし、 ｐｏｌｙ Ｓｉ
膜が薄い場合にも高いゲ−ト酸化膜耐圧が容易に得られ
る。また薄いｐｏｌｙＳｉを用いることによってゲート
電極の段差が軽減できるため、電極自体の微細加工や上
部アルミ配線の加工不良等を防止できる。さらに導電型
形成不純物含有金属・シリサイド膜を用いるのでこの膜
から他の部分へ不純物拡散が可能で、例えばコンタクト
抵抗低減にも寄与する。この様に本発明は、従来の欠点
を除き、半導体装置の歩留り向上、特性向上にその効果
を発揮するものである。Effects of the Invention As explained in the examples above, the manufacturing method according to the present invention can produce poly with a low impurity concentration that contains almost no impurities.
The interfacial reaction between the polySi film and the conductive film caused by heat treatment can be made almost uniform in a plane by using a simple method of using a conductive metal deposited film made of impurity-containing metal or its metallized metal as an electrode on the Si film. Wake up, poly Si
Even when the film is thin, a high gate oxide film breakdown voltage can be easily obtained. Further, by using thin polySi, the step difference in the gate electrode can be reduced, so that fine processing of the electrode itself and processing defects of the upper aluminum wiring can be prevented. Furthermore, since a metal/silicide film containing conductivity type forming impurities is used, impurities can be diffused from this film to other parts, contributing to, for example, a reduction in contact resistance. As described above, the present invention is effective in improving the yield and characteristics of semiconductor devices, while eliminating the conventional drawbacks.
第１図（ａ）〜（ｄ）は本発明の第１の実施例で二層ゲ
ートのＭＯＳキャパシタの製造工程を示す断面図。
第２図は第１図に示した工程及び従来の工程でそれぞれ
製造したＭＯＳキャパシタのゲート５ｉ０２の耐圧歩留
りを示すグラフ、第３図（ＪＬ）〜（ｄ）は本発明の第
２の実施例でゲート配線とシリコン基板との直接コンタ
クトをもつ半導体装置の工程断面図、第４図（＆）〜（
ｄ）は本発明の第３の実施例で、ＭＯＳスタチックＲＡ
Ｍの工程断面図である。
１・・・・・・シリコン基板、２・・・・・・ゲート＋
３ｉ０２膜、３・・・・・・導電型形成不純物をほとん
ど含まないｐｏｌｙＳｉ膜、４°−−−−°ＷＳｉｚ膜
、 ５−− ＣＶ Ｄ ５ｉ０２膜、６・・・・・・Ａ
１電極％７・・・・・・４い５ｉ０２膜、８・・・・・
・Ｎ型拡散層、９・・・・・・コンタクト窓％ １０町
・・ソース・ドＬ／（７，１１−・−・−ｃｖｎｓｉｏ
２膜、１２−９−１９．Ａｌ／Ｓｉｌ／Ｓｉ電極用１３
ＣＶ Ｄ ５ｉ０２膜、１４・・・・・・コンタクト窓
％ １６・・・・・・ｐｏｌｙ Ｓｉ負荷抵抗。
代理人の氏名 弁理士 中 尾 敏 男 はが１名第１
図
？
第２隠Ｉ
Ｐ崎ｓ４．ｔ）＋膿屡 （川
第３図
第４図FIGS. 1(a) to 1(d) are cross-sectional views showing the manufacturing process of a double-layer gate MOS capacitor according to a first embodiment of the present invention. FIG. 2 is a graph showing the breakdown voltage yield of the gate 5i02 of the MOS capacitor manufactured by the process shown in FIG. 1 and the conventional process, and FIGS. Figure 4 (&) - (
d) is a third embodiment of the present invention, in which a MOS static RA
It is a process sectional view of M. 1... Silicon substrate, 2... Gate +
3i02 film, 3...polySi film containing almost no conductivity type forming impurities, 4°----°WSiz film, 5-- CV D 5i02 film, 6...A
1 electrode%7...45i02 film, 8...
・N-type diffusion layer, 9...Contact window% 10...Source de L/(7,11-...-cvnsio
2 membrane, 12-9-19. 13 for Al/Sil/Si electrodes
CV D 5i02 film, 14... Contact window % 16... Poly Si load resistance. Name of agent: Patent attorney Toshio Nakao (1st person)
figure? 2nd Ink I Psaki s4. t) + phlegm (Fig. 3, Fig. 4)
Claims (1)
成する工程と、前記シリコン膜上に少なくとも導電型形
成不純物を含む高融点金属膜又は高融点金属化合物のう
ちの一種類よりなる導電膜を被着する工程と、熱処理す
る工程を有し、前記熱処理による前記シリコン膜及び導
電膜との界面反応を平面的にほぼ一様に起こすことを特
徴とする半導体装置の製造方法。A step of forming a polycrystalline silicon film with a low impurity concentration on a semiconductor substrate, and a conductive film made of one type of a high melting point metal film or a high melting point metal compound containing at least a conductivity type forming impurity on the silicon film. 1. A method for manufacturing a semiconductor device, comprising a step of adhering and a step of heat treatment, and the interfacial reaction between the silicon film and the conductive film caused by the heat treatment occurs almost uniformly in a plane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4961784A JPH0763060B2 (en) | 1984-03-15 | 1984-03-15 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4961784A JPH0763060B2 (en) | 1984-03-15 | 1984-03-15 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60193333A true JPS60193333A (en) | 1985-10-01 |
| JPH0763060B2 JPH0763060B2 (en) | 1995-07-05 |
Family
ID=12836191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4961784A Expired - Lifetime JPH0763060B2 (en) | 1984-03-15 | 1984-03-15 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0763060B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62117368A (en) * | 1985-11-15 | 1987-05-28 | Mitsubishi Electric Corp | Semiconductor device |
| JPH01120863A (en) * | 1987-11-05 | 1989-05-12 | Fujitsu Ltd | Semiconductor storage device |
| JPH01292865A (en) * | 1988-05-20 | 1989-11-27 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0277122A (en) * | 1988-06-16 | 1990-03-16 | Toshiba Corp | Manufacture of semiconductor device |
| US5661081A (en) * | 1994-09-30 | 1997-08-26 | United Microelectronics Corporation | Method of bonding an aluminum wire to an intergrated circuit bond pad |
| US5691235A (en) * | 1994-11-30 | 1997-11-25 | Micron Technology, Inc. | Method of depositing tungsten nitride using a source gas comprising silicon |
-
1984
- 1984-03-15 JP JP4961784A patent/JPH0763060B2/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62117368A (en) * | 1985-11-15 | 1987-05-28 | Mitsubishi Electric Corp | Semiconductor device |
| JPH01120863A (en) * | 1987-11-05 | 1989-05-12 | Fujitsu Ltd | Semiconductor storage device |
| JPH01292865A (en) * | 1988-05-20 | 1989-11-27 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0277122A (en) * | 1988-06-16 | 1990-03-16 | Toshiba Corp | Manufacture of semiconductor device |
| US5661081A (en) * | 1994-09-30 | 1997-08-26 | United Microelectronics Corporation | Method of bonding an aluminum wire to an intergrated circuit bond pad |
| US5734200A (en) * | 1994-09-30 | 1998-03-31 | United Microelectronics Corporation | Polycide bonding pad structure |
| US5691235A (en) * | 1994-11-30 | 1997-11-25 | Micron Technology, Inc. | Method of depositing tungsten nitride using a source gas comprising silicon |
| US6429086B1 (en) | 1994-11-30 | 2002-08-06 | Micron Technology, Inc. | Method of depositing tungsten nitride using a source gas comprising silicon |
| US6472323B1 (en) | 1994-11-30 | 2002-10-29 | Micron Technology, Inc. | Method of depositing tungsten nitride using a source gas comprising silicon |
| US6730954B2 (en) | 1994-11-30 | 2004-05-04 | Micron Technology, Inc. | Method of depositing tungsten nitride using a source gas comprising silicon |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0763060B2 (en) | 1995-07-05 |
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