JPS60160666A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60160666A JPS60160666A JP1510484A JP1510484A JPS60160666A JP S60160666 A JPS60160666 A JP S60160666A JP 1510484 A JP1510484 A JP 1510484A JP 1510484 A JP1510484 A JP 1510484A JP S60160666 A JPS60160666 A JP S60160666A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- film
- etching
- shaped
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000007772 electrode material Substances 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract description 2
- 239000003870 refractory metal Substances 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- PCTMTFRHKVHKIS-BMFZQQSSSA-N (1s,3r,4e,6e,8e,10e,12e,14e,16e,18s,19r,20r,21s,25r,27r,30r,31r,33s,35r,37s,38r)-3-[(2r,3s,4s,5s,6r)-4-amino-3,5-dihydroxy-6-methyloxan-2-yl]oxy-19,25,27,30,31,33,35,37-octahydroxy-18,20,21-trimethyl-23-oxo-22,39-dioxabicyclo[33.3.1]nonatriaconta-4,6,8,10 Chemical compound C1C=C2C[C@@H](OS(O)(=O)=O)CC[C@]2(C)[C@@H]2[C@@H]1[C@@H]1CC[C@H]([C@H](C)CCCC(C)C)[C@@]1(C)CC2.O[C@H]1[C@@H](N)[C@H](O)[C@@H](C)O[C@H]1O[C@H]1/C=C/C=C/C=C/C=C/C=C/C=C/C=C/[C@H](C)[C@@H](O)[C@@H](C)[C@H](C)OC(=O)C[C@H](O)C[C@H](O)CC[C@@H](O)[C@H](O)C[C@H](O)C[C@](O)(C[C@H](O)[C@H]2C(O)=O)O[C@H]2C1 PCTMTFRHKVHKIS-BMFZQQSSSA-N 0.000 description 1
- -1 +Ta-8i +W-8l Chemical compound 0.000 description 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 210000001624 hip Anatomy 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は高集積度で高速化が可能な半導体装置の製造方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a semiconductor device that can be highly integrated and operate at high speed.
半導体回路を高集積化、高速化するために、近年、配線
幅は微細化する傾向にあり、これにともなってゲート酸
化膜の厚ざは薄くなり、また、ゲート電極の材料もポリ
シリコンからより低抵抗のりフラクトリメタＡ／ （ｒ
ｅｆｒａｃｔｏｒｙ ｍｅｔａｌ） シリサイドとポリ
シリコンとの２層構造のいわゆるポリサイド、さらには
低抵抗のりフラクトリーメタルに順次移ってきている。In recent years, in order to increase the integration and speed of semiconductor circuits, the width of interconnections has tended to become smaller.As a result, the thickness of gate oxide films has become thinner, and the material for gate electrodes has also changed from polysilicon to polysilicon. Low resistance glue frac trimeta A/ (r
(efractory metal) There is a gradual shift to so-called polycide, which has a two-layer structure of silicide and polysilicon, and further to low-resistance factory metal.
このようにゲート酸化膜が薄くなると、ゲート電極とソ
ース・ドレインとの間の印加電圧によるゲート酸化膜中
の電界強度が高くなシ、ゲート酸化膜中にわずかの不純
物、結晶欠陥等が存在していても絶縁破壊が起りやすく
なる。When the gate oxide film becomes thinner in this way, the electric field strength in the gate oxide film due to the voltage applied between the gate electrode and the source/drain becomes high, and small amounts of impurities, crystal defects, etc. are present in the gate oxide film. dielectric breakdown is more likely to occur.
また、配線加工法も従来のドライエツチング技術である
と、等方性エツチングのために加工のすそが拡が９回路
の微細化が難しくなるので、垂直方向に加工可能な異方
性エツチング法（以下ＲＩＩＩＣと称す〕が多用されて
きている。しかしながら、ＲＩＥによると加工すべき面
に段差がある場合に段差の壁に存在する被加工物質がエ
ツチング除去されずに残ってしまうという大きな問題が
める。ここで、等方、性エツチング法を併用して、段差
壁の不要被加工物質を除去する必要性が生じる。In addition, if the wiring processing method is conventional dry etching technology, the base of the processing will expand due to isotropic etching, making it difficult to miniaturize the circuit. RIE (hereinafter referred to as RIIIC) has been widely used.However, RIE poses a major problem in that when there is a step on the surface to be processed, the material to be processed on the wall of the step remains without being etched away. Here, it is necessary to use isotropic etching methods in combination to remove unnecessary material from the step wall.
第１図は通常のＭＯ８形半導体メモリの平面図、第２図
はその■−■断面図、第３図は■−■断面図である。Ｐ
形のシリコン基板１にはゲート酸化膜となるＳｉｎｇ膜
２が形成式れ、その上にゲート電極３．メモリ電極４が
形成されている。５は２つのメモリ素子を取り囲むＬＯ
ＧＯ８Ｓｉｎ、膜である。FIG. 1 is a plan view of an ordinary MO8 type semiconductor memory, FIG. 2 is a cross-sectional view taken along the line ■-■, and FIG. 3 is a cross-sectional view taken along the line ■-■. P
A Sing film 2 serving as a gate oxide film is formed on a shaped silicon substrate 1, and a gate electrode 3. A memory electrode 4 is formed. 5 is the LO surrounding the two memory elements
GO8Sin is a film.
なお、シリコン基板１に形成される炉のソース。Note that the source of the furnace is formed on the silicon substrate 1.
ドレイン領域は省略しである。The drain region is omitted.
メモリ素子はメモリ電極４とシリコン基板１の間に形成
されるメモリ領域と、ＭＯＳ ＦＥＴによって構成され
るメモリコントロール領域とからなり、両領域はＡＢＣ
Ｄの領域によって分けられておシ、このＡＢＣＤの領域
は油量、 ８０間で第３図に示すように、ＬＯＣＯ８Ｓ
ｉｎ、膜５上に層間絶縁膜としての８１０．膜６がある
ために大きな段差が存在する。The memory element consists of a memory area formed between the memory electrode 4 and the silicon substrate 1, and a memory control area formed by MOS FETs, and both areas are ABC.
It is divided by the area D, and this area ABCD is the oil amount, as shown in Figure 3, between 80 and LOCO8S.
810.in as an interlayer insulating film on the film 5. Due to the presence of the film 6, a large step exists.
このような構造において、ゲート電極となる物質を第４
図の点線に示すように被着し、配線を形成するためにこ
れを選択的にＲＩＥすると、前記段差部にゲート電極と
なる物質Ｉが第４図に示すように残シ、これが相隣シあ
うゲー］・電極３間を短絡するという問題が生ずる。こ
の問題をなくすためには、ゲート電極を形成する際にあ
る程度等方性エツチングを行ない、段差部に残こる物質
を完全に除去する必要がある。In such a structure, the material that will become the gate electrode is
When it is deposited as shown by the dotted line in the figure and selectively subjected to RIE to form wiring, the material I that will become the gate electrode remains in the stepped portion as shown in FIG. A problem arises in which the electrodes 3 are short-circuited. In order to eliminate this problem, it is necessary to perform isotropic etching to some extent when forming the gate electrode to completely remove the material remaining in the stepped portion.
また、第５図はゲート電極をマスクにソース。Also, Figure 5 shows the source using the gate electrode as a mask.
ドレイン領域を形成する状態の断面図である。シＩＪ）
７Ｊ［１上にＳｉｎ、膜２を介してゲート電極３を形成
する際、レジストマスク８をパターニングした後、等方
性エツチングによりゲート酸化膜３を形成するが、等方
性のために富士山状になりすそを引いた形になる。その
後、Ｎ形不純物のイオン注入を行なってソース、ドレイ
ン領域となる丈領域９を形成する。この際、マスクのな
いＡの範囲ではイオンはＳｉｎ、膜２に損傷を与えなが
らシリコン基板１に打込まれてＮ＋領域９が形成される
φよ、同時にゲート電極３のすその途中点からもイオン
は打込まれＢの範囲にもｓｉｏ、ｌ膜２に損傷を与えな
がら虻領域は形成される。このような構造によると、Ｂ
の範囲でゲート電極３とＮ＋領域９がオーバーラツプし
ていわゆる寄生的なミラー容量バ増加する問題がある。FIG. 3 is a cross-sectional view of a state in which a drain region is formed. SIJ)
7J[When forming the gate electrode 3 through the Sin film 2 on the film 2, after patterning the resist mask 8, the gate oxide film 3 is formed by isotropic etching. It becomes the shape with the hem subtracted. Thereafter, N-type impurity ions are implanted to form height regions 9 that will become source and drain regions. At this time, in the range A where there is no mask, the ions are implanted into the silicon substrate 1 while damaging the Sin film 2, forming the N+ region 9. The ions are implanted and a fly region is formed in the region B, damaging the film 2. According to this structure, B
There is a problem that the gate electrode 3 and the N+ region 9 overlap in the range of .
さらに、ソース・ドレイン間に高電圧を印加した場合、
損傷を受けたＢの範囲のホットキャリアがトラップされ
易くなり、スレシュホールド電圧■ｔｈが変化したす、
ソース。Furthermore, if a high voltage is applied between the source and drain,
The damaged hot carriers in the range B become more likely to be trapped, and the threshold voltage ■th changes.
sauce.
ドレイン耐圧が低下したシする問題がある。このような
問題はゲート酸化膜が薄い程大きくなる。There is a problem that the drain breakdown voltage is lowered. Such problems become more serious as the gate oxide film becomes thinner.
本発明は、このような従来の問題点を解決するためにな
されたものであり、段差部のエツチング残りによる短絡
事故がなく、しかもミラー容量の増加がなく、かつホッ
トキャリア効果による悪影響もないような半導体装置の
製造方法を提供することにある。The present invention has been made to solve these conventional problems, and eliminates short-circuit accidents due to etching residue on the stepped portion, does not increase mirror capacitance, and does not have any adverse effects due to hot carrier effects. An object of the present invention is to provide a method for manufacturing a semiconductor device.
本発明はこのような目的を達成するためになされたもの
であり、等方性エツチングを行なってゲート電極を形成
した後、これをマスクに不純物を注入してソース、ドレ
イン領域となる高濃度不純物領域を形成し、ゲート電極
上のマスクを用いて２−ト電極のすそ部分をＲＩＥによ
シ除去し、さらここの除去した部分に低濃度不純物領域
を形成すｂものである。The present invention has been made to achieve such an object, and after forming a gate electrode by isotropic etching, impurities are implanted using this as a mask to form highly concentrated impurities that will become the source and drain regions. A region is formed, a base portion of the two-tooth electrode is removed by RIE using a mask on the gate electrode, and a low concentration impurity region is formed in the removed portion.
以下、本発明を実施例を用いて詳細に説明する。 Hereinafter, the present invention will be explained in detail using examples.
第６図（、）〜（、）は、本発明に係る半導体装置の製
造方法の一実施例を適用した場合の各工程における断面
図を示す。FIGS. 6(,) to 6(,) show cross-sectional views at each step when an embodiment of the method for manufacturing a semiconductor device according to the present invention is applied.
先づ、Ｐ形のシリコン基板１１にゲートＳｉｎ。First, a gate Sin is formed on a P-type silicon substrate 11.
膜１２を形成した後、この表面に１％、Ｗ、Ｔａ等のり
フラクトリー金属からなるゲート電極用物質１３を形成
し、適当なアニール焼成した後に、この上にさらに薄い
８１ｓＮ、膜１４を形成する。この状態を第６図（、）
に示す。After forming the film 12, a gate electrode material 13 made of a glue factory metal such as 1% W, Ta, etc. is formed on this surface, and after appropriate annealing, a thinner 81sN film 14 is formed thereon. . This state is shown in Figure 6 (,)
Shown below.
次に、ゲート電極形成用のレジスト１５のパターンを形
成する。この状態を第６図（ｂ）に示す。Next, a pattern of resist 15 for forming a gate electrode is formed. This state is shown in FIG. 6(b).
次に、レジスト１５をマスクにして５１８Ｎ４膜１４を
エツチングし、次いでレジスト１５の下に残った５１８
Ｎ、膜１４をマスクにして、例えばＣＦ、の０２プラズ
マ中で等方性エツチングを行ないゲート電（ｉ１３ａを
形成する。等方性エツチングによってゲート電極１３ａ
は５ｉ８Ｎ、膜１４の直下が深くサイドエツチングされ
てすそを有する富士山形に々る。Next, the 518N4 film 14 is etched using the resist 15 as a mask, and then the 518N4 film 14 remaining under the resist 15 is etched.
Using the N, film 14 as a mask, isotropic etching is performed in 02 plasma of CF, for example, to form a gate electrode (i13a).
is 5i8N, and has a Mt. Fuji shape with a deep side etching just below the film 14 and a skirt.
この状態を第６図（Ｃ）に示す。This state is shown in FIG. 6(C).
次に、レジスト１５の下の８１３Ｎ４膜１４のひさし状
になった部分を燐酸中にて処理して除去し、同時にレジ
スト１５も除去する。次いで、Ａ８等Ｎ形の不純物をイ
オン打込みしてソース、ドレイン領域となる高不純物濃
度の１領域１５．１６を形成する。不純物はゲート電極
１３ａのすそ部分の中途点Ｐの範囲まで打込まれる。こ
の状態を第６図（ｄ）に示す。Next, the eave-shaped portion of the 813N4 film 14 under the resist 15 is removed by treatment in phosphoric acid, and the resist 15 is also removed at the same time. Next, N-type impurity ions such as A8 are implanted to form one region 15 and 16 with high impurity concentration that will become the source and drain regions. The impurity is implanted up to the midpoint P of the base of the gate electrode 13a. This state is shown in FIG. 6(d).
次に、シリコン基板をＲＩＥエツチングガス中にさらし
てＳｉ、Ｎ、膜１４下以外のゲート電極１３ａのすそ部
分をエツチング除去する。しかる後、Ｐ等を注入してゲ
ート電極１３ａの直下と虻領域１５゜１６との間に低不
純物濃度のＮ−領域１７．１８を形成する。Next, the silicon substrate is exposed to RIE etching gas to etch away Si, N, and the base portion of the gate electrode 13a except under the film 14. Thereafter, P or the like is implanted to form N- regions 17 and 18 with a low impurity concentration between directly below the gate electrode 13a and the hip regions 15.16.
以上の実施例ではゲート電極としてリフラクトリ−金属
を用いた例で説明したが、次にポリサイドを用いた実施
例について第７図（、）〜（ｃ）により説明する。In the above embodiments, an example in which refractory metal was used as the gate electrode was explained. Next, an embodiment in which polycide was used will be explained with reference to FIGS. 7(a) to 7(c).
シリコン基板１１上に形成した８１０８膜１２の表面に
ポリシリコン層を形成し、さらにその上にＭｏ−８ｉ
＋Ｔａ−８ｉ ＋Ｗ−８ｌ 等のシリサイド）−を形成
した後、第６図の実施例と同様に５１８Ｎ４膜１４゜レ
ジスト１５を形成し、しかる後エツチングを行なう。先
づ、等方性エツチングまた社ＲＩＥによってシリサイド
をエツチングした後、等方性エツチングによってポリシ
リコンをエツチングする。この状態を第７図（−）に示
す。ゲート電極１３ａはポリシリコン部１３ａ□とシリ
サイド部１３ａ、とからなる。A polysilicon layer is formed on the surface of the 8108 film 12 formed on the silicon substrate 11, and Mo-8i is further formed on the polysilicon layer.
After forming a silicide such as +Ta-8i +W-8l, a 518N4 film 14° resist 15 is formed in the same manner as in the embodiment shown in FIG. 6, and then etching is performed. First, the silicide is etched by isotropic etching or RIE, and then the polysilicon is etched by isotropic etching. This state is shown in FIG. 7(-). The gate electrode 13a consists of a polysilicon portion 13a□ and a silicide portion 13a.
次に、５ｉａＮ＋膜１４のひさし部分およびレジスト１
５を除去し、不純物を打込んでＮ＋領域１５゜１６を形
成する。この状態を第７図（ｂ）に示す。Next, the eaves part of the 5iaN+ film 14 and the resist 1
5 is removed and impurities are implanted to form N+ regions 15° and 16. This state is shown in FIG. 7(b).
次に、ＲＩＥによってゲート電極１３ａのポリシリコン
部１３ａ１のすそ部分を除去し、しかる後、ｒ領域１７
．１８を形成する。Next, the base portion of the polysilicon portion 13a1 of the gate electrode 13a is removed by RIE, and then the r region 17
．． form 18.
このように本発明に係る半導体装置の製造方法によると
、等方性エツチングによってゲート電極を形成するので
エツチング残シによる短絡事故がなくなる。また、等方
性エツチングによって生じたゲート電極のすそ部分によ
り虻領域がすその中途の範囲まで形成されるが、ＲＩＥ
によってこのすそ部分を除去し、さらに除去した虻領域
の端にＮ−領域を形成するため、ゲート電極とのオーバ
ーラツプ容量がなくなるとともに、ｒ領域によって？領
域の電界強度が低減されホットキャリア効果による悪影
響が減少するという優れた効果がある。As described above, according to the method of manufacturing a semiconductor device according to the present invention, since the gate electrode is formed by isotropic etching, short-circuit accidents due to etching residues are eliminated. In addition, a gadfly region is formed halfway up the hem by the hem of the gate electrode produced by isotropic etching, but RIE
By removing this base portion, and forming an N- region at the end of the removed dovetail region, the overlap capacitance with the gate electrode is eliminated, and the r-region also eliminates the overlapping capacitance with the gate electrode. This has the excellent effect of reducing the electric field strength in the region and reducing the negative effects caused by hot carrier effects.
第１図は通常のＭＯ８形半導体メモリの平面図、第２図
は第１図の■−■断面図、第３図は第１図の■−■断面
図、第４図はエツチング残りが生ずる状態を説明するた
めの断面図、第５図はゲート電極のすそ部分に不純物が
打込まれる状態を説明するだめの断面図、第６図（、）
〜（、）は本発明に係る半導体装置の製造方法の一実施
例における各工程の断面図、第７図（、）〜（ｃ）は他
の実施例における各工程の断面図である。
１１・・・・シリコン基板、１２・・・・Ｓｉｎ。
膜−１３ａ・・・・ゲート電極、１４・・・・５ｉ８Ｎ
。
膜、１５・・・・レジスト、１５．１６・・・・Ｎ＋領
領域１７．１８・・・・Ｎ−領域。
第１図
第２図
第５図
第６図Figure 1 is a plan view of a normal MO8 type semiconductor memory, Figure 2 is a cross-sectional view taken along ■-■ of Figure 1, Figure 3 is a cross-sectional view taken along ■-■ of Figure 1, and Figure 4 is a diagram showing how etching remains. Figure 5 is a cross-sectional view to explain the state, and Figure 6 is a cross-sectional view to explain the state in which impurities are implanted into the base of the gate electrode.
7(,) are sectional views of each step in one embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIGS. 7(,) to 7(c) are sectional views of each step in another embodiment. 11...Silicon substrate, 12...Sin. Film-13a...Gate electrode, 14...5i8N
. Film, 15...Resist, 15.16...N+ region 17.18...N- region. Figure 1 Figure 2 Figure 5 Figure 6
Claims (1)
にマスクを形成した後、等方性エツチングを行なってゲ
ート電極を形成する工程と、全面に不純物を打込んで半
導体基板の主面に第２導電形の高濃度不純物領域を形成
する工程と、異方性エツチングを行なってマスク下のゲ
ート′電極のみ残しゲート電極の他の部分を除去する工
程と、しかる後に杢糸−を打込んで高濃度不純物領域の
端に低濃度不純物領域を形成する工程とを有する半導体
装置の製造方法。After forming an electrode material on a semiconductor substrate of the first conductivity type and forming a mask on this, isotropic etching is performed to form a gate electrode, and impurity is implanted into the entire surface of the semiconductor substrate. A step of forming a high concentration impurity region of the second conductivity type on the surface, a step of performing anisotropic etching to remove the other part of the gate electrode leaving only the gate electrode under the mask, and then removing the heathered yarn. 1. A method for manufacturing a semiconductor device, comprising the step of implanting a low concentration impurity region at an end of a high concentration impurity region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1510484A JPS60160666A (en) | 1984-02-01 | 1984-02-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1510484A JPS60160666A (en) | 1984-02-01 | 1984-02-01 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60160666A true JPS60160666A (en) | 1985-08-22 |
Family
ID=11879526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1510484A Pending JPS60160666A (en) | 1984-02-01 | 1984-02-01 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60160666A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62224974A (en) * | 1986-03-27 | 1987-10-02 | Toshiba Corp | Manufacture of semiconductor device |
| JP2005129632A (en) * | 2003-10-22 | 2005-05-19 | National Institute Of Advanced Industrial & Technology | Method for manufacturing mosfet semiconductor device |
| JP2009302528A (en) * | 2008-06-11 | 2009-12-24 | Magnachip Semiconductor Ltd | Method for forming triple gate of semiconductor element |
-
1984
- 1984-02-01 JP JP1510484A patent/JPS60160666A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62224974A (en) * | 1986-03-27 | 1987-10-02 | Toshiba Corp | Manufacture of semiconductor device |
| JP2005129632A (en) * | 2003-10-22 | 2005-05-19 | National Institute Of Advanced Industrial & Technology | Method for manufacturing mosfet semiconductor device |
| JP2009302528A (en) * | 2008-06-11 | 2009-12-24 | Magnachip Semiconductor Ltd | Method for forming triple gate of semiconductor element |
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