JPH0377376A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0377376A
JPH0377376A JP21342789A JP21342789A JPH0377376A JP H0377376 A JPH0377376 A JP H0377376A JP 21342789 A JP21342789 A JP 21342789A JP 21342789 A JP21342789 A JP 21342789A JP H0377376 A JPH0377376 A JP H0377376A
Authority
JP
Japan
Prior art keywords
film
polycrystalline silicon
conductor film
side walls
reverse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21342789A
Other languages
Japanese (ja)
Inventor
Hiromichi Ichikawa
宏道 市川
Kiyoshi Irino
清 入野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21342789A priority Critical patent/JPH0377376A/en
Publication of JPH0377376A publication Critical patent/JPH0377376A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To avoid short circuit between conductor film patterns which are so formed as to cross reverse-tapered steps by a method wherein the side walls of the tapered steps are covered with insulating films and a conductor film is built up on them and selectively etched to form the conductor film patterns which cross the thin film pattern and are separated from each other. CONSTITUTION:Side walls 7 composed of polycrystalline silicon films are formed on the ends of a gate electrode 4 to eliminate a reverse-tapered shape, and a thermal treatment is performed in an oxidizing gas atmosphere to oxidize the side walls 7. Apertures are formed in an oxide film 3 on a source diffused layer 6a and a drain diffused layer 6b. A conductor film 8 composed of an Al film or a polycrystalline silicon film is built up over the whole surface and patterned by anisotropic etching with an RIE method to form a source electrode 8a and a drain electrode 8b. As the reverse-tapered region K at the end of the gate electrode 4 is filled with the side walls 7 composed of the polycrystalline silicon films and, further, the polycrystalline silicon films are insulated from the conductor film 8 leakage current between the source electrode 8a and the drain electrode 8b can be eliminated.

Description

【発明の詳細な説明】 〔概 要〕 導電体膜パターンの形成方法に関し、 逆テーパ状の段差と交差して形成された導体膜パターン
の短絡を防止することを目的とし、逆テーパ形状の薄膜
パターンを有する基板上に多結晶シリコン膜を堆積し異
方性エンチングを行って該薄膜パターン端部に該多結晶
シリコン膜からなる側壁を形成する工程と、該側壁の全
部あるいは少なくともその表面を酸化するか、又は該側
壁を絶縁膜で覆う工程と、この上に導電体膜を堆積し選
択的にエツチングすることにより該薄膜パターンと交差
しかつ互いに分離された導電体膜パターンを形成する工
程を含むように構成する。
[Detailed Description of the Invention] [Summary] Regarding a method for forming a conductive film pattern, the purpose of this method is to form a thin film with an inverted tapered shape, with the aim of preventing short circuits in a conductive film pattern formed across steps in an inverted tapered shape. A step of depositing a polycrystalline silicon film on a substrate having a pattern and performing anisotropic etching to form a sidewall made of the polycrystalline silicon film at the edge of the thin film pattern, and oxidizing all or at least the surface of the sidewall. Alternatively, a step of covering the side wall with an insulating film, and a step of depositing a conductive film on this and selectively etching it to form conductive film patterns that intersect with the thin film pattern and are separated from each other. Configure to include.

〔産業上の利用分野] 本発明は半導体装置の製造方法に係り、特に導電体膜パ
ターンの形成方法に関する。
[Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a conductive film pattern.

[従来の技術〕 半導体ICの構成要素であるMOS)ランジスタのソー
171147間リーク電流は通常10− ’ ”A程度
の極めて微小な値とすることが要求される。
[Prior Art] The leakage current between the saws 171 and 147 of a MOS transistor, which is a component of a semiconductor IC, is normally required to be an extremely small value of about 10-''A.

しかし従来、上記リーク電流を安定して微小な値に抑え
そのバラツキを小さくすることは難しく、半導体ICの
特性劣化の原因となっていた。リーク電流の増大は以下
に述べるようにゲート電極パターンの端部形状が逆テー
パ状となっていることにその一因がある。
However, conventionally, it has been difficult to stably suppress the leakage current to a very small value and reduce its variation, which has caused deterioration in the characteristics of semiconductor ICs. One reason for the increase in leakage current is that the end shape of the gate electrode pattern is reversely tapered, as described below.

第3図(a)〜(C)は従来のMOS)ランジスタの工
程断面図、第4図はMO3I−ランジスタの平面図であ
り、第4図中AA’断面図が第3図(C)に対応してい
る。第3図(a)に示すように、まずp型半導体基板1
1上にフィールド酸化膜12で分離された活性領域を形
成しその表面に熱酸化膜13を形成する。
3(a) to 3(C) are process cross-sectional views of a conventional MOS transistor, and FIG. 4 is a plan view of a MO3I-transistor. Compatible. As shown in FIG. 3(a), first, a p-type semiconductor substrate 1
An active region separated by a field oxide film 12 is formed on the active region 1, and a thermal oxide film 13 is formed on the surface thereof.

ついで多結晶シリコン膜を堆積し選択的にエツチングす
ることによりゲート電極14を形成する。このエツチン
グによってゲート電極14の端部形状が図中に示したよ
うに逆テーパ状に整形された場合、ゲート電極14の端
部には逆テーパ領域Kが生じることになる。以上のよう
にしてゲート電極14を形成した後、熱処理してゲート
電極14の表面を酸化膜15で覆う。続いてゲート電極
14をマスクとし熱酸化膜15を通してn型不純物のイ
オン注入を行いソース拡散層16aおよびドレイン拡散
Ji16bを形成する。ついで同図(b)に示すように
ソース拡散層16aおよびドレイン拡散1i 16b上
の熱酸化膜13を窓開けし、全面にAI膜あるいは不純
物のドープされた多結晶シリコン膜からなる導電体膜1
8を堆積するが、この場合には当然のことながら逆テー
パ領域に内も上記導電体膜18で埋め込まれることにな
る。ついで同図(C)に示すように導電体膜18をバタ
ーニングしてソース電極18aおよびドレイン電極18
bを分離・形成する。パターン精度向上のため上記バタ
ーニングは通常反応性イオンエツチング(RI E)法
を用いた異方性エツチングによって行う。そのため、逆
テーパ領域に内に埋め込まれた導電体膜は逆テーパ領域
上部のひさしがマスクとなって除去されずに残る。この
ようにして逆テーパ領域に内に残された導電体膜が第4
図に見られるようにソース電極18a とドレイン電極
18bを導通させ、その結果ソース/ドレイン間のリー
ク電流が増加する。
A gate electrode 14 is then formed by depositing a polycrystalline silicon film and selectively etching it. When the end shape of the gate electrode 14 is shaped into a reverse tapered shape as shown in the figure by this etching, a reverse taper region K is generated at the end of the gate electrode 14. After forming the gate electrode 14 as described above, heat treatment is performed to cover the surface of the gate electrode 14 with an oxide film 15. Next, using the gate electrode 14 as a mask, n-type impurity ions are implanted through the thermal oxide film 15 to form a source diffusion layer 16a and a drain diffusion Ji 16b. Next, as shown in FIG. 6B, the thermal oxide film 13 on the source diffusion layer 16a and the drain diffusion layer 1i 16b is opened, and a conductive film 1 made of an AI film or a polycrystalline silicon film doped with impurities is formed on the entire surface.
8 is deposited, but in this case, as a matter of course, the inside of the reverse tapered region is also filled with the conductive film 18. Next, as shown in FIG. 2C, the conductive film 18 is patterned to form a source electrode 18a and a drain electrode 18
Separate and form b. In order to improve pattern accuracy, the patterning is usually performed by anisotropic etching using reactive ion etching (RIE). Therefore, the conductor film embedded in the reverse taper region remains without being removed, with the eaves above the reverse taper region acting as a mask. In this way, the conductor film left inside the reverse taper region becomes the fourth conductor film.
As seen in the figure, the source electrode 18a and the drain electrode 18b are brought into conduction, resulting in an increase in leakage current between the source and drain.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

以上の工程において、ゲート電極14のバターニングを
RIE法による異方性エツチングによって行えばパター
ン端部は通常は垂直形状となり、逆テーパ形状が生しる
ことは稀である。しかしながら、エツチング途中におけ
るエツチング条件の変動等に起因して僅かに生じる逆テ
ーパ形状を完全に防ぐことは困難であり、特にMOSト
ランジスタのソー171147間リーク電流は、前述し
たように10−” A程度の微小な値であるためわずか
な逆テーパ形状が生じた場合にも上記リーク電流を増加
させる。
In the above process, if the patterning of the gate electrode 14 is performed by anisotropic etching using the RIE method, the end portions of the pattern will normally have a vertical shape, and a reverse tapered shape will rarely occur. However, it is difficult to completely prevent the reverse taper shape that slightly occurs due to variations in etching conditions during etching, and in particular, the leakage current between the saw 171147 of the MOS transistor is about 10-''A as described above. Since this is a very small value, even if a slight reverse taper shape occurs, the leakage current increases.

また、以上述べたような問題はMOS)ランジスタを製
造する場合に限らず、一般に半導体基板上の薄膜パター
ンに交差する導体膜パターンを形成する場合に起こり素
子特性の劣化を招く。
Further, the above-mentioned problems occur not only when manufacturing MOS transistors, but also generally occur when forming a conductor film pattern that intersects a thin film pattern on a semiconductor substrate, leading to deterioration of device characteristics.

そこで本発明は逆テーパ状の段差と交差して形成された
導体膜パターンの短絡を防止することを目的とする。
Therefore, an object of the present invention is to prevent short-circuiting of a conductor film pattern formed to intersect with a reversely tapered step.

[課題を解決するための手段] 上記課題の解決は、逆テーパ形状の薄膜パターンを有す
る基板上に多結晶シリコン膜を堆積し異方性エツチング
を行って該薄膜パターン端部に該多結晶シリコン膜から
なる側壁を形成する工程と、該側壁の全部あるいは少な
くともその表面を酸化するか、又は該側壁を絶縁膜で覆
う工程と、この上に導電体膜を堆積し選択的にエツチン
グすることにより該薄膜パターンと交差しかつ互いに分
離された導電体膜パターンを形成する工程を含むことを
特徴とする半導体装置の製造方法によって達成される。
[Means for Solving the Problems] To solve the above problems, a polycrystalline silicon film is deposited on a substrate having a thin film pattern having an inverted tapered shape, and anisotropic etching is performed to form the polycrystalline silicon film at the edge of the thin film pattern. A step of forming a side wall made of a film, a step of oxidizing all or at least the surface of the side wall, or a step of covering the side wall with an insulating film, and depositing a conductive film on the side wall and selectively etching it. This is achieved by a method for manufacturing a semiconductor device characterized by including the step of forming conductor film patterns that intersect with the thin film pattern and are separated from each other.

[作 用] 本発明では、まず薄膜パターンを有する基板上に段差被
覆性に優れた多結晶シリコン膜を堆積することによって
上記3膜パターンの端部の逆テーパ領域を上記多結晶シ
リコン膜で完全に埋め込む。
[Function] In the present invention, first, a polycrystalline silicon film having excellent step coverage is deposited on a substrate having a thin film pattern, so that the inverted tapered regions at the ends of the three film patterns are completely covered with the polycrystalline silicon film. Embed in.

ついで多結晶シリコン膜を異方性エツチングすることに
よって逆テーパ領域に埋め込まれた多結晶シリコンを薄
膜パターン端部に側壁として残す。
Then, by anisotropically etching the polycrystalline silicon film, the polycrystalline silicon embedded in the reverse taper region is left as a sidewall at the end of the thin film pattern.

以上の工程によって薄膜パターン端部の逆テーパ形状を
完全に解消することができる。次に、以上のようにして
形成した側壁の全部あるいは少なくともその表面を酸化
するか、又は上記側壁を絶縁膜で覆うことによって次の
工程でこの上に堆積された導電体膜と上記多結晶シリコ
ンとを分離・絶縁する。
Through the above steps, the inverse tapered shape of the end portion of the thin film pattern can be completely eliminated. Next, by oxidizing all or at least the surface of the sidewall formed as described above, or covering the sidewall with an insulating film, the conductor film and the polycrystalline silicon deposited thereon in the next step are formed. Separate and insulate.

ついで4体膜を堆積し異方性エツチングによってバター
ニングした場合、薄膜パターン端部の逆テーパ形状が解
消されているため上記薄膜パターン端部の導電体膜は完
全にエンチング除去される。
When a four-layer film is then deposited and buttered by anisotropic etching, the conductor film at the ends of the thin film pattern is completely etched away because the reverse tapered shape at the ends of the thin film pattern has been eliminated.

従って導電体膜パターンがリークを生じることがな(な
る。また、側壁を構成する多結晶シリコンは先の工程で
導電体膜パターンと絶縁されているため、導電体膜パタ
ーンが上記多結晶シリコンを通してリークすることもな
い。
Therefore, the conductor film pattern will not leak (no leakage will occur).Also, since the polycrystalline silicon forming the sidewalls was insulated from the conductor film pattern in the previous process, the conductor film pattern will pass through the polycrystalline silicon. No leaks.

(実施例〕 本発明に係る方法をMO3I−ランジスタの製造工程に
適用した実施例について、第1図の工程断面図を参照し
て説明する。
(Example) An example in which the method according to the present invention is applied to the manufacturing process of an MO3I-transistor will be described with reference to the process cross-sectional view of FIG.

まず同図(a)に示すように、p型半導体基板l上にフ
ィールド酸化膜2で分離された活性領域を形成しその表
面に熱酸化膜3を形成した後、通常のCVD法を用いて
多結晶シリコン膜を堆積しRIE法による異方性エツチ
ングを行いゲート電極4を形成する。上記エツチング途
中のエツチング条件の変動等によりゲート電極4の端部
形状が逆テーパ状に整形された場合には図中に示したよ
うに逆テーパ領域Kが生じる。その後、熱処理してゲー
ト電極4の表面を酸化することにより酸化膜5を形成す
る。続いてゲート電極4をマスクとし熱酸化膜3を通し
てn型不純物、例えばリン(P)のイオン注入を行いソ
ース拡散層6aおよびドレイン拡散層6hを形成する。
First, as shown in FIG. 2(a), an active region separated by a field oxide film 2 is formed on a p-type semiconductor substrate l, and a thermal oxide film 3 is formed on the surface of the active region. A polycrystalline silicon film is deposited and anisotropically etched using the RIE method to form a gate electrode 4. When the end shape of the gate electrode 4 is shaped into a reverse tapered shape due to a change in the etching conditions during the etching, a reverse taper region K is generated as shown in the figure. Thereafter, the surface of the gate electrode 4 is oxidized by heat treatment to form an oxide film 5. Next, using the gate electrode 4 as a mask, ions of an n-type impurity, such as phosphorus (P), are implanted through the thermal oxide film 3 to form a source diffusion layer 6a and a drain diffusion layer 6h.

ついで全面に多結晶シリコン膜8を堆積した後、RIE
法を用いた異方性エツチングを行い同図(b)に示すよ
うに、ゲート電極4の端部に多結晶シリコン膜からなる
側壁7を形成し逆テーパ形状を解消する。続いて酸化性
ガス雰囲気中で熱処理し側壁7を酸化する。この際、側
壁7を構成する多結晶シリコン膜を全て酸化する必要は
なく、その表面を酸化するだけでも後の結果には影響し
ない。あるいは、上記側壁7を酸化することなくその表
面にCVD法を用いて酸化膜を形成してもよい。ついで
同図(C)に示すようにソース拡散Fi6aおよびドレ
イン拡散層6b上の酸化膜3を窓開けし全面にAl膜あ
るいは多結晶シリコン膜からなる導電体膜8を堆積する
。ついで同図(d)に示すように導電体膜8をRIE法
を用いた異方性エツチングによりバターニングしてソー
ス電極8aおよびドレイン電極8bを形成する。第2図
は以上の工程によって形成されたMOSトランジスタの
平面図を示したものであり、同図中AA’断面図が第1
図(d)に対応している。第2図に見られるようにゲー
ト電極4の端部の逆テーパ領域には多結晶シリコン膜か
らなる側壁7で構成され、かつこの多結晶シリコン膜は
先の工程で導電体膜8とは絶縁されているため、ソース
電極8aとドレイン電極8bとの間でリークが生しるこ
とはない。
After depositing a polycrystalline silicon film 8 on the entire surface, RIE
As shown in FIG. 3B, side walls 7 made of polycrystalline silicon film are formed at the ends of the gate electrode 4 to eliminate the reverse tapered shape. Subsequently, the side wall 7 is oxidized by heat treatment in an oxidizing gas atmosphere. At this time, it is not necessary to oxidize the entire polycrystalline silicon film constituting the sidewall 7, and oxidizing only its surface will not affect the subsequent results. Alternatively, an oxide film may be formed on the surface of the side wall 7 by using the CVD method without oxidizing the side wall 7. Then, as shown in FIG. 2C, windows are opened in the oxide film 3 on the source diffusion layer Fi6a and the drain diffusion layer 6b, and a conductive film 8 made of an Al film or a polycrystalline silicon film is deposited on the entire surface. Then, as shown in FIG. 2D, the conductor film 8 is patterned by anisotropic etching using the RIE method to form a source electrode 8a and a drain electrode 8b. FIG. 2 shows a plan view of the MOS transistor formed by the above steps, and the cross-sectional view taken along the line AA' is the first one.
This corresponds to figure (d). As seen in FIG. 2, the reverse tapered region at the end of the gate electrode 4 is composed of a side wall 7 made of a polycrystalline silicon film, and this polycrystalline silicon film was insulated from the conductive film 8 in the previous step. Therefore, no leakage occurs between the source electrode 8a and the drain electrode 8b.

〔発明の効果] 以上のように本発明によれば、逆テーパ状の段差を有す
る薄膜パターンを交差する導体膜パターンを形成した場
合にも、導体膜パターン間でリークが生じることがなく
なるため、半導体装置の信頼性を向上させる上で有益で
ある。
[Effects of the Invention] As described above, according to the present invention, even when a conductive film pattern is formed that intersects a thin film pattern having an inversely tapered step, leakage does not occur between the conductive film patterns. This is useful in improving the reliability of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は本発明の実施例を示す工程断面
図、 第2図は本発明の実施例を示す平面図、第3図(a)〜
(C)は従来例の問題点を示す工程断面図、 第4図は従来例の問題点を示す平面図、である。 図において、 1.11は半導体基板、 2.12はフィールド酸化膜、 3.13は熱酸化膜、 4.14はゲート電極、 5.15は酸化膜、 6a、16aはソース拡散層、 6b、 16bはドレイン拡散層、 7は側壁、 8.18は導電体膜、 8a、 18aはソース電極、 8b、18bはドレイン電極、 である。 彷pw+の辻演4たを示ナエ柔律πめ図従来例の問題点
を示す平面図 第 四
Figures 1 (a) to (d) are process sectional views showing an embodiment of the present invention, Figure 2 is a plan view showing an embodiment of the present invention, and Figures 3 (a) to
(C) is a process sectional view showing the problems of the conventional example, and FIG. 4 is a plan view showing the problems of the conventional example. In the figure, 1.11 is a semiconductor substrate, 2.12 is a field oxide film, 3.13 is a thermal oxide film, 4.14 is a gate electrode, 5.15 is an oxide film, 6a and 16a are source diffusion layers, 6b, 16b is a drain diffusion layer, 7 is a side wall, 8.18 is a conductive film, 8a and 18a are source electrodes, and 8b and 18b are drain electrodes. 4th floor plan showing the problems of the conventional example

Claims (2)

【特許請求の範囲】[Claims] (1)逆テーパ形状の薄膜パターン(4)を有する基板
(1)上に多結晶シリコン膜を堆積し異方性エッチング
を行って該薄膜パターン(5)の端部に該多結晶シリコ
ン膜からなる側壁(7)を形成する工程と、該側壁(7
)の全部あるいは少なくともその表面を酸化する工程と
、この上に導電体膜(8)を堆積し選択的にエッチング
することにより該薄膜パターン(5)と交差しかつ互い
に分離された導電体膜パターン(8a)、(8b)を形
成する工程を含むことを特徴とする半導体装置の製造方
法。
(1) A polycrystalline silicon film is deposited on a substrate (1) having an inversely tapered thin film pattern (4), and anisotropic etching is performed to remove the polycrystalline silicon film from the edge of the thin film pattern (5). a step of forming a side wall (7);
), and depositing a conductive film (8) thereon and selectively etching it to form conductive film patterns that intersect with the thin film pattern (5) and are separated from each other. A method for manufacturing a semiconductor device, comprising the steps of forming (8a) and (8b).
(2)前記多結晶シリコン膜からなる側壁を絶縁膜で覆
う工程を含むことを特徴とする特許請求の範囲第1項記
載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of: (2) covering the sidewall made of the polycrystalline silicon film with an insulating film.
JP21342789A 1989-08-19 1989-08-19 Manufacture of semiconductor device Pending JPH0377376A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21342789A JPH0377376A (en) 1989-08-19 1989-08-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21342789A JPH0377376A (en) 1989-08-19 1989-08-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0377376A true JPH0377376A (en) 1991-04-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP21342789A Pending JPH0377376A (en) 1989-08-19 1989-08-19 Manufacture of semiconductor device

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Country Link
JP (1) JPH0377376A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100290873B1 (en) * 1993-12-09 2001-09-17 김영환 Method for manufacturing thin film transistor
US11211465B2 (en) 2014-03-13 2021-12-28 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device having gate dielectric and inhibitor film over gate dielectric

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100290873B1 (en) * 1993-12-09 2001-09-17 김영환 Method for manufacturing thin film transistor
US11211465B2 (en) 2014-03-13 2021-12-28 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device having gate dielectric and inhibitor film over gate dielectric

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