JPS5989457A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve an insulation between a polycrystalline silicon layer and a metallic electrode, and to prevent a short circuit by forming an oxidation- resisting film to the upper section of polycrystalline silicon, independently oxidizing only a side wall section and thickly forming only the oxide film on the side wall section of the polycrystalline silicon. CONSTITUTION:A high-concentration N type region 2, a P type region 3 as a channel stopper, an N type epitaxial layer 4, an isolation oxide film 5, a high- concentration N type region 6 for extracting a collector and a P type region 7 as a base region are formed on a P type semiconductor substrate 1. A polycrystalline silicon layer 8 as a region for extracting an emitter, an oxide film 9 and a nitride film 10 are formed. The nitride film 10, the oxide film 9 and the silicon 8 are patterned, and an emitter electrode and a collector electrode are formed. An oxide film 11 is formed through oxidation, an emitter region 12 is formed through heat treatment, and the base region 7 is exposed. The film thickness of an upper section and a side section can be controlled because the oxide film 9 and 11 can be formed through separate processes.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method of manufacturing a multi-layered semiconductor device using a self-alignment method using polycrystalline silicon, and in particular, to prevent short circuits, which have been a problem in the past. The present invention relates to a method of manufacturing a semiconductor device suitable for manufacturing.

[Prior art]

Semiconductor devices are being miniaturized in order to obtain high-speed semiconductor devices, and various self-alignment methods that do not require mask alignment have been proposed in order to efficiently miniaturize the devices. For example ■p
, 3Tr1nsBctions on EDvol E
D-27A 8 August 1980, the self-alignment method, as shown in FIG. 1, forms an isolation oxide film 2 on a semiconductor substrate 1, forms a space region 3,
A polycrystalline silicon layer 4 with a high impurity concentration is formed as an emitter region and wiring, and then an oxide film 5 is oxidized or CVD
It is formed by the D method and patterned to form a cross-sectional structure as shown in FIG.

Next, oxidation is performed to oxidize polycrystalline silicon 4 and base region 3 to form oxide films 7 and 8. At this time, since polycrystalline silicon has a high impurity concentration, the oxidation rate is faster than that of the space region 3, and the oxide film 7 is formed thick and the oxide film 8 is formed thin. During this oxidation step, an emitter diffusion layer 6 is formed using polycrystalline silicon as a diffusion source to obtain a cross section as shown in FIG. 2(b). Next, the entire surface is etched to completely remove the oxide film 8 on the base region using the self-alignment method. Next, a high concentration paste layer 9 is formed by ion implantation, and a metal electrode 10 is formed.
is formed, resulting in a cross-sectional structure shown in FIG.

This method is effective for miniaturization because the emitter and base contacts can be formed in self-alignment. Furthermore, since the base contact can be formed near the emitter periphery and the base resistance is reduced, this is an excellent method for obtaining high-speed devices. However, the film thickness d3 of the oxide film insulating between the polycrystalline silicon 4 and the metal electrode 10 is different from the film thickness d1 of the oxide film 7 shown in FIG.
Since the difference between the thickness d2 of the oxide film 8 and the thickness d3 of the oxide film 8 is d3=d, -d2, insulation defects and short circuits are likely to occur. Furthermore, since the distance between the metal electrode 10 and the emitter diffusion layer 6 is the difference between the thin oxide film thickness mentioned earlier and the lateral diffusion length of the diffusion layer 6, very small shorts are likely to occur. A major drawback was that short-circuits between the emitter and base of the transistor were likely to occur.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a semiconductor device using a self-alignment method that can improve the insulation between a diffusion layer, a polycrystalline silicon layer, and a metal electrode, and completely prevent short circuits.

[Summary of the invention]

As mentioned earlier, the cause of short circuits between polycrystalline silicon and metal electrodes is the thin oxide film on the polycrystalline silicon sidewalls, and it is important to form a thick oxide film on the polycrystalline silicon sidewalls. It is solvable. This is it,
In order to form a thick oxide film only on the polycrystalline silicon sidewalls, we have invented a manufacturing method in which an oxidation-resistant film is formed on top of the polycrystalline silicon and only the sidewalls can be oxidized independently.

The process is as follows.

In a semiconductor device using a self-alignment method using polycrystalline silicon, a process of forming an oxide film after growing polycrystalline silicon, a process of forming a nitride film, a process of buttering a nitride film, an oxide film, and polycrystalline silicon, a nitride film This process includes the step of oxidizing the sidewalls of polycrystalline silicon using the mask as a mask.

Further, an oxidation-resistant film can be used to replace the nitride film.

[Embodiments of the invention]

A first embodiment of the present invention will be explained below with reference to FIG.

FIG. 2 shows a process for forming an npn (pnp) transistor according to the present invention.

Selectively high concentration n(p) on p(n) type semiconductor substrate 1
I)(n) forms a shadow region 2 and becomes a channel stopper
A shadow region 3 is formed, an n(p) type epitaxial layer 4 is formed, an isolation oxide film 5 is formed, a high concentration n(p) shadow region 6 for extracting the collector is formed, and a p (
n) forming a type region 7; Although the steps up to the formation of this region 7 are performed using an insulator separation method, they may be formed using other methods such as a junction separation method. Next, the polycrystalline silicon layer 8, which will become the emitter extraction area, is
Approximately 000 people will be formed. In the formation of region 8, n(1
)) type doped polycrystalline silicon layer may be deposited or a cine blunt may be introduced, such as by ion implantation. Next, an oxide film 9 of about 3000 layers is formed on the polycrystalline silicon layer for taking out the emitter. Here, the oxide film 9 may be formed by oxidizing a polycrystalline silicon layer or by a CVD method. As will be described later, this oxide film serves as an insulating film between the emitter and base electrodes.

Next, a nitride film 10 having a thickness of about 500 to 2000 A is formed.

Here, an oxidation-resistant film may be used to replace the nitride film. A cross-sectional view up to this step is shown in FIG. 2(a).

Next, as shown in FIG. 2(b), the nitride film 10. The oxide film 9 and polycrystalline silicon 8 are patterned to form an emitter electrode and a collector electrode.

Next, oxidation is performed. In this oxidation step, since the nitride film 10 is present, only the side surfaces of the polycrystalline silicon layer 8 and the exposed portions of the base region 7 are oxidized, and an oxide film 11 having a thickness of 2,000 to 5,000 can be formed.

By appropriate heat treatment during or after this oxidation process,
Emitter region 12 is formed using polycrystalline silicon as a diffusion source. The cross section at this time is shown in the same figure (C).

Next, using the nitride film 10 as a mask, the silicon oxide film is etched by anisotropic etching such as dry etching.
The base region 7 is exposed. The cross section at this time is shown in the same figure (d
). As shown in the figure, the upper part of the polycrystalline silicon 8 is insulated by an oxide film 9, and the side part is insulated by an oxide film 11. As described above, since the oxide films 9 and 11 can be formed in separate steps, the thickness of the oxide films on the top and sides can be controlled independently.

Next, ions are implanted into the base extraction part to obtain a high concentration p(n).
forming a region 13, removing the nitride film 10 and selectively removing the oxide film to make contact with the polycrystalline silicon layer;
A contact hole 14 is formed and a metal electrode 15 is formed to complete the process. A cross-sectional view after completion is shown in figure (e). As described above, the present invention has the advantage that by adding a simple process, the top and side parts of the oxide film thickness for insulating polycrystalline silicon can be independently controlled, and the film thickness does not become thinner when completed. There is. Therefore, the distance between the polycrystalline silicon layer 8 and the emitter diffusion layer 12 and the metal electrode 15 can be increased independently in the upper and side parts, which has the effect of completely preventing short circuits.

Next, a second embodiment of the present invention will be explained with reference to FIG. FIG. 3 shows the steps for forming an npn (pnp)) transistor according to the present invention.gp(n) type semiconductor substrate 1, n(I) type heavily doped buried layer 2.1)(n) type channel stopper 3, n (1)) type epitaxial layer 4,
The formation of the isolation oxide film 5, the collector extraction n(p) type high concentration layer 6, and the p(n) type base layer 7 is the same as in FIG. Next, an oxide film of about 300 to 1500 layers is formed, and the emitter region is selectively removed. Next, an n(p) type polycrystalline silicon layer 8 is formed by depositing about 2,000 to 4,000 layers of n(p) type polycrystalline silicon, or by introducing a cine blunting material by ion implantation etc. after depositing the polycrystalline silicon. .Next, an oxide film 9 is formed on the top of the polycrystalline silicon layer for 30 minutes.
It is formed by oxidation or deposition by CVD method. Next, the nitride film 10 is formed by about 500 to 2000 people.An oxidation-resistant film may be used as the base of the nitride film. Furthermore, the emitter region 12 can be formed by using the polycrystalline silicon as a diffusion source through the heat treatment during the process up to now. Here, the emitter region 12 may be formed by ion implantation or the like after patterning the oxide film 100. A cross-sectional view up to this step is shown in Figure (a).

Next, in a patterning step to determine the emitter extraction region and the collector extraction region, the nitride film 10, the oxide film 9,
Polycrystalline silicon 8 is selectively removed. Further, the polycrystalline silicon layer is over-formed by about 1,000 to 3,000 times so that the oxide film 9 and the nitride film 10 form an eaves shape. A cross-sectional view at this time is shown in the same figure (b).

Next, oxidation is performed. In this oxidation process, the upper part of the polycrystalline silicon is not oxidized by the nitride film, and only the sides and base region of the polycrystalline silicon layer are oxidized.
About 00 people can form a film 102°101. The cross section at this time is shown in the same figure (C).

Next, the oxide film is etched using anisotropic etching such as dry etching using the nitride film 10 as a mask, and the oxide film 101 is removed. The cross section at this time is shown in FIG. 2(d).

Next, a high concentration pace region 13 is formed by ion implantation, the nitride film 10 is removed, the oxide film is selectively removed to make contact with the polycrystalline silicon, and a metal electrode 15 is formed to complete the process. . A completed cross-sectional view is shown in figure (e). As described above, according to the present invention, the polycrystalline silicon layer 8 and the metal electrode 15 are insulated by the oxide film 9 on the upper part (and the oxide film 102 on the side parts). , 102 can be controlled independently, and since the film thicknesses are not too thin when completed, short circuits can be completely prevented.

Furthermore, since an appropriate distance can be maintained between the emitter diffusion layer 12 and the metal electrode 15 using a mask, there is a thick surface effect in that short circuits can be prevented.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 4 shows the steps for forming an npn(1)11)) transistor according to the invention.

p(n) type semiconductor substrate 1, n(1) type high concentration buried layer 2
, p(n) type channel stopper 3, n(1) type epitaxial layer 4, isolation oxide film 5, collector extraction n(
The formation of the p) type high concentration layer 6 and the I) (n) type base layer 7 is the same as in FIG. Next, an oxide film 100 with a thickness of 300 to 1,500 is formed, and a nitride film 2 of about 500 to 2,000 is formed. Here, an oxidation-resistant film may be used instead of the nitride film. A cross section up to this step is shown in FIG.

Next, the emitter region and the collector extraction region are patterned, and the nitride film 200 and oxide film 100 are selectively removed. Next, an emitter diffusion layer 12 is formed by ion implantation,
A polycrystalline silicon layer 8 of about 2,000 to 4,000 layers is deposited. Here, the emitter region 12 can also be formed by diffusion from polycrystalline silicon. The cross section at this time is (b)
Shown below.

Next, by oxidation or CVD, an oxide film 9 of about 3,000 layers is formed, and a nitride film of about 500 to 2,000 layers is formed. Here, an oxidation-resistant film may be used to replace the nitride film. The cross section at this time is shown in the same figure (C).

Next, a cross section after patterning polycrystalline silicon so as to cover the emitter region and selectively removing nitride film 10, oxide film 9, and polycrystalline silicon 8 is shown in FIG. Next, oxidation is performed. Due to the presence of the nitride films 10 and 200, only the sides of the polycrystalline silicon layer 8 are oxidized and
An oxide film 102 of about 0 A is formed. A cross section at this time is shown in FIG.

Next, the nitride film is removed, the oxide film 100 is removed,
A heavily doped base region 13 is formed by ion implantation, the oxide film at the contact portion is removed to take out the metal electrode from the polycrystalline silicon layer, and a metal electrode 15 is formed to complete the npn) transistor.

This is shown in the same figure (f). As described above, according to the present invention, the polycrystalline silicon 8 and the metal electrode 15 are insulated by the oxide film 9 on the upper part and the oxide film 102 on the side parts, and the oxide films 9 and 102 are formed independently. Since it has the advantage of being controllable, short circuits can be completely prevented.

Next, a fourth embodiment of the present invention will be explained with reference to FIG. FIG. 5 shows the I"L (integrated
1 shows a process for forming an injection logic. Since most of this manufacturing process is the same as in Example 3 described above, only the differences will be described in detail here.

The formation of the p(n) type substrate 1, the n(1) type high-concentration buried layer 2, the epitaxial layer 4, and the isolation oxide film 5 is the same as in the third embodiment. Next, p(n) swelling diffusion layers 70 and 71, which will become the injector and pace regions of I2L, are formed. Next, a cross section after forming an oxide film 100 and a nitride film 200 is shown in FIG. Next, polycrystalline silicon 8, oxide film 9
, a nitride film 101 and a collector diffusion layer 12 are formed and patterned.

Here, patterning is performed so as to cover the space region of the lateral transistor formed by the diffusion layers 70 and 71. The cross section at this time is shown in FIG. Next, a cross section after oxidation is performed to form an oxide film 102 on the sidewalls of the polycrystalline silicon layer is shown in FIG. Next, nitride film 10.200. Oxide film 1
The cross section after removing 0'0 is shown in FIG. 4(d). Next, a high concentration pace region 72 is formed by ion implantation,
Metal electrodes 15 and 16 are formed to complete the process. A cross section at this time is shown in FIG. As above, 12L is also np
n) It can be formed in the same way as a transistor, and short circuits between polycrystalline silicon and metal electrodes can be prevented.

Next, a fifth embodiment of the present invention is shown in FIG. This is the first
This is the case where I''L is formed in Example 1, and is the same as Example 1 except that the oxide film 50 is formed and the injector and base layers 70 and 71 are formed using this as a mask. p (n) type substrate, 2 is n (p) type high concentration buried layer, 4 is n (p) type epitaxial layer, 5 is isolation oxide film, 8 is polycrystalline silicon, 9.11 is oxide film, 15.
16 is a metal electrode, and 72 is a high concentration p(n) type base layer. Similar to the first embodiment, short circuits between the polycrystalline silicon and the metal electrode can be prevented.

Next, a sixth embodiment of the present invention is shown in FIG. This is the second
This is the case where I2L is formed in the embodiment of I) (n) swelling diffusion layer 70 which becomes the injector and base diffusion layer.
．． The second embodiment is the same as the second embodiment except that 71 is formed, and a short circuit between the polycrystalline silicon and the metal electrode can be prevented.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to independently control the oxide film thickness on the top and side parts of the polycrystalline silicon layer, and also to Since it is possible to make the change in film thickness extremely small, there is an effect that a fine semiconductor device can be easily formed by a self-alignment method that does not cause short circuits over a wide range of process conditions.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a manufacturing method according to the prior art, FIG. 2 is a sectional view showing a first embodiment of the present invention, and FIG. 3 is a sectional view showing a second embodiment of the present invention. 4 is a sectional view showing a third embodiment of the invention, FIG. 5 is a sectional view showing a fourth embodiment of the invention, and FIG. 6 is a sectional view showing a fifth embodiment of the invention. FIG. 7 is a sectional view showing a sixth embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Buried layer, 3... Channel stopper, 4... Epitaxial layer, 5, 9, 10
0゜101.102... Oxide film, 6... Diffusion layer for collector extraction, 7, 13... Base diffusion layer, 8...
Polycrystalline silicon, 10,200...Nitride film, 12...
・Emi-vine hanging 2 Fig. (d,) (e) ■ 3 Fig. (fork) (b) 3 n (1) (go) ”fa J Fig. ■ Fig. 4 (d) (e) Fig. 5<b) Y 5 Figure (cl) (e) Figure 6 7 Continuation of figure 1 ■ Applicant Hitachi Microcomputer Engineering Co., Ltd. 1479 Josui Honmachi, Kodaira City

Claims (1)

[Claims] 1. In a semiconductor device using a self-alignment method using polycrystalline silicon, a step of forming an oxide film after growing polycrystalline silicon, a step of forming a nitride film, a nitride film, an oxide film, polycrystalline silicon 1. A method for manufacturing a semiconductor device, comprising the steps of: buttering the polycrystalline silicon; and oxidizing the sidewalls of polycrystalline silicon using a nitride film as a mask. 2. The method of manufacturing a semiconductor device according to claim 1, wherein an oxidation-resistant film is used as a base for the nitride film. 3. In the buttering step described in claim 1, a step of forming a nitride film in a canopy shape, a step of oxidizing the sidewall of polycrystalline silicon using the nitride film as a mask, and a step of removing the oxide film using the nitride film as a mask. 1. A method of manufacturing a semiconductor device, the method comprising the steps of: