JPS5923475B2 - Method for forming electrodes for semiconductor devices - Google Patents

Method for forming electrodes for semiconductor devices

Info

Publication number
JPS5923475B2
JPS5923475B2 JP15245978A JP15245978A JPS5923475B2 JP S5923475 B2 JPS5923475 B2 JP S5923475B2 JP 15245978 A JP15245978 A JP 15245978A JP 15245978 A JP15245978 A JP 15245978A JP S5923475 B2 JPS5923475 B2 JP S5923475B2
Authority
JP
Japan
Prior art keywords
electrode
forming
window
film
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15245978A
Other languages
Japanese (ja)
Other versions
JPS5578532A (en
Inventor
良美 田中
正一 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP15245978A priority Critical patent/JPS5923475B2/en
Publication of JPS5578532A publication Critical patent/JPS5578532A/en
Publication of JPS5923475B2 publication Critical patent/JPS5923475B2/en
Expired legal-status Critical Current

Links

Description

【発明の詳細な説明】 本発明はリフトオフ法による電極形成方法の下で、半導
体基板上を覆う絶縁被膜の上にまで延びる電極を形成す
ることのできる半導体装置用電極の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming an electrode for a semiconductor device, which is capable of forming an electrode extending onto an insulating film covering a semiconductor substrate using an electrode forming method using a lift-off method.

半導体装置、たとえばプレーナ型トランジスタのベース
領域ならびにエミッタ領域に対して電極を形成するにあ
たり、これらの領域上を覆う絶縁被膜に電極形成用窓を
形成するためのマスクとなるホトレジスト膜を窓穿けの
のちもそのまま残存させ、この状態のままで全面に電極
金属膜を形成し、こののち、ホトレジスト膜を除去する
ことによつてこの上に被着された電極金属膜を併せて除
去し、電極形成用窓の内部にのみ電極金属膜を残す所謂
リフトオフ法が知られている。
When forming electrodes on the base region and emitter region of a semiconductor device, for example, a planar transistor, a photoresist film that serves as a mask for forming electrode formation windows is formed in an insulating film covering these regions, and then a window is formed. An electrode metal film is formed on the entire surface in this state, and then, by removing the photoresist film, the electrode metal film deposited on this is also removed, and the electrode metal film is removed. A so-called lift-off method is known in which an electrode metal film is left only inside the window.

第1図a−cは上記のリフトオフ法による電極の形成方
法を説明するための図であり、先ず第1図aで、示すよ
うにコレクタ領域となる1導電形のシリコン基板1の中
へその表面に形成された二酸化シリコン膜2を不純物拡
散のマスクとして用いる周知の選択拡散技術によつてベ
ース領域3ならびにエミッタ領域4を形成する。
FIGS. 1a to 1c are diagrams for explaining the method of forming an electrode by the lift-off method described above. First, as shown in FIG. A base region 3 and an emitter region 4 are formed by a well-known selective diffusion technique using the silicon dioxide film 2 formed on the surface as a mask for impurity diffusion.

ところで、上記の拡散処理が終了したのちのシリコン基
板は全て二酸化シリコン膜によつて覆われるが、トラン
ジスタの形成から明らかなごとく、その厚さは図示する
ようにコレクタ領域上で最も厚く、一方、エミッタ領域
上で最も薄く、ベース領域上ではその中間の厚さとなつ
ている。次いで、二酸化シリコン膜2の上面全域にホト
レジスト膜5を形成し、このホトレジスト膜をマスクと
して二酸化シリコン膜に電極形成用窓を穿設し、このの
ちホトレジスト膜5を残したままでシリコン基板上の全
域に電極金属膜を形成する。第1図bはかかる処理を経
たのちのシリコン基板の状態を示す図であり、図示する
ようにホトレジスト膜5の上部ならびにベース電極形成
用窓6、エミツタ電極形成用窓7の内部には電極金属膜
8が被着されている。このようにして電極金属膜8の被
着がなされたのち、シリコン基板上のホトレジスト膜5
を溶解もしくは焼却によつて除去することによりホトレ
ジスト膜5上の電極金属膜8が同時に除去され、第1図
cで示すようにベース領域3ならびにエミツタ領域4の
上部に穿設した窓の内部にのみ電極金属膜8が形成され
たトランジスタが得られる。以上説明してきた従来の電
極形成方法により形成される電極金属膜は常に二酸化シ
リコン膜の窓の内部にのみ存在するところとなる。
Incidentally, after the above-mentioned diffusion process is completed, the silicon substrate is entirely covered with a silicon dioxide film, but as is clear from the formation of the transistor, the thickness is the thickest on the collector region as shown in the figure; It is thinnest on the emitter region and has an intermediate thickness on the base region. Next, a photoresist film 5 is formed over the entire upper surface of the silicon dioxide film 2, and using this photoresist film as a mask, a window for forming an electrode is formed in the silicon dioxide film. An electrode metal film is formed on the surface. FIG. 1b is a diagram showing the state of the silicon substrate after undergoing such processing, and as shown in the figure, there is electrode metal on the top of the photoresist film 5 and inside the base electrode forming window 6 and the emitter electrode forming window 7. A membrane 8 is applied. After the electrode metal film 8 is deposited in this way, the photoresist film 5 on the silicon substrate is
The electrode metal film 8 on the photoresist film 5 is removed at the same time by melting or incinerating it, and as shown in FIG. A transistor in which only the electrode metal film 8 is formed is obtained. The electrode metal film formed by the conventional electrode forming method described above always exists only inside the window of the silicon dioxide film.

したがつてかかる電極の形成方法は微細でしかも複雑な
パターンを有する電極の形成に好適であり、また、電極
金属膜の選択エツチングが不要となり、電極形成のため
の作業を容易にもする。ところで、プレーナ型半導体装
置においてその耐圧を高める構造として、PN接合を形
成するためにシリコン基板内に作り込まれた拡散領域ヘ
オーミツク接触する電極を、シリコン基板の表面に露呈
するPN接合を覆う二酸化シリコン膜の上面にまで連続
延長させPN接合端部の破壊電圧を実質的に高めた構造
がたとえば特公昭40−15139号公報に記載の発明
によりすでに知られている。
Therefore, this method of forming an electrode is suitable for forming an electrode having a fine and complicated pattern, and also eliminates the need for selective etching of the electrode metal film, making the work for forming the electrode easier. By the way, as a structure for increasing the withstand voltage in a planar semiconductor device, an electrode that contacts a diffusion region formed in a silicon substrate to form a PN junction is made of silicon dioxide that covers the PN junction exposed on the surface of the silicon substrate. A structure in which the breakdown voltage at the end of the PN junction is substantially increased by continuously extending it to the upper surface of the film is already known, for example, from the invention described in Japanese Patent Publication No. 15139/1983.

しかるに、第1図を参照して説明した電極の形成方法で
は、すでに説明したように窓の内部にのみ電極が形成さ
れるため、上記公報に記載のような電極形成を行うこと
ができない。したがつて、かかる電極形成を行うに当つ
て、作業性に富むリフトオフ法を駆使する電極形成方法
にかえて、従来ではたとえば、電極金属膜を全面に形成
したのち、これに選択エツチングを施すことにより電極
形成を行う方法を採用しなければならなかつた。本発明
は以上説明してきた従来の電極の形成方法における問題
点に鑑みてなされたもので、半導体基板上を覆う絶縁被
膜の上面にまで延長する電極をリフトオフ法を駆使して
形成することのできる電極の形成方法を提供するもので
ある。本発明の電極の形成方法の特徴は、たとえばPN
接合を形成する拡散領域が作り込まれるとともに、表面
全域に前記の拡散領域上で薄く他部分で厚い関係を成立
させて絶縁被膜が形成された半導体基板の前記絶縁被膜
上にホトレジスト膜を形成し、さらに、このホトレジス
ト膜に窓を穿ちその内部に、前記拡散領域上を覆う絶縁
被膜の電極形成用窓穿設領域の全てと拡散領域外を覆う
厚い絶縁被膜の一部を露呈させ、次いで、このホトレジ
スト膜に形成された開孔内に露呈する絶縁被膜に対して
、その電極形成用窓穿設領域部の絶縁被膜を完全に除去
し、一方厚い絶縁被膜を完全に除去することのない時間
にわたり食刻処理を施すことにより電極形成用窓を穿設
し、こののち、ホトレジスト膜を残したままの状態で半
導体基板上の全域に電極金属膜を被着し、最後にホトレ
ジスト膜を除去することによりこの上に被着された電極
金属膜を同時に除去するところにある。以下に第2図を
参照して本発明の半導体装置用電極の形成方法について
詳しく説明する。
However, in the electrode formation method described with reference to FIG. 1, the electrode is formed only inside the window, as described above, and therefore the electrode formation as described in the above publication cannot be performed. Therefore, when forming such electrodes, instead of using the lift-off method, which is highly workable, conventional methods have involved, for example, forming an electrode metal film over the entire surface and then selectively etching it. Therefore, a method of forming electrodes had to be adopted. The present invention has been made in view of the problems in the conventional electrode formation methods described above, and it is possible to form an electrode that extends to the upper surface of an insulating film covering a semiconductor substrate by making full use of the lift-off method. A method for forming an electrode is provided. The feature of the electrode forming method of the present invention is, for example, PN
A photoresist film is formed on the insulating film of a semiconductor substrate in which a diffusion region for forming a junction is formed, and an insulating film is formed over the entire surface so that the film is thin on the diffusion region and thick on other parts. Further, a window is bored in this photoresist film to expose the entire electrode forming window bored region of the insulating film covering the diffusion region and a part of the thick insulating film covering the outside of the diffusion region, and then, Regarding the insulating coating exposed in the opening formed in the photoresist film, the insulating coating in the area where the window for electrode formation is formed is completely removed, while the thick insulating coating is not completely removed. A window for forming an electrode is formed by etching over several steps, then an electrode metal film is deposited over the entire area on the semiconductor substrate while leaving the photoresist film, and finally the photoresist film is removed. As a result, the electrode metal film deposited thereon is removed at the same time. The method for forming an electrode for a semiconductor device according to the present invention will be described in detail below with reference to FIG.

第2図において、第1図と同一のものには同一番号を付
している。第2図a−dはプレーナ型トランジスタのベ
ース領域ならびにエミツタ領域に電極を形成し、かつ、
ベース電極をコレクタ領域上を覆う絶縁被膜の上にまで
延長させる電極の形成方法を示す図である。
In FIG. 2, the same parts as in FIG. 1 are given the same numbers. FIGS. 2a to 2d show electrodes formed in the base region and emitter region of a planar transistor, and
FIG. 6 is a diagram illustrating a method of forming an electrode in which the base electrode extends above the insulating coating covering the collector region.

第2図aは一導電型のシリコン基板1の中にPN接合を
形成する反対導電型のベース領域3および一導電型のエ
ミツタ領域4を作り込み、さらにシリコン基板の表面を
覆う絶縁被膜2の上にホトレジスト膜5を形成し、この
ホトレジスト膜5にベース電極形成のための窓9および
エミツタ電極形成のための窓10を形成したのちの状態
を示す。トランジスタの製造はベース領域3、エミツタ
領域4の順番になされるため、ベース領域3、エミツタ
領域4上の絶縁被膜は前述の第1図a、第2図aに示す
ごとく順次薄いものとなる。本発明は、かかる構造を有
効に利用し、リフトオフ法により半導体基板から絶縁被
膜上にも同時に電極を形成することを可能としたもので
ある。したがつて、本発明では窓9の穿設に際しては、
窓9の幅12をベース電極形成用窓穿設領域の幅11よ
り大とし、しかも窓9の内部にシリコン基板1の上部を
覆う絶縁被膜の一部が露呈する関係を成立させることが
大切である。上記の関係を成立させて窓穿けを行つたの
ちホトレジスト膜5をマスクとして絶縁被膜に対してエ
ツチング処理を施す。
In FIG. 2a, a base region 3 of an opposite conductivity type and an emitter region 4 of one conductivity type forming a PN junction are formed in a silicon substrate 1 of one conductivity type, and an insulating coating 2 is further formed to cover the surface of the silicon substrate. The state is shown after a photoresist film 5 is formed on the photoresist film 5, and a window 9 for forming a base electrode and a window 10 for forming an emitter electrode are formed in this photoresist film 5. Since the transistor is manufactured in the order of base region 3 and emitter region 4, the insulating coatings on base region 3 and emitter region 4 become thinner in sequence as shown in FIGS. 1a and 2a described above. The present invention effectively utilizes such a structure and makes it possible to simultaneously form electrodes on an insulating film from a semiconductor substrate by a lift-off method. Therefore, in the present invention, when drilling the window 9,
It is important to make the width 12 of the window 9 larger than the width 11 of the window perforation area for base electrode formation, and to establish a relationship such that a part of the insulating film covering the upper part of the silicon substrate 1 is exposed inside the window 9. be. After establishing the above relationship and drilling the window, the insulating film is etched using the photoresist film 5 as a mask.

このとき、エツチング時間をベース電極形成用窓穿設領
域にある絶縁被膜部分11を確実に除去し、一方、窓9
の中に露呈するシリコン基板1の上部を覆う11よりも
厚い絶縁被膜部分12を完全に除去するには満たない時
間に選定する。第2図bは上記の条件を成立させたエツ
チング処理によつて絶縁被膜をエツチングしたのちの状
態を示す。かかるエツチング処理により窓9内に露呈す
る薄い絶縁被膜部分11と窓10の中に露呈する絶縁被
膜は全て除去され、ベース電極形成用窓6およびエミツ
タ電極形成用窓7が形成されるとともに、ベース電極形
成用窓の外側にはホトレジスト膜5によつて覆われるこ
とのない絶縁被膜12が存在する。なお、この絶縁被膜
12の厚みはエツチング前の厚みより減少している。次
いで、第2図cで示すように表面全域に電極金属膜8を
形成する。
At this time, the etching time is set to ensure that the insulating coating portion 11 in the region where the window for forming the base electrode is formed is removed, while the window 9
The time is selected to be less than completely removing the insulating coating portion 12 which is thicker than the insulating coating portion 11 covering the upper part of the silicon substrate 1 exposed in the silicon substrate 1 . FIG. 2b shows the state after the insulating film has been etched by an etching process that satisfies the above conditions. By this etching process, the thin insulating coating portion 11 exposed in the window 9 and the insulating coating exposed in the window 10 are all removed, and the base electrode forming window 6 and the emitter electrode forming window 7 are formed. An insulating coating 12 that is not covered with the photoresist film 5 exists outside the electrode forming window. Note that the thickness of this insulating film 12 is smaller than the thickness before etching. Next, as shown in FIG. 2c, an electrode metal film 8 is formed over the entire surface.

この電極金属膜8はホトレジスト膜5の存在によりホト
レジスト膜5上とホトレジスト膜5に穿設した窓の内部
とに分断され、しかもベース領域3にオーミツク接触す
る電極金属膜は絶縁被膜12の上にまで連続して形成さ
れる。こののち、ホトレジスト膜を除去することにより
同時にこの上にある電極金属が取り去られ、第2図dで
示す電極形成ずみのトランジスタ基板が得られる。
Due to the presence of the photoresist film 5, this electrode metal film 8 is divided into the top of the photoresist film 5 and the inside of the window formed in the photoresist film 5, and moreover, the electrode metal film in ohmic contact with the base region 3 is on the insulating coating 12. are formed continuously until Thereafter, by removing the photoresist film, the electrode metal on the photoresist film is simultaneously removed, and a transistor substrate with electrodes formed thereon as shown in FIG. 2d is obtained.

このようにして電極形成のなされたトランジスタでは、
図示するようにベース電極がコレクタベースPN接合1
3の端部上を覆う絶縁被膜の上にまでのびており、コレ
クタベース接合端部の破壊電圧を実質的に高めることの
できる構造を有するものとなる。
In a transistor with electrodes formed in this way,
As shown in the figure, the base electrode is collector-base PN junction 1.
3, and has a structure that can substantially increase the breakdown voltage at the collector-base junction end.

以上説明してきたところから明らかなように、本発明の
半導体装置用電極の形成方法は、リフトオフ法を駆使す
る製造条件の下で、電極形成用窓に隣接する絶縁被膜の
上にまで連続させて電極金属膜を形成しうるものであり
、特に高耐圧の半導体装置を形成するにあたり、その作
業性を大幅に高めることができ、半導体装置の製造に大
きく寄与するものである。
As is clear from the above explanation, the method for forming an electrode for a semiconductor device of the present invention is performed under manufacturing conditions that make full use of the lift-off method, in which the electrode is formed continuously onto the insulating film adjacent to the electrode forming window. It is capable of forming an electrode metal film, and can greatly improve workability, especially when forming a high-voltage semiconductor device, and greatly contributes to the manufacture of semiconductor devices.

なお、以上の説明はプレーナ型トランジスタの電極形成
にも絶縁膜上に電極を延長する場合同様に適用可能であ
る。
Note that the above description can be applied to the formation of electrodes of planar transistors as well as to the case where electrodes are extended on an insulating film.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a−eはリフトオフ法を駆使した従来の半導体装
置用電極の形成方法を説明するための図、第2図a−d
は本発明の一実施例にかかる半導体装置用電極の形成方
法を説明するための図である。 1・・・・・・シリコン基板、2,11,12・・・・
・・絶縁被膜、3・・・・・・ベース領域、4・・・・
・・エミツタ領域、5・・・・・・ホトレジスト膜、6
・・・・・・ベース電極形成用窓、7・・・・・・エミ
ツタ電極形成用窓、8・・・・・・電極金属膜、9,1
0・・・・・・ホトレジストに穿設した窓、13・・・
・・・コレクタベースPN接合。
Figures 1 a-e are diagrams for explaining a conventional method of forming electrodes for semiconductor devices using the lift-off method, and Figures 2 a-d
FIG. 3 is a diagram for explaining a method of forming an electrode for a semiconductor device according to an embodiment of the present invention. 1... Silicon substrate, 2, 11, 12...
...Insulating coating, 3...Base region, 4...
...Emitter region, 5...Photoresist film, 6
... Window for forming base electrode, 7 ... Window for forming emitter electrode, 8 ... Electrode metal film, 9, 1
0... Window drilled in photoresist, 13...
...Collector base PN junction.

Claims (1)

【特許請求の範囲】[Claims] 1 ベースおよびコレクタ拡散領域が作り込まれ、さら
に表面全域に前記両拡散領域上で薄く他部分で厚い関係
を成立させて絶縁被膜が形成された半導体基板の前記絶
縁被膜上にホトレジスト膜を形成する工程、同工程で形
成したホトレジスト膜にベース電極およびエミッタ電極
形成用の窓を穿設するとともに、少なくとも前記ベース
電極形成用窓内にベース拡散域上を覆う絶縁被膜の電極
形成用窓穿設領域の全てとコレクタ領域となる半導体基
板上を覆う厚い絶縁被膜の一部を露呈させる工程、前記
ホトレジスト膜に穿設した窓内に露呈する絶縁被膜に対
して、前記電極形成用窓穿設領域のみを完全に除去しう
るエッチング処理を施す工程、同工程を経た半導体基板
上の全域に電極金属膜を被着する工程および半導体基板
上のホトレジスト膜を除去し、同時この上に被着された
電極金属膜を取り去る工程を前記コレクタ領域となる半
導体基板部分を覆う絶縁膜上までのびるベース電極およ
びエミッタ電極形成をなすことを特徴とする半導体装置
用電極の形成方法。
1. Forming a photoresist film on the insulating film of a semiconductor substrate in which a base and a collector diffusion region are formed, and an insulating film is formed over the entire surface such that it is thin on both the diffusion regions and thick on other parts. Step: drilling a window for forming a base electrode and an emitter electrode in the photoresist film formed in the same step, and at least forming a region for forming an electrode forming window in the insulating film covering the base diffusion region within the window for forming the base electrode. and a part of the thick insulating film covering the semiconductor substrate that will become the collector region, and exposing only the area where the window for electrode formation is formed, with respect to the insulating film exposed in the window formed in the photoresist film. A step of applying an etching process that can completely remove the photoresist film, a step of depositing an electrode metal film over the entire area on the semiconductor substrate that has undergone the same process, and a step of removing the photoresist film on the semiconductor substrate and simultaneously removing the electrode metal film deposited on the semiconductor substrate. A method for forming an electrode for a semiconductor device, characterized in that the step of removing the metal film forms a base electrode and an emitter electrode extending onto an insulating film covering a portion of the semiconductor substrate that will become the collector region.
JP15245978A 1978-12-07 1978-12-07 Method for forming electrodes for semiconductor devices Expired JPS5923475B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15245978A JPS5923475B2 (en) 1978-12-07 1978-12-07 Method for forming electrodes for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15245978A JPS5923475B2 (en) 1978-12-07 1978-12-07 Method for forming electrodes for semiconductor devices

Publications (2)

Publication Number Publication Date
JPS5578532A JPS5578532A (en) 1980-06-13
JPS5923475B2 true JPS5923475B2 (en) 1984-06-02

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ID=15540972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15245978A Expired JPS5923475B2 (en) 1978-12-07 1978-12-07 Method for forming electrodes for semiconductor devices

Country Status (1)

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JP (1) JPS5923475B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56107553A (en) * 1980-01-29 1981-08-26 Nec Corp Semiconductor device and preparation thereof
JPS5792862A (en) * 1980-12-01 1982-06-09 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS57102069A (en) * 1980-12-17 1982-06-24 Mitsubishi Electric Corp Semiconductor device
JPS57160126A (en) * 1981-03-27 1982-10-02 Nec Home Electronics Ltd Manufacture of semiconductor device
JPS57176769A (en) * 1981-04-21 1982-10-30 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device and manufacture thereof
JPS58157129A (en) * 1982-03-12 1983-09-19 Matsushita Electronics Corp Manufacture of semiconductor device
KR920004538B1 (en) * 1988-08-11 1992-06-08 삼성전자 주식회사 Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JPS5578532A (en) 1980-06-13

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