JPS6038874B2 - Method for manufacturing insulator gate field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a structure of a self-aligned insulator gate field effect transistor, and more particularly to a method for manufacturing a self-aligned insulator gate field effect transistor structure having a structure that prevents a short-circuit accident between a gate electrode and a source or drain electrode. A method of manufacturing an effect transistor is provided.

A cross-sectional view of a conventional non-self-aligned insulator gate field effect transistor having a conventional metal gate electrode is shown in FIG.

For example, when making an n-channel aluminum gate MOS transistor, first oxidize a p-type silicon wafer 101 as shown in FIG.
02 is formed, a region of the silicon substrate that will become a source 103 and a drain 104 is selectively exposed, and an n-type impurity such as phosphorus is added. Next, the silicon dioxide Si02 film 102 which will become the gate portion 105 is removed, and a silicon dioxide Si02 film 106 is formed as a gate insulating film in order to obtain a desired threshold voltage. At that time, the tops of the source region 103 and drain region 104 are also oxidized;
Normally, the oxidation rate of the phosphorus diffusion portion is fast, so the silicon dioxide S on the source region 103 and drain region 104
The i02 film 1061 is silicon dioxide Si0 in the gate region.
2 film 106. For example, when the silicon dioxide IJ film 106 in the gate region is oxidized in saturated water vapor with a thickness of 1000 Å, the silicon dioxide S on the source region 103 and the drain region 104 is
The thickness of the i02 film 1061 reaches 2500A. Next, in order to attach electrodes to the source region 103 and drain region 104, it is necessary to open a hole in the silicon dioxide Sj02 film 1061, and for this purpose, a photoresist film 107 is formed.
A cross-sectional view of the coating is shown in FIG. 1B. FIG. 1C is a cross-sectional view of a stage in which aluminum was then vapor-deposited by a conventional method and a wiring pattern was formed by a photoresist method. In the step of applying the photoresist film 107, the current ultraviolet exposure apparatus must have an alignment margin of about 2 degrees. Furthermore, the accuracy of the photoresist process when forming the aluminum electrode wiring must be 2 peaks in total, so it is necessary to have a margin of 4 peaks in total. The stray capacitance of can also not be ignored. On the other hand, as shown in FIG. 1 C', which is an enlarged view of the circled area in FIG. The distance L is thick Si
02 film 1 It is thicker than the gate insulating film portion of the reservoir in which 061 is interposed, and therefore short-circuit accidents between the gate electrode 108 and the source or drain are unlikely to occur. On the other hand, in order to reduce this stray capacitance, a technology has been developed in which the position of the gate is self-aligned with the positions of the source and drain. Typical examples include a method of forming a drain region, and a method of using silicon for the gate electrode, which also serves as a mask for thermal diffusion of impurities for forming the source and drain regions. FIG. 2 shows a cross-sectional view showing the process. For example, as shown in FIG. 2A, a p-type silicon wafer 20
After thermally oxidizing 1 and forming a thick silicon dioxide Si02 film 202 on adjacent transistors to prevent leakage current from flowing through the MOS structure between the wiring and the substrate wafer 201, the source, gate, and drain S of the place where it becomes part
The i02 film 202 is removed, the substrate wafer 201 is exposed, and a gate insulating film 203 is formed again to a thickness that allows a desired threshold voltage to be produced. Thereafter, polycrystalline silicon is formed as the gate electrode 204 by a normal vapor phase growth method. Next, using this polycrystalline silicon gate electrode 204 as a mask, the thin silicon dioxide Si02 film 203 is removed to expose the underlying substrate silicon 201 and doped with n-type impurities.
A source region 205 and a drain region 206 are formed. This may be done by a thermal diffusion method, an ion implantation method, or a combination of both. A cross-sectional view at this stage is shown in FIG. 2B.
Thereafter, as shown in FIG.
05. In order to make ohmic contact with the drain region 206, a hole is opened and a metal wiring 208 is formed as shown in FIG. 2C. Since this structure does not require the above-mentioned alignment margin for the photoresist, it has a feature that there is little overlap between the gate electrode 204 and the source region 205 or the drain region 206, and there is little stray capacitance. However,
In this case, the pn junction 205' (or 20
6') and the gate electrode 204
2 is the thickness of the thin gate insulating film 203, so
It is much thinner compared to the case of FIG. 1C'. Therefore, the gate electrode 204, the source region 205, and the drain region 206
There are many short-circuit accidents with the gate insulating film 203, and the gate insulating film 203 cannot be made very thin. An object of the present invention is to provide a manufacturing method that prevents electrical short-circuit accidents between a gate electrode and a source region and a drain region while maintaining the characteristic of a self-aligned insulator gate transistor of low stray capacitance. With the goal.

Although the present invention is self-aligned, it has a structure in which the thickness of the gate insulating film is made non-uniform, and the distance between the gate electrode and the high impurity concentration regions of the source and drain regions is increased.
At the same time as preventing electrical short-circuit accidents between the gate electrode and the source and drain regions, the film thickness of the gate insulating film other than the peripheral area is made thin enough to obtain the desired functional voltage. It is based on the idea that physical characteristics do not change.

Further, in this invention, since the position of the green end of the pn junction in the source or drain region under the partially thickened part of the gate insulating film is at a deeper position than the source/drain electrode part, the pn junction The structure has a gentle impurity concentration gradient at the edge.

In other words, when making a planar type p-n junction, when doping impurities into a semiconductor from the barrier part, diffusion is faster in the lateral direction than in the depth direction.
The impurity concentration gradient becomes steep at the green end of the n-junction. The present invention is characterized in that the green end is located deeper than the semiconductor surface, so that the impurity concentration gradient becomes gentler. Next, an embodiment of the present invention will be described using an example applied to a flat MOS structure.

FIG. 3 shows a cross-sectional view illustrating the process. First, a p-type silicon wafer 301 is prepared as shown in FIG.
Two films 302 are formed. Next, polycrystalline silicon is grown in a vapor phase using a conventional method and selectively removed to form a gate electrode 303. A silicon nitride film Si3N4304 is grown thereon by the usual chemical vapor deposition method, and then the portions that will become the source region, drain region, and gate region are covered with a photoresist film 305. At this time, it is important for implementing the present invention that the hole 306 is raised so as to expose a portion corresponding to the periphery of the gate electrode 303. The final diagram of this stage is shown in FIG. 3B. If the silicon nitride film Si3N4304 is selectively removed in this state, the third
It will look like Figure C. For selective etching of silicon nitride Si3N4304, a photoresist 305 was used here, and was made by a plasma etching method. At this time, the side surfaces of the polycrystalline silicon electrodes are exposed. Next, as shown in FIG. 3D, oxidation is performed in saturated steam at 110,000 ℃ for 2 hours using this silicon nitride Si3N4304 as a mask to form approximately 1 μm of silicon dioxide Sj02307 on the outer regions of the source and drain. . At this time, corresponding to the groove 306 around the gate mentioned earlier, the original gate insulating film 3 of silicon dioxide Si02 is also formed there.
A silicon dioxide film Si02308, which is thicker than Si02308, is formed. Furthermore, at this time, the side surface of the polycrystalline silicon 303 serving as the gate electrode and the silicon nitride film Si3N430
Although the side and top surfaces of 4 are also oxidized, the silicon nitride film Sj3
Since the oxidation rate of N4 is slow, its silicon dioxide Si0
2309 is thin. Next, this silicon dioxide Si023
09 is removed, and the silicon nitride film Si3N4304 is further removed, and an n-type impurity such as phosphorus is diffused to form a source region 310 and a drain region 311. Phosphorus is also diffused into the gate electrode 303 of polycrystalline silicon. to improve conductivity. Thereafter, a silicon dioxide Si02 film 3 1 2 is grown in a vapor phase using a conventional chemical vapor deposition method to form a silicon dioxide film 3 1 2 as shown in FIG. 3E. Next, metal electrodes 313 are attached to the source region 310 and drain region 311 to complete the process as shown in FIG. 3F. According to this structure, a pn junction 310' forming a source region 310 and a drain region 311,
The insulating film is thicker on the green end of 311' on the gate side, and the distance from the gate electrode 303 is longer than in FIG.

Therefore, an electrical short circuit between the gate electrode 303 and the source region 310 or the drain region 311 will not occur. Further, according to this structure, a pn junction 310' forming a source region and a p-pn junction 311' forming a drain region
Since the pn junction green bridge portions on the gate side are in contact with the thick Si02 film 308 around the gate at a depth deeper than the surface of the source region 310 and drain region 311, the pn junction edge portion on the gate side is Since the impurity concentration gradient is gentle and concentration of electric field strength can be avoided,
Since the injection rate of hot carriers into the 02 film 302 can be reduced, the breakdown voltage between the gate and the source and between the gate and the drain can be increased. The above explanation is based on the example of thickening the insulating film under the entire periphery of the gate electrode on the source and drain regions, but it is not necessarily the case that the insulating film is thickened all around, but for example, just thickening the insulating film around the gate in contact with the drain side. It can also be a structure.

Furthermore, it goes without saying that a normal self-aligned MOS may be used instead of the flat MOS structure. The method of the present invention is also applicable to the gate electrode, which is not limited to just a semiconductor, but can also be a metal electrode as long as it is self-aligned.

[Brief explanation of the drawing]

Figures 1A to C and C' are cross-sectional views for explaining the process order for explaining the related technology, and Figures 2A to C and C' are cross-sectional views of conventional self-aligned gate electrodes. FIGS. 3A to 3F are cross-sectional views for explaining a method of manufacturing a transistor having this structure, and FIGS. 3A to 3F are cross-sectional views for sequentially explaining embodiments of the present invention. 101, 201, 301...p-type Si wafer,
102, 202, 307...Field insulating film, (thick Si02 film), 1 03, 205, 3 1 0
．． ...Source area, 104, 206, 311...
...Drain region, 105... Gate section, 10
6,203,302...Gate Si02 film, 106'...
...Thick Si02 on the high concentration layer formed during gate oxidation
Film, 107,305...Photoresist film, 108...
N gate electrode, 204, 303...Si gate electrode, 103', 205', 310'...pn junction forming the source region, 104', 205', 311'...
pn junction forming the drain region, 207, 312...
...Vapor-phase grown Si02 film, 208,313...
...AI electrode, 304... Vapor phase growth Si3N4
Membrane, 306...Groove corresponding to the periphery of the gate, 3
08...Thick Si02 film around the gate, 30
9...Si 4 film 304 oxide film. 2 boxes and 3 pictures

Claims (1)

[Claims] 1. A first silicon nitride film pattern is formed on a polycrystalline silicon pattern serving as a gate electrode provided on a thin gate insulating film on a semiconductor substrate of one conductivity type, and
The first and third silicon nitride film patterns are formed on the semiconductor substrate by a predetermined distance from the silicon nitride film patterns, and heat treatment is performed using these silicon nitride film patterns as masks. between the second silicon nitride film patterns and between the first and third silicon nitride film patterns;
forming an insulating film buried in the semiconductor substrate and thicker than the gate insulating film in a portion of the semiconductor substrate between the silicon nitride film patterns, and then removing the second and third silicon nitride film patterns; Impurities of opposite conductivity type are introduced into the semiconductor substrate from these parts to form a p-type impurity at the bottom of the thick insulating film.
forming source and drain regions respectively terminated by n-junctions.