JPS5911644A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a high density impurity region at the desired position on the circumferential part of an active area by a method wherein impurities are doped at the prescribed position on a semiconductor region by performing a self-alignment method using a mask material pattern as a mask, and a thick oxide film region is formed by performing a selective oxidation. CONSTITUTION:A P type region 13 can be formed on the circumference of the region which will be turned to the active area of a transistor when a thick oxide film 10 is formed at the part which is not covered by a nitride film 102 when an oxidation is performed. A P type base region 4 is formed by removing the nitride film 102. Besides, after an oxide film 11 has been deposited, an emitter region 5 is formed, and metal electrodes 7 and 8 for base and emitter are formed. As the region 13 is formed by performing a self-matching method, no increase is made in transistor area, thereby producing an excellent effect in a high degree. Besides, the impurities on the circumference of the base region 4 can be formed in high density by having the region 13.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, in particular a self-alignment (
This invention relates to a method of obtaining a high concentration impurity region using a self-alignment method.

There is an insulator separation method as a technique for separating semiconductor elements.

As a method for obtaining isolation regions, LOCO8 (Localized Oxidation), which selectively oxidizes /licon, is used.
A method called the on of 5 silicon or isoplanar method is well known. According to this method, the isolation region is covered with a thick oxide film.

The allowance for mask alignment of the element region with respect to the isolation region is no longer necessary, and the area occupied by the element can be reduced.

The walled emitter method is conventionally known as a method for miniaturizing bipolar transistors.

FIG. 1 shows the cross-sectional structure of Umerd Eminota's bipolar transistor/distor manufactured by the selective oxidation method and the conventional method.

An n-type region (11+buried layer) 2 is selectively formed on the surface of a p-type semiconductor substrate 1, and an n-type epitaxial layer 6 is formed. Thereafter, an oxide film 10 is formed by selective oxidation. Thereafter, a base layer (base region) 4 is provided, and 1] a shadow region (emitter region) 5 and a layered region (collector region) 6 are provided. Furthermore, electrodes 7, 8.9 are formed. As in the structure shown in FIG.
Further, a part of the peripheral side surface of the emitter region 5 in contact with the oxide film 10 is called a walled emitter. Although the walled emitter method has the advantage of reducing the area occupied by the device, it has major drawbacks as described below. That is, since the impurity concentration is usually low in the deep part of the base layer 4, the oxide film 10 and the silicon base material (base region 4
) is prone to leakage current, making it difficult to obtain good transistor characteristics. The reasons for this are as follows. The first reason is that in order to define the emitter region, the oxide film 11 on the surface is etched to open a hole, but in order to etch the tip of the bird's beak, the oxide film must be over-etched. Therefore, the interface 1 between the base region 4 and the oxide film 10
The part 2 becomes narrow and tends to exhibit leakage characteristics. The second reason is that the oxide film 10 tends to contain cations such as Na, and therefore a depletion layer is likely to be formed at the interface 120, which tends to exhibit leakage characteristics. As a countermeasure to these problems, it is conceivable to increase the impurity concentration in the peripheral portion of the base region 4. One possible method for this is to use a mask to form a highly concentrated layer, but since mask alignment is required, the area becomes large and the original walled emitter effect is lost. These drawbacks have hitherto made it difficult to put wall emitters into practical use.

The purpose of the present invention is to eliminate the drawbacks of the conventional method and to solve the problem of the self-aligning method (
An object of the present invention is to provide a method for forming a high concentration impurity region in the periphery of an active area using a self-alignment method.

In order to achieve the above object, the present invention employs a process of forming a pattern of a material that serves as a mask for zero-selective oxidation on the surface of a base material on which a semiconductor element is to be formed, and a self-alignment method using the mask material pattern as a mask. A step of doping impurities into a predetermined position of the semiconductor region under the periphery of the mask material pattern; and a step of forming a thick oxide film (field oxide film) region by selective oxidation using the mask material pattern; A high concentration impurity region is formed at a desired location around the periphery. The high concentration impurity region mentioned here is the base layer (intrinsic base region).
This is a region with a higher impurity concentration, and the desirable impurity concentration is 10 cm or more.

By utilizing the present invention, a semiconductor device as shown in FIG. 2, for example, can be formed. So, Figure 2 is npn
) In the case where a transistor is formed, FIG. 5(a) shows a cross-sectional structure, and FIG. 2(b) shows a planar pattern. A high concentration impurity region (p shadow region with high impurity concentration, hereinafter simply referred to as p shadow region) 13 is provided in a portion where the emitter region 5 is in contact with the oxide film 10. Since this region is obtained by a self-alignment method, there is no need to increase the dimensions of the device.

Hereinafter, the present invention will be explained in detail with reference to Examples.

Embodiment 1: FIGS. 6(a) to 6(g) show cross sections of the main steps of a bipolar transistor formed using the present invention. The completed bipolar transistor (NPN) transistor has a structure similar to that shown in Fig. 2, but in order to simplify the drawing and explanation, only the collector portion constructed at the same time in the same process is shown. (In the following embodiments, only the main parts will be explained.)

First, an n region (n buried layer) 2 is formed at a desired location on a p-type semiconductor substrate 1 having a specific resistance of about 10 to 50 Ω·can,
A type 11 epitaxial layer 6 having a resistivity of about 1 Ω·cm is provided. After that, surface oxidation is performed and the
An oxide film 101 of about A is provided, and further 500 to 2000
A silicon nitride film 102 having a thickness of approximately A is formed by, for example, CVD (Ch
chemical vapor deposition)
Formed by law. FIG. 6(a) shows the cross-sectional structure at this stage. Thereafter, when the nitride film is selectively etched and the oxide film is further etched, the result is as shown in FIG. 3(b). Thereafter, as shown in FIG. 2C, a p shadow region 16 is formed using the nitride film as a mask.

In order to form this p shadow region also under the peripheral portion of the oxide film 101, it is preferable to deposit boron glass and diffuse boron from the boron glass into silicon. However, after boron ion implantation, heat treatment may be performed to cause lateral diffusion. Next, as shown in FIG. 3(d), etching is performed using the nitride film as a mask to remove the nitride film 1.
Remove the silicon in the area not covered with 02. Through this step, a p shadow region 1 is formed under the peripheral part of the nitride film 102.
6 remains, but the p of the part not covered with the nitride film 102
Remove shadow areas. In order to form such a shape, it is preferable to use IE (reactive ion etching) for silicon/etching in this step. If the conditions for IL-E are selected appropriately, it is possible to etch silicon using the nitride film 102 as a mask, but in order to perform the main etching more reliably, it is necessary to It is preferable to deposit an oxide film on the film 102. Next, oxidation is performed to form a thick oxide film 10 on the portions not covered with the nitride film, resulting in the result as shown in FIG. 2(e). Through this step, a p shadow region 13 can be formed around the region that will become the active area of the transistor. After that, a normal bipolar transistor manufacturing process is followed. As shown in FIG. 3(f), the nitride film 102 is removed to form a p-type base region 4. To form the base region 4, for example, 1×10~
5×1014c] -2 or so. Further, after depositing an oxide film 11, an emitter region 5 is formed. For example, 1×10 to 1×10 arsenic is added to form the emitter region 5.
It is sufficient to insert approximately 16C111-2. When the metal electrodes 7 and 8 of the base and emitter are formed, the result is as shown in FIG. 3(g).

Note that when a p-shade region for a channel stopper is provided below 1° of the oxide film, the p-shade region for a channel stopper and the p-shade region for a channel stopper are
It is necessary to prevent the shadow areas 16 from touching each other. To avoid this, either a mask is used to form a p shadow region for the channel stopper so that it does not touch the region 16, or a p shadow region for the channel stopper is formed by ion implantation in the step shown in FIG. 6(d).
When forming the shadow region, the distance between the region 16 and the channel stopper in the vertical direction is obtained by using the silicon step.

In addition, according to this embodiment, a p-shadow region is also formed in the periphery of the extraction portion of the collector electrode (not shown);
;, there is no problem with the operation of the transistor.

According to this embodiment, even if a walled emitter structure is used as shown in FIG. 2 or 6(g), leakage current between the collector and emitter can be prevented because the p shadow region 16 is provided. Since the region 16 is formed by a self-alignment method, there is no increase in the area of the transistor, and the effect is very large. Furthermore, since the impurity concentration around the base region 4 can be made high due to the region 16, even with a walled emitter structure, the base resistance does not increase and very excellent characteristics can be obtained.

Embodiment 2: FIGS. 4(a) to 4(1) show cross sections of the main steps of a bipolar transistor similarly formed using the present invention.

The second embodiment is the same as the first embodiment in that the p-type semiconductor substrate 1 is used and the n++-containing layer 2 and the n-type epitaxial layer 6 are formed. Next, in this embodiment, a p+ type region 14 for isolation is formed. The region 14 is obtained by forming an oxide film on the surface of the epitaxial layer B, selectively opening holes in the oxide film, and diffusing boron. After that, the mask for boron diffusion and the oxide film on the top surface are removed, and again the thin oxide film 10 is removed.
1 and the nitride film 102 are formed as shown in FIG. 4(a).

Next, as shown in FIG. 2B, the nitride film 102 is selectively removed, and the oxide film 101 is further etched. next.

P-type doped polysilicon (polysilicon layer) 1
When 03 is deposited, it becomes as shown in the same figure (C). Furthermore, luE
When the polysilicon layer 106 is etched using etching, the result is as shown in FIG. By utilizing the anisotropy of RIE, polysilicon 106 can be left around nitride film 102. Yet, this enoching allows the silicon (base material)
The surface may be slightly etched. Next, heat treatment is performed in a nitrogen atmosphere to diffuse p-type impurities from the polysilicon into the 7 silicon, resulting in a nitride film 1 as shown in Figure (e).
A p shadow region 16 is obtained below the 02 periphery. Next, selective oxidation is performed using the nitride film 102 as a mask, as shown in FIG.
A p shadow region 16 is obtained around the portion that becomes the active area of the transistor. Incidentally, in order to obtain the structure shown in FIG. 10(f), selective oxidation may be performed directly from the step shown in FIG. 10(d). In this case, the p-type impurity is diffused from the polysilicon simultaneously with the oxidation, and the p-shaded region 13 is obtained.

The following steps are the same as in Example 1. That is, nitride film 1
Remove 02.

When the base region (p-type impurity region) 4 is formed, the same figure (g
). For example, to form region 4,
Ion implantation is performed in the range of -20 ions IXIQ cm to 5 x 1014 cm-2. Further, after forming an oxide film 11 on the surface, an emitter region 5 is formed. The region 5 is obtained, for example, by ion implantation of arsenic in a range of 1×10 15 to 1×10 16 cm −2 . Next, by forming the base and emitter electrodes 7 and 8, the result will be as shown in the same figure (l).

The effects of this embodiment are the same as those of the first embodiment.

Embodiment 6: FIGS. 5(a') to 5(h) show cross-sections of the main steps of a bipolar transistor formed using the present invention. Figure ゛(a),
(b) The process at t is the same as in Example 1. In this actual flow example, silicon is then etched as shown in FIG. 3(C). For this etching, K 01-1, which is well known in isoplanar technology, may be used. The appropriate etching depth is about the same thickness as the epitaxial layer 6. The subsequent steps are the same as in Example 2. That is, polysilicon 103 doped with p-type impurities is deposited (FIG. 10(d)), polysilicon is etched using R, IE (FIG. 12(e)), and heat treatment is performed (FIG. 2(f)).
)), selective oxidation is performed ((g) in the same figure), and the base region 4 is
゜An emitter region 5 is formed and electrodes 7 and 8 are provided ((h) in the same figure).

In this embodiment, the high concentration impurity layer (p shadow region) 16 is provided on the tapered sidewall formed by silicon etching, so it is possible to increase the depth of the p shadow region 16. .

Embodiment 4: FIGS. 6(a) to 6(h) are cross-sectional views showing the main steps of a bipolar transistor formed using the present invention. Figure (a), (1
)) The process at t is the same as in Example 2. In this example, an oxide film 104 is then deposited as shown in FIG. The oxide film 104 is formed with a thickness of 1000 nm using the usual CVD method.
It is formed to an appropriate thickness of ~5000A. After that, when a metal film (for example, an aluminum film) 105 is deposited, a step break occurs due to the step of the oxide film 104, as shown in FIG. The thickness of the metal film 105 is a value smaller than the sum of the thickness of the oxide film 101 and the thickness of the nitride film 102 (
For example, about 500 to 2000 A). Next, when the oxide film 104 is etched, the etching progresses from the cut-off portion of the metal film 1050, resulting in a shape as shown in FIG. 4(e). Thereafter, when the metal film 105 is removed, a groove can be formed around the nitride film 102. Furthermore, by doping silicon (epitaxial layer 3) with a p-type impurity from this groove, a p-shade region 15 can be formed under the periphery of the nitride film 1020, as shown in FIG. 3(f). Doping with the ρ-type impurity is performed by boron ion implantation or thermal diffusion.

Next, the oxide film 104 is removed and selective oxidation is performed using the nitride film 102 as a mask. As shown in FIG.
is obtained. The subsequent steps are the same as in Example 1.

A cross-sectional view when the base and emitter electrodes 7 and 8 are formed is shown in FIG. 1 (1).

In this embodiment as well, the p shadow region 16 can be obtained by self-alignment around the active area of the transistor. Therefore,
By increasing the dimensions of the device, the emitter-collector leakage current can be reduced, and the base resistance can also be significantly reduced.

Embodiment 5: FIGS. 7(a) to 7(1) show cross-sections of the main steps of a bibolar transistor also formed using the present invention. ]), (1
)) The steps at t are the same as in Example 1.

In this embodiment, silicon (epitaxial layer 3) is then etched using ItIIu.

■■Also ■■Rero can obtain the shape shown in the same figure (C) by utilizing the anisotropy of E. In this case, in order to more reliably etch only the 7 silicon (epitaxial layer 3), as described in Example 1, an oxide film is deposited on the nitride film 102 at the stage shown in FIG. 7(a). It's good to keep it. The subsequent steps are as follows: Example 4
It is similar to That is, the oxide film 104 is deposited as shown in FIG.
d)), metal film (e.g. aluminum film, thickness 500~
Approximately 5000A. ) 105 is deposited (e) in the same figure,
After etching the oxide film 104 ((f) in the same figure) and removing the metal film 105, thermal diffusion of the p-type impurity is performed ((g) in the same figure), and selective oxidation ((h) in the same figure). Furthermore,
Base area 4. After forming the emitter region 5, electrodes 7 and 8 are provided ((1) in the figure).

The feature of this embodiment is that a large step (approximately 17 zm) is used during vapor deposition of the metal film 105 to facilitate step cutting of the metal film 105. The effect is similar to that of Example 1.

In the above embodiments, npn) has been explained as an example. Below, taking the manufacturing method of Example 2 as an example, I
L (Integrated Injection)
Log+c), 'MO81, transistor (Meta
Examples for L 0xide 5ilicon) transistors) and Schottky diodes will be described. However, it is also possible to use not only the manufacturing method of Example 2 but also the manufacturing methods of other examples described above.

Example 6: FIGS. 8(a) to 8(1) are explanatory diagrams of the main steps in manufacturing IL using the present invention. Note that the element formed in this example has a base contact made with a self-alignment line using oxidation of polysilicon that will serve as the collector electrode (for example, Japanese Patent Application No. 1982-15).
0741).

The steps shown in FIGS. 4(a) to 4(d) are the same as the steps shown in FIGS. 4(a) to 4(d) described in Example 2. however,
- In FIG. 8, the deep p shadow region 14 is omitted.

The planar pattern shown in FIG. 3(d) is shown in FIG. 2(e). Polysilicon 106 remains around the nitride film 102. In this embodiment, this polysilicon 103 is further partially removed. For this purpose, the area indicated by the broken line in FIG. 2(e) is covered with a mask, and the poly-7 silicon is etched with hydrofluoric nitric acid. Polysilicon is highly doped,
Since the etching speed is high, the silicon (epitaxial layer 6) is hardly etched, and only the portions of the polysilicon layer 103 indicated by parallel hatching are removed. For example, photoresist may be used as a mask for this etching. Figure (f) is a cross-sectional view at this stage. Thereafter, when heat treatment is performed, p-type impurities are diffused into the silicon (epitaxial layer 6) as shown in FIG. Furthermore,
If oxidation is performed, a p shadow region 16 is obtained in a portion around the portion that will become the active area of the device, as shown in FIG. 11 (11). After that, the nitride film 102 is removed and the base region 4 and injector region (p shadow region) 15 are formed.
), a nitride film 106 is deposited, and a hole is formed in the collector region ((J) in the same figure). Furthermore, an n-type doped polysilicon layer 107 is deposited, or undoped polysilicon is deposited and doped with n-type impurities. Next, after patterning the polysilicon, oxidation is performed to form an oxide film 1.
08 is formed as shown in the same figure (1ri). Furthermore, the nitride film 106 is etched, the oxide film is etched, holes are formed for the injector and base electrodes, and the metal electrodes 16 are etched.
, 7, the result will be as shown in Figure (1). Note that when opening the collector region (n+ type region 5), a hole is opened inside the dashed line in FIG.
The n+ type region 5 has a wall structure. Still, book 12
The base area of the transistor is
.

The part where the polysilicon layer 103 has been removed (FIG. 8(e)
r) nl) ) emitter (p shadow region 15) and collector (base region 4) of the transistor.
will not short circuit. - A feature of this embodiment is that it is possible to obtain a p-type impurity region in a part of the periphery of the active area of the transistor. In addition, in the 12N- obtained in this example, even though the collector (+14- shadow region 5) has a wall structure, there is no leakage between the collector and emitter due to the self-alignment p shadow region 13. The current can be reduced, and because of the region 13, the base resistance is reduced, and the IL delay time is significantly reduced.

Embodiment 7: FIGS. 9(a) to 9(11) are diagrams illustrating the main steps of another method for creating a p-shadow region in a part of the periphery of the active area, similar to the embodiment 6. The steps up to FIG. 9(a) are the same as the steps up to FIG. 8(a). After that, the nitride film 102 is selectively etched, as shown in FIG.
1)) The same figure (C) is.

This shows the plane pattern at this stage. Same figure (C)
Cover the inside of the broken line indicated by K with a mask and remove the oxide film 10.
When etching No. 1 is performed, an oxide film remains inside the broken line. Figure (d) is a cross-sectional view at this stage. Then p
Depositing the doped polysilicon layer 10.5
The result will be as shown in FIG. 2(e). Next, when the polysilicon is etched using R and IE, polysilicon 103 remains in the areas where the difference between the underlying layers is large, as shown in FIG. 3(r). Next, when heat treatment is performed, p-type impurities are diffused from the polysilicon 106, as shown in FIG. 3(g). As a result, p shadow area 16
is obtained, but this region is not formed inside the broken line in FIG. Next, the oxide film 101 is etched to remove the portion of the oxide film remaining inside the broken line in FIG. The order of removing the oxide film and removing the polysilicon may be reversed.

Next, when oxidation is performed, a p-shade region 16 is obtained in a portion around the active area of the device, as shown in FIG. 4(h).

The subsequent steps are the same as in Example 6.

Embodiment 8: FIGS. 10(a) to 10(h) are explanatory views of the main steps in manufacturing a MOS transistor using the present invention. A p-type well region 18 is formed at a desired location on an n-type semiconductor substrate 17, and an oxide film 101 and a nitride film 1 are formed on the surface.
If 02 is provided, the result will be as shown in FIG. 10(a). After that, the process from (b) to (f) in the figure is 1. The steps in FIGS. 4(b) to 4(f)t described in Example 2 are the same. That is, the nitride film is patterned, the oxide film is etched (FIG. 10(b)), and polysilicon 103 doped with p-type impurities is deposited (FIG. 10(C)).
Etching the polysilicon using a nitride film 1
The polysilicon is left in the vicinity of 02 (Figure (d)), and the p-type impurity is diffused into the silicon by heat treatment to form the p-shaded region 13.
After oxidation, a 1]-shaped region 13 is provided around the round part of the transistor (see figure (2)).The subsequent process is to form a normal MOS transistor. This depends on the manufacturing process. That is, the nitride film 102 is removed, the oxide film 101 is removed, and a new gate oxide film 109 is formed using oxygen (
Polysilicon is formed by oxidation in an atmosphere of 200 yen (O2), and then polysilicon is deposited and patterned to form a polysilicon film.
-107 is provided ((g) in the same figure). Furthermore, the oxide film in the portions that will become the source and drain is etched and doped with n-type impurities to form n-shaded regions (source and drain regions) 20. Next, the oxide film 110 is formed by CVD.
After depositing the metal electrodes, the north and drain electrode extraction portions are opened and metal electrodes 19 are provided, resulting in a structure as shown in FIG. 1 (1).

According to this embodiment, the p shadow region 13 is obtained in the peripheral portion of the transistor by self-alignment. This p shadow region becomes a channel stonopa. Conventional channel stoppers are formed using a mask, so they have to occupy a large area. However, according to this embodiment, since the channel stoppers are provided in self-alignment, the entire device including the channel stoppers can be area can be significantly reduced.

Embodiment 9: FIGS. 11(a) to 11(1) are explanatory views of the main steps in manufacturing a Schottky diode using the present invention. Figure 11(a) The process in the trench is Example 2
The steps up to FIG. 4(f) described above are the same. After that, the nitride film 102. The oxide film 101 is removed to provide a metal electrode (for example, an A7 electrode) 21 that will serve as an anode.

In this embodiment, a p shadow region 13 can be formed around the Schottky diode. This region serves as a guard ring for the Yotsky diode, and is effective in stabilizing the diode characteristics and reducing reverse saturation current. The guard ring becomes essential because the ratio of the peripheral length to the area of the diode increases with the miniaturization of elements. In this embodiment, since the guard ring is obtained by self-alignment, the area of the diode including the guard ring can be significantly reduced.

In each of the embodiments of the present invention described above, in order to simplify the explanation, the conductivity type of the base semiconductor layer is defined and explained for convenience, but the present invention is also applicable when the conductivity type is reversed. Of course, as described above, according to the present invention, a high concentration impurity region can be formed at a desired location around the active area of a semiconductor element by a self-alignment method. This region 1d is the collector of the bipolar transistor.
It has effects such as reducing leakage current between emitters, acting as a channel stopper for MOS transistors, and guard ring for diodes. As elements become finer, the ratio of the periphery to the area of the element increases, and the influence of the periphery on the characteristics of the element increases. In the present invention, since the impurity region formed in the peripheral portion can be formed by self-alignment, the dimensions of the device including the peripheral portion can be significantly reduced. For example, if the active area is 10μm x 10μ
When forming a high concentration region of 1 μm around an element of m,
In the conventional case where mask alignment is required, the length of one side is 14 μm, whereas in the present invention, it is 12 μm.

Therefore, in addition to the area reduction of 20 to 30%, no additional mask is required when forming a high concentration region around the entire periphery of the element. However, it is very effective economically or industrially.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a walled emitter transistor manufactured by a conventional method, and FIG. 2 is a cross-sectional view of an NPN transistor manufactured by the present invention.
) is a plan view. Figures 6(a) to (g), Figure 4(
a) to (+1), Fig. 5(a) to (h). FIGS. 6(a) to 6(h) and FIGS. 7(a) to 7(i) are explanatory diagrams of main steps in manufacturing a bipolar transistor using the present invention. Figure 8(a)-(
1) is an explanatory diagram of the main steps when manufacturing an IL using the present invention, and FIGS. 9(a) to (h) are explanatory diagrams of the main steps of a method for creating a p-shade region in a part of the periphery of the active area. ,
10(a) to (11) are MOS devices using the present invention)
FIGS. 11(a) to 11(b) are explanatory views of the main steps in manufacturing a transistor. FIGS. 1... N-type semiconductor substrate 2...] Region (n+buried layer) 6°°/N-type epitaxial layer 4... Base layer (base region) 5°°°n Shadow region (emitter of np0 transistor (Collector area of IL) 6...Shadow area (NPN) Collector of transistor) 7.8.9...Electrode 10...Oxide film (field oxide film) 11...Oxide film 12...・Interface 16 between base region and field oxide film
...High concentration impurity layer (p shadow region) 14...■)+shadow region 15...injector region (p shadow region) 16...electrode (injector electrode) 17...n type semiconductor substrate 18. ...p-type well region 19...electrode 20...n shadow region (source, drain region) 21.
...Metal electrode 101...Oxide film 102...Nitride film 103...Polysilicon (polysilicon layer) 104...
...Oxide film 105...Metal film 106...
Nitride film 107... Polysilicon layer 108...
...Oxide film 109...Gate oxide film 110
...Oxide Film Agent Patent Attorney Junnosuke Nakamura Book 1 Figure 2 (Q) Class 3 i +3 Figure 4 Figure 3 Figure 4 Figure 5 Figure 5''l#P6 Figure 1F6 Figure 7 Closed' IP7 figure z Volume 7 figure 1'8 figure 1P8 figure (d) (e) (f) 1'F8 figure (i) ?8 figure 594 O9 figure (C) 1---------------------- --'' 4p9 Figure O'' 0 Figure (Q) (d) Figure 10 Figure 11 (Q) (b) 195- Hitachi, Ltd. Central Research Laboratory, 280 Higashi Koigakubo-chome, Kokubunji City

Claims (4)

[Claims] (1) A process of forming a selective oxidation mask material on the surface of a semiconductor substrate, a patterning process of the mask material, and a self-alignment method using the mask material pattern formed by the patterning as a mask. A step of doping an impurity at a predetermined position of the semiconductor region under the periphery of the material pattern to form a high concentration impurity region, a step of forming a thick oxide film region by selective oxidation using the mask pattern, and a step of forming a thick oxide film region by selective oxidation using the mask pattern; A method for manufacturing a semiconductor device, comprising the steps of: forming a semiconductor element having a film region. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor element is an NPNL-transistor. (3) The method for manufacturing a semiconductor device according to claim 1, when the semiconductor element is a pnp transistor. (4) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor element is an IL.