KR950000137B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR950000137B1
KR950000137B1 KR1019870010068A KR870010068A KR950000137B1 KR 950000137 B1 KR950000137 B1 KR 950000137B1 KR 1019870010068 A KR1019870010068 A KR 1019870010068A KR 870010068 A KR870010068 A KR 870010068A KR 950000137 B1 KR950000137 B1 KR 950000137B1
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layer
film
type
silicon dioxide
polysilicon
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KR1019870010068A
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KR890005883A (en
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고장만
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삼성전자 주식회사
김광호
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors

Abstract

The method includes of the steps of depositing a poly-Si film (8') and a 1st SiO2 film (9) on the Si substrate to form a resist pattern (14) etching the exposed film (8') to remove the pattern (14) to diffuse the p type semiconductor material included in the film (8') into the epi layer (3) to form a base contact region (5), depositing and etching a SiN film (11) and a 2nd SiO2 film (12), implanting p impurities into the n type epitaxial layer (3) to form a active base region (6) to deposit a poly-Si layer (10') thereon to form a resist pattern thereon to etch the layer (10'), and removing the resist pattern to diffuse n impurities through the layer (10') to form an emitter region (7).

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

제 1 도는 제 1 도는 종래의 셀프얼라인드 트랜지스터의 단면도.1 is a cross-sectional view of a conventional self-aligned transistor.

제 2 도는 본 발명의 트랜지스터의 단면도.2 is a cross-sectional view of a transistor of the present invention.

제 3 도는 본 발명의 트랜지스터의 제조공정도.3 is a manufacturing process diagram of the transistor of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : p형 Si기판 2 : n형 메몰층1: p-type Si substrate 2: n-type buried layer

3 : n형 에피택셜층 4 : 전계확산층3: n-type epitaxial layer 4: electric field diffusion layer

5 : p+형 베이스접촉영역 6 : p형 활성베이스영역5: p + type base contact area 6: p type active base area

7 : n+에미터영역 8 : p형 전극7: n + emitter region 8: p-type electrode

9, 12 : 이산화실리콘막 10 : 에미터전극9, 12 silicon dioxide film 10 emitter electrode

11 : 질화 실리콘막 13 : 열산화층11: silicon nitride film 13: thermal oxide layer

본 발명은 바이폴라 반도체장치에 관한 것으로, 특기 자기정합(self- aligned)된 베이스전극, 베이스접촉영역, 활성베이스영역 및 에미터영역을 갖는 반도체 장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar semiconductor device, and more particularly to a method of manufacturing a semiconductor device having a self-aligned base electrode, a base contact region, an active base region, and an emitter region.

제 1 도는 종래의 이소플래너(Isoplanar)형 셀프 얼라인드 트랜지스터의 단면도를 나타낸 것이다. 상기 트랜지스터는 에미터-베이스접합(J)의 주변부가 폴리실리콘으로 된 베이스전극(8)으로부터 에미터전극(10)을 분리시키는 열산화층(13)의 에지에서 끝난다. 이때 열산화층(13)은 다공성이고 표면상태가 화학적으로 증착시킨 산화층이므로, 이 열산화층(13)은 질화실리콘막의 표면상태와 비교하면 불안정하여 에미터와 베이스사이에 항복전압이 감소하고, 누설전류가 발생하며, 또한 장치의 회수율과 신뢰성이 저하되는 문제점이 있었다.1 is a cross-sectional view of a conventional isoplanar type self-aligned transistor. The transistor ends at the edge of the thermal oxidation layer 13 separating the emitter electrode 10 from the base electrode 8 of which the periphery of the emitter-base junction J is made of polysilicon. At this time, since the thermal oxidation layer 13 is porous and the surface state is chemically deposited oxide layer, the thermal oxidation layer 13 is unstable compared with the surface state of the silicon nitride film, so that the breakdown voltage between the emitter and the base decreases, and the leakage current Occurred, and there was also a problem that the recovery rate and reliability of the device is lowered.

본 발명은 상기한 문제점을 해결하기 위해 안출된 것으로, 에미터-베이스접합(J)부위를 질화실리콘막(11)과 이산화산화막(12)으로 피복하여 성능이 안정되고 생산회수율이 높으며, 불순물 확산을 얕게 하여 동작속도가 빠른 반도체장치의 제조방법을 제고하는데 그 목적이 있다.The present invention has been made to solve the above problems, by coating the emitter-base junction (J) with the silicon nitride film 11 and the dioxide dioxide film 12, the performance is stable, production recovery rate is high, impurity diffusion The purpose of the present invention is to improve the manufacturing method of a semiconductor device with a high operating speed by making the angle shallow.

이하에 첨부된 도면에 의하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제 2 도는 본 발명의 의해 제조된 트랜지스터의 단면도를 나타낸 것으로, 제조공정도가 도시된 제 3 도를 참조하여 상세히 설명한다. 먼저 p형 실리콘기판(1)상에 n+형 메몰층(2)과 n형 에피택셜층(3) 및 전계산화층(4)을 확산 및 에피택셜 성장기술을 사용하여 제 1 도(a)와 같이 순차적으로 형성하는데, 이때 메몰층(2)은 전계산화층(4)과 pn접합에 의해 인접한 층과 분리된다(도면에는 나타나 있지 않음).2 is a cross-sectional view of a transistor manufactured by the present invention, which will be described in detail with reference to FIG. First, the n + type buried layer 2, the n-type epitaxial layer 3, and the electro-oxidation layer 4 are deposited on the p-type silicon substrate 1 using diffusion and epitaxial growth techniques as shown in FIG. In this case, the buried layer 2 is separated from the adjacent layer by the pn junction with the electrooxidation layer 4 (not shown).

상기 형성된(3, 4)위에 폴리실리콘(8)을 두께가 약 3000-4000Å 정도로 증착시키고, 이온주입법을 이용하여 폴리실리콘층(8)내로 붕소이온 (B+)또는, 디플루오르화 붕소이온(BF-2)를 상당량 주입하여 폴리실리콘층(8)을 높게 도우핑된 폴리실리콘층(8')으로 변화시키며, 상기 높게 도우핑된 폴리실리콘층(8')위에 화학적 진공증착법으로 1차이산화실리콘막(9)을 3000-4000Å 정도 증착시킨다. 1차이산화막(9)을 증착시킨 후 사진식각술을 이용하여 에미터가 형성될 부위에 저항 패턴(14)을 형성하면 제 3 도(b)와 같이 된다. 이때, 상기 저항패턴(14)을 형성되어 사용되는 석판 인쇄마스트가 본 발명에서 사용되는 유일한 마스크이다.On the formed (3, 4), the polysilicon 8 is deposited to a thickness of about 3000-4000 mm 3, and the boron ion (B +) or the difluorinated boron ion (BF) is introduced into the polysilicon layer 8 by ion implantation. 2 ) injecting a substantial amount to change the polysilicon layer 8 to a highly doped polysilicon layer 8 ', and primary silicon dioxide on the highly doped polysilicon layer 8' by chemical vacuum deposition. The film 9 is deposited on the order of 3000-4000 mm 3. After the deposition of the primary dioxide film 9, the resist pattern 14 is formed on the portion where the emitter is to be formed using photolithography, as shown in FIG. 3 (b). At this time, the lithography mask used to form the resistance pattern 14 is the only mask used in the present invention.

패턴(14)을 형성한 후 1차 이산화실리콘막(9)을 반응성 이온에칭방법으로 에칭시키고, 이때 폴리실리콘막(8')이 1차 이산화실리콘막(9)에 의해 노출되는데, 패턴화된 1차 이산화실리콘막(9)과 패턴(14)을 마스크로 사용하여 노출된 폴리실리콘막(9)위에 저항패턴(14)을 제거한 후 패턴화된 이산화실리콘막(9)을 마스크로 하여 노출된 폴리실리콘막(8')을 습식에칭법으로 선택적에칭한다.After forming the pattern 14, the primary silicon dioxide film 9 is etched by a reactive ion etching method, wherein the polysilicon film 8 'is exposed by the primary silicon dioxide film 9, which is patterned. After removing the resistance pattern 14 on the exposed polysilicon film 9 using the primary silicon dioxide film 9 and the pattern 14 as a mask, the patterned silicon dioxide film 9 was exposed as a mask. The polysilicon film 8 'is selectively etched by the wet etching method.

상기한 에칭을 하기위해서 사이드에칭공정이 적합한데, 사이드에칭처리된 부분의 폭은 약 2000Å-3500Å이다.The side etching process is suitable for the above etching, and the width of the side etched portion is about 2000 kPa-3500 kPa.

다음에, 폴리실리콘층(8')내에 주입된 도핑물질인 붕소를 n형 에픽택셜층(3)으로 확산시켜 두께가 약 3000-5000Å인 p형 베이스 접촉영역(5)을 제 3 도(d)와 같이 형성한다.Next, boron, a doping material injected into the polysilicon layer 8 ', is diffused into the n-type epitaxial layer 3 to form a p-type base contact region 5 having a thickness of about 3000-5000 mm 3 (d). ).

기판위의 모든 표면상에 두께 500-1500Å정도의 질화실리콘막(11)을 증착한 후 2차 이산화실리콘막(12)을 증착시키면 제 3 도(e)와 같이되고, 반응성 이온에칭법으로 질화실리콘막(11)과 2차 이산화실리코막(12)을 순차적으로 에칭시키면 에지부분의 질화실리콘막(11)과 이산화실리콘막(12)만 남게 된다.After depositing a silicon nitride film 11 having a thickness of about 500-1500 상 에 on all surfaces on the substrate, the second silicon dioxide film 12 is deposited as shown in FIG. 3 (e), and nitrided by reactive ion etching. When the silicon film 11 and the secondary silicon dioxide film 12 are sequentially etched, only the silicon nitride film 11 and the silicon dioxide film 12 at the edge portion remain.

다음공정으로, 1013-1014atm/㎠ 정도의 붕소를 30-40 KeV로 n형 에픽택셜층(3)에 주입한다.In the next step, 10 13 -10 14 atm / cm 2 boron is injected into the n-type epitaxial layer 3 at 30-40 KeV.

상기 이온주입공정에 있어서, 1차 이산화실리콘층(9)은 마스크로 사용되고, 붕소를 n형 에피택셜층(3)에 선택적으로 주입한 후 기판을 어닐링(annealing)하면 제 3 도(f)처럼 3000-4000Å정도 길이의 p형 활성베이스 영역(6)이 형성된다.In the ion implantation process, the primary silicon dioxide layer 9 is used as a mask, selectively implanting boron into the n-type epitaxial layer 3, and then annealing the substrate, as shown in FIG. 3 (f). A p-type active base region 6 of about 3000-4000 mm in length is formed.

이 어닐링처리에 의해 활성베이스영역(6)이 확장되어 베이스접촉영역(5)에 접하게 된다.By this annealing treatment, the active base region 6 is extended to come into contact with the base contact region 5.

다음은, 폴리실리콘막(10)을 기판의 표면상에 전체적으로 증착한 뒤 약 1015-1016atm/㎠ 량의 비소이온(As)을 120-150 KeV로 상시 폴리실리콘막(10)전체에 주입하면 제 3 도(g)와 같이 된다.Next, the polysilicon film 10 is entirely deposited on the surface of the substrate, and then about 10 15 -10 16 atm / cm 2 of arsenic ions (As) is always 120-150 KeV to the entire polysilicon film 10. When injected, it is shown in FIG. 3 (g).

다음은 에미터 접촉전극을 형성하기 위한 공정으로, 사진석판인쇄술로 폴리실리콘막(10')위에 저항패턴을 형성하고, 이 저항패턴을 마스크로 하여 폴리실리콘막(10')을 플라즈마(plaama) 이온에칭한 후 저항패턴을 제거한다.Next, a process for forming an emitter contact electrode is performed. A resist pattern is formed on the polysilicon film 10 'by photolithography, and the polysilicon film 10' is plasma by using the resist pattern as a mask. After ion etching, the resistance pattern is removed.

저항패턴을 제거한 후 어닐링하면 폴리실리콘막(10')에 주입된 비소는 p형 할성베이스영역(6)의 상부에 깊이 1000-2000Å정도까지 확산되어 제 3 도(h)와 같이 에미터영역(7)이 형성된다.After removing the resistance pattern and annealing, the arsenic injected into the polysilicon film 10 'is diffused to a depth of about 1000-2000 mm over the p-type active base region 6, so that the emitter region (Fig. 7) is formed.

이때, 에미터영역(7)이 질화실리콘막(11)의 아래부분으로 확장되어 베이스-에미터접합(J)이 질화실리콘막(11)으로 보호되고, 베이스접촉전극(8')과 에미터접촉전극(10')은 이산화실리콘막(9)에 의해 서로 분리된다.At this time, the emitter region 7 extends to the lower portion of the silicon nitride film 11 so that the base-emitter junction J is protected by the silicon nitride film 11, and the base contact electrode 8 'and the emitter are protected. The contact electrodes 10 'are separated from each other by the silicon dioxide film 9.

비소이온을 p형 활성베이스영역(6)의 상부에 직접주입하는 것보다 본 발명과 같이 폴리실리콘막(10')을 통하여 주입하면 얕은 접합을 얻을 수 있어 고속의 소자성능을 얻을 수 있다.Rather than injecting arsenic ions directly into the upper portion of the p-type active base region 6 through the polysilicon film 10 'as in the present invention, shallow junctions can be obtained and high-speed device performance can be obtained.

따라서, 본 발명에 따르면 본 발명의 반도체장치를 제조하는데 사용되는 마스크는 저항패턴을 형성하기 위해 사용되는 마스크뿐이고, 전극이 모두 자기정합되어 형성되므로 정교하게 트랜지스터를 제조하는 것이 용이할 뿐만아니라, 경비도 절감되고, 회수율도 커지게 된다.Therefore, according to the present invention, the mask used to manufacture the semiconductor device of the present invention is only a mask used to form the resistance pattern, and since the electrodes are all formed by self-alignment, it is easy to manufacture the transistor precisely as well as the cost. In addition, the recovery rate is also increased.

또한, 에미터와 베이스접합부가 질화실리콘막으로 피복되어 보호되므로 고품질, 고속, 고신뢰성을 갖는 반도체장치를 제공할 수 있으며, 에미터영역을 형성할 때 비소이온을 폴리실리콘막(10')을 통해 주입하므로 얕은 접합을 얻을 수 있어 고속성능의 소자를 얻을 수 있다.In addition, since the emitter and the base junction portion are covered and protected by a silicon nitride film, it is possible to provide a semiconductor device having high quality, high speed, and high reliability, and to form a polysilicon film 10 'using arsenic ions when forming the emitter region. Through injection, shallow junctions can be obtained, resulting in high-speed devices.

Claims (1)

p형 실리콘기판(1)상에 n형메몰층(2), n형 에픽택셜층(3) 및 전계확산층(4)이 순차적으로 형성되는 반도체장치를 제조하는데 있어서, (a)상기 에피택셜층(3) 및 전계확산층(4)위에 높게 도우핑된 폴리실리콘막(8')과 첫 번째 이산화실리콘막(9)을 순차적으로 증착하고, (b)는 상기 이산화실리콘막(9)위에 저항패턴(14)을 형성한 후 이산화실리콘막(9)을 선택적으로 에칭하고, (d)저항패턴(14)을 제거한 후 에닐링하여 상기 폴리실리콘막(8')의 사이드에칭부분을 제공하고, 또한, 베이스영역을 형성하기 위하여 상기 폴리실리콘막(8')에 포한된 p형 반도체물질을 n형 에픽택셜층(3)으로 확산시켜 베이스접촉영역(5)을 형성하며, (e)기판의 전표면상에 질화실리콘막(11)과 두 번째 이산화실리콘막(12)을 증착하고, (f)상기 질화실리콘막(11) 두 번째 이산화실리콘막(12)을 에지부분만 남기고 순차적으로 에칭하며, (g)두번째 이산화실리콘층(11)을 마스크로 하여 이온주입법으로 p형 반도체 물질을 n형 에피택셜층(3)으로 주입하여 p형 활성베이스영역(6)을 형성하고, (h)기판의 전표면상에 높게 도우핑된 폴리실리콘층(10')을 적층한 후 저항패턴을 형성하여 노출된 폴리실리콘층(10')을 식각하며, (i)저항패턴을 제거한 후 상기 두 번째 폴리실리콘 층(10')을 통해 n형 반도체물질을 확산시켜 에미터영역(7)을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.In manufacturing a semiconductor device in which an n-type buried layer 2, an n-type epitaxial layer 3, and an electric field diffusion layer 4 are sequentially formed on a p-type silicon substrate 1, (a) the epitaxial layer (3) and the highly doped polysilicon film 8 'and the first silicon dioxide film 9 are sequentially deposited on the field diffusion layer 4, and (b) is a resist pattern on the silicon dioxide film 9 (14) and then selectively etch the silicon dioxide film 9, (d) remove the resistive pattern 14 and then anneal to provide a side etched portion of the polysilicon film 8 '. In order to form the base region, the p-type semiconductor material contained in the polysilicon film 8 'is diffused into the n-type epitaxial layer 3 to form the base contact region 5, (e) a substrate of the substrate The silicon nitride film 11 and the second silicon dioxide film 12 are deposited on the surface, and (f) the silicon nitride film 11 and the second silicon dioxide film 12 are edged. Etching is carried out sequentially, leaving only the minute, (g) p-type semiconductor material is implanted into n-type epitaxial layer 3 by ion implantation method using second silicon dioxide layer 11 as a mask to form p-type active base region 6 (H) stacking the highly doped polysilicon layer 10 'on the entire surface of the substrate and forming a resist pattern to etch the exposed polysilicon layer 10', and (i) removing the resist pattern And then forming an emitter region (7) by diffusing the n-type semiconductor material through the second polysilicon layer (10 ').
KR1019870010068A 1987-09-11 1987-09-11 Manufacturing method of semiconductor device KR950000137B1 (en)

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