KR100332116B1 - Method for fabricating bipolar transistor - Google Patents

Method for fabricating bipolar transistor Download PDF

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Publication number
KR100332116B1
KR100332116B1 KR1019950047330A KR19950047330A KR100332116B1 KR 100332116 B1 KR100332116 B1 KR 100332116B1 KR 1019950047330 A KR1019950047330 A KR 1019950047330A KR 19950047330 A KR19950047330 A KR 19950047330A KR 100332116 B1 KR100332116 B1 KR 100332116B1
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layer
oxide film
bipolar transistor
oxide layer
polysilicon layer
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KR1019950047330A
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Korean (ko)
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KR970054369A (en
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황준
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]

Abstract

PURPOSE: A method for fabricating a bipolar transistor is provided to fabricate a bipolar transistor having a high cutoff frequency and a high speed by preventing a silicon substrate from being damaged by an etch process. CONSTITUTION: A silicon substrate(1) having a P-well(2) is prepared. A collector N+ epi layer(3) is formed on the P-well. A field oxide layer(4) is formed to define an active region through an isolation process. A base polysilicon layer(5) doped with P+ type impurities and an oxide layer(6) are sequentially formed on the field oxide layer including the N+ epi layer. The oxide layer and the base polysilicon layer are patterned to overlap a part of the N+ epi layer and a part of the field oxide layer. A spacer is formed on the side of the patterned oxide layer and base polysilicon layer. After a pedestal ion implantation process using BF2 is performed on the exposed region of the N+ epi layer, a heat treatment process is carried out to form a P- diffusion region(8). An emitter polysilicon layer(9) doped with N+ type impurities is formed on the P- diffusion region and the edge of the oxide layer.

Description

바이폴라 트랜지스터 제조방법Bipolar Transistor Manufacturing Method

본 발명은 바이폴라 트랜지스터(Bipolar Transistor) 제조방법에 관한 것으로, 특히 하이 컷 오프 프리퀀시(high cut off frequency)를 갖는 바이폴라 트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor manufacturing method, and more particularly, to a bipolar transistor manufacturing method having a high cut off frequency.

실리콘 기판에 형성되는 종래 바이폴라 트랜지스터는 산화막 스페이서를 이용하는 자기정렬기술을 적용함에 있어, CVD 산화막을 비등방성식각에 의존하여 산화막 스페이서를 형성하므로, 이로인하여 실리콘 기판이 불필요하게 식각되어져 이온주입에 의해 매우 얕게 형성된 베이스 영역이 과도식각되어 하이 컷 오프 프리퀀시와 하이 스피드(high speed)의 바이폴라 트랜지스터를 이룰수 없는 단점이 있다.In a conventional bipolar transistor formed on a silicon substrate, in applying a self-aligning technique using an oxide spacer, the CVD oxide layer is formed by relying on anisotropic etching to form the oxide spacer, which causes the silicon substrate to be unnecessarily etched, thereby greatly reducing the ion implantation. The shallowly formed base region is excessively etched, which makes it impossible to achieve a high cut off frequency and a high speed bipolar transistor.

따라서, 본 발명은 하이 컷 오프 프리퀀시와 하이 스피드를 갖는 바이폴라 트랜지스터를 제조하는 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a bipolar transistor having a high cut off frequency and a high speed.

이러한 목적을 달성하기 위한 본 발명의 바이폴라 트랜지스터 제조방법은 P웰이 형성된 실리콘 기판이 제공되고, 상기 P웰상에 콜렉터 N+에피층이 형성되는 단계; 소자분리공정에 의해 필드 산화막을 형성하여 액티브 영역이 확정되는 단계; P+타입의 불순물이 도핑된 베이스 폴리실리콘층 및 산화막을 상기 N+에피층을 포함한 상기 필드 산화막상에 순차적으로 형성한 후, 상기 N+에피층의 일부와 상기 필드 산화막의 일부상에 중첩되도록 상기 산화막 및 상기 베이스 폴리실리콘층이 패턴닝되는 단계: 상기 패턴닝된 산화막 및 베이스 폴리실리콘층의 측부에 스페이서가 형성되는 단계; BF2로 페스탈이온주입공정을 실시한 후 열처리함에 의해 상기 노출된 N+에피층에 P-확산영역이 형성되는 단계: 및 상기 P-확산영역의 일부와 상기 산화막의 일부상에 중첩되도록 N+타입의 불순물이 도핑된 에미터 폴리실리콘층이 형성되는 단계로 이루어지는 것을 특징으로 한다.Bipolar transistor manufacturing method of the present invention for achieving this object is provided with a silicon substrate formed with a P well, forming a collector N + epitaxial layer on the P well; Forming a field oxide film by an element isolation process to determine an active region; A base polysilicon layer and an oxide film doped with a P + type impurity are sequentially formed on the field oxide film including the N + epi layer, and then the oxide film and a portion of the N + epi layer and a part of the field oxide film are superimposed. Patterning the base polysilicon layer: forming a spacer on sides of the patterned oxide film and the base polysilicon layer; Forming a P-diffusion region on the exposed N + epitaxial layer by performing heat treatment after performing a pestal ion implantation process with BF 2 ; and N + type to overlap a portion of the P-diffusion region with a portion of the oxide film. It characterized in that it comprises a step of forming an emitter polysilicon layer doped with an impurity.

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제 1A 내지 1C 도는 본 발명의 제 1 실시예에 의한 바이폴라 트랜지스터를 제조하는 방법을 설명하기 위해 도시한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for explaining a method of manufacturing a bipolar transistor according to a first embodiment of the present invention.

제 1A 도를 참조하면, P웰(2)은 P타입 이온주입공정에 의해 실리콘 기판(1)에 형성된다. P웰(2)상에 콜렉터 N+에피층(3)이 형성된다. 소자분리 공정에 의해 필드 산화막(4)이 형성되고, 이로인하여 액티브영역이 확정된다.Referring to FIG. 1A, the P well 2 is formed on the silicon substrate 1 by a P type ion implantation process. The collector N + epitaxial layer 3 is formed on the P well 2. The field oxide film 4 is formed by the element isolation process, thereby determining the active region.

제 1B 도를 참조하면, P+타입의 불순물이 도핑된 베이스 폴리실리콘층(5) 및 산화막(6)을 N+에피층(3)을 포함한 필드 산화막(4)상에 순차적으로 형성한 후, 포토마스크 공정 및 식각공정으로 N+에피층(3)의 일부와 필드 산화막(4)의 일부가 노출되도록 산화막(6) 및 베이스 폴리실리콘층(5)이 패턴닝된다. 패턴닝된 산화막(6) 및 베이스 폴리실리콘층(5)의 측부에 산화막 스페이서(7)가 형성된다. 페스탈(pedestal)이온주입 예를들어, BF2이온주입공정을 실시한 후 열처리함에 의해 노출된 N+에피층(3)에 P-확산영역(8)이 형성된다.Referring to FIG. 1B, after forming the base polysilicon layer 5 and the oxide film 6 doped with P + type impurities sequentially on the field oxide film 4 including the N + epitaxial layer 3, a photomask The oxide film 6 and the base polysilicon layer 5 are patterned so that a part of the N + epi layer 3 and a part of the field oxide film 4 are exposed by the process and the etching process. An oxide spacer 7 is formed on the side of the patterned oxide film 6 and the base polysilicon layer 5. For example, a P-diffusion region 8 is formed in the N + epitaxial layer 3 exposed by heat treatment after performing a BF 2 ion implantation process.

제 1C 도를 참조하면, P-확산영역(8)의 일부와 산화막(6)의 일부상에 중첩되도록 N+타입의 불순물이 도핑된 에미터 폴리실리콘층(9)이 형성된다.Referring to FIG. 1C, an emitter polysilicon layer 9 doped with an N + type impurity is formed so as to overlap a portion of the P-diffusion region 8 and a portion of the oxide film 6.

제 2 도는 본 발명의 제 2 실시예에 의한 바이폴라 트랜지스터 제조방법을 설명하기 위해 도시한 소자의 단면도로서, 제 1 실시예와 유사한 구성을 갖되, 제 1 실시예의 산화막 스페이서(7)내에 질화막 스페이서(10)가 포함된 이중 스페이서 구조가 다르다.FIG. 2 is a cross-sectional view of a device for explaining the bipolar transistor manufacturing method according to the second embodiment of the present invention, which has a structure similar to that of the first embodiment, and includes a nitride film spacer (a) in the oxide film spacer 7 of the first embodiment. The double spacer structure that includes 10) is different.

제 1 및 2 실시예에서는 NPN형 바이폴라 트랜지스터를 제조하는 경우를 설명했지만, PNP형 바이폴라 트랜지스터를 제조하는 경우에도 본 발명의 원리는 동일하게 적용된다.In the first and second embodiments, the case of manufacturing an NPN type bipolar transistor has been described, but the principle of the present invention is equally applied to the case of manufacturing a PNP type bipolar transistor.

상술한 바와같이 본 발명의 제 1 및 2 실시예에 의하면, 실리콘 기판이 식각손상되지 않아 하이 컷 오프 프리퀀시와 하이 스피드를 갖는 바이폴라 트랜지스터를 제조할 수 있다.As described above, according to the first and second embodiments of the present invention, since the silicon substrate is not etched, a bipolar transistor having high cut-off frequency and high speed can be manufactured.

제 1A 내지 1C 도는 본 발명의 제 1 실시예에 의한 바이폴라 트랜지스터 제조방법을 설명하기 위해 도시한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining the method for manufacturing a bipolar transistor according to the first embodiment of the present invention.

제 2 도는 본 발명의 제 2 실시예에 의한 바이폴라 트랜지스터 제조방법을 설명하기 위해 도시한 소자의 단면도.2 is a cross-sectional view of a device illustrated to explain a method for manufacturing a bipolar transistor according to a second embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

1: 실시콘 기판 2: P웰1: Conductor substrate 2: P well

3: 콜렉터 N+에피층 4: 필드 산화막3: collector N + epi layer 4: field oxide film

5: 베이스 폴리실리콘층 6: 산화막5: base polysilicon layer 6: oxide film

7; 산화막 스페이서 8; P-확산영역7; Oxide spacer 8; P-diffusion area

9: 에미터 폴리실리콘층 10: 질화막 스페이서9: emitter polysilicon layer 10: nitride film spacer

Claims (3)

P웰이 형성된 실리콘 기판이 제공되고, 상기 P웰 상에 콜렉터 N+ 에피층이 형성되는 단계;Providing a silicon substrate having a P well formed thereon, and forming a collector N + epilayer on the P well; 소자분리공정으로 필드 산화막을 형성하여 액티브 영역이 확정되는 단계;Forming a field oxide film through an isolation process to determine an active region; P+ 타입의 불순물이 도핑된 베이스 폴리실리콘층 및 산화막을 상기 N+ 에피층을 포함한 상기 필드 산화막 상에 순차적으로 형성한 후, 상기 산화막 및 상기 베이스 폴리실리콘층이 상기 N+ 에피층의 일부와 상기 필드 산화막의 일부 상에 중첩되도록 패터닝되는 단계;After a base polysilicon layer and an oxide film doped with an impurity of P + type are sequentially formed on the field oxide film including the N + epitaxial layer, the oxide film and the base polysilicon layer are a part of the N + epitaxial layer and the field oxide film. Patterned to overlap on a portion of the; 상기 패터닝된 산화막 및 베이스 폴리실리콘층의 측부에 스페이서가 형성되는 단계;Forming a spacer on sides of the patterned oxide layer and the base polysilicon layer; 상기 N+ 에피층의 노출된 영역에 BF2로 페스탈이온주입공정을 실시한 후 열처리 공정을 실시하여 P-확산 영역이 형성되는 단계; 및Performing a heat treatment process on the exposed region of the N + epitaxial layer with BF 2 to form a P-diffusion region; And 상기 P-확산영역 상부와 상기 산화막의 가장자리 상부에 N+ 타입의 불순물이 도핑된 에미터 폴리실리콘층이 형성되는 단계로 이루어지는 것을 특징으로 하는 바이폴라 트랜지스터 제조방법.And forming an emitter polysilicon layer doped with an N + type impurity on the P-diffusion region and on the edge of the oxide layer. 제 1 항에 있어서,The method of claim 1, 상기 스페이서는 산화막으로 이루어지는 것을 특징으로 하는 바이폴라 트랜지스터 제조방법.The spacer is a bipolar transistor manufacturing method characterized in that the oxide film. 제 1 항에 있어서,The method of claim 1, 상기 스페이서는 질화막으로 이루어지는 것을 특징으로 하는 바이폴라 트랜지스터 제조방법.The spacer is a bipolar transistor manufacturing method, characterized in that consisting of a nitride film.
KR1019950047330A 1995-12-07 1995-12-07 Method for fabricating bipolar transistor KR100332116B1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR890005883A (en) * 1987-09-11 1989-05-17 강진구 Manufacturing Method of Semiconductor Device
KR900015256A (en) * 1989-03-30 1990-10-26 강진구 Manufacturing method of self-aligned bipolar transistor
KR930005139A (en) * 1991-08-09 1993-03-23 김광호 Bipolar Transistor Manufacturing Method
US5204277A (en) * 1992-02-03 1993-04-20 Motorola, Inc. Method of forming bipolar transistor having substrate to polysilicon extrinsic base contact
JPH06244365A (en) * 1993-02-15 1994-09-02 Hitachi Ltd Semiconductor device, and manufacture thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR890005883A (en) * 1987-09-11 1989-05-17 강진구 Manufacturing Method of Semiconductor Device
KR900015256A (en) * 1989-03-30 1990-10-26 강진구 Manufacturing method of self-aligned bipolar transistor
KR930005139A (en) * 1991-08-09 1993-03-23 김광호 Bipolar Transistor Manufacturing Method
US5204277A (en) * 1992-02-03 1993-04-20 Motorola, Inc. Method of forming bipolar transistor having substrate to polysilicon extrinsic base contact
JPH06244365A (en) * 1993-02-15 1994-09-02 Hitachi Ltd Semiconductor device, and manufacture thereof

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