KR890005883A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR890005883A
KR890005883A KR870010068A KR870010068A KR890005883A KR 890005883 A KR890005883 A KR 890005883A KR 870010068 A KR870010068 A KR 870010068A KR 870010068 A KR870010068 A KR 870010068A KR 890005883 A KR890005883 A KR 890005883A
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KR
South Korea
Prior art keywords
film
layer
silicon dioxide
type
resist pattern
Prior art date
Application number
KR870010068A
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Korean (ko)
Other versions
KR950000137B1 (en
Inventor
고장만
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019870010068A priority Critical patent/KR950000137B1/en
Publication of KR890005883A publication Critical patent/KR890005883A/en
Application granted granted Critical
Publication of KR950000137B1 publication Critical patent/KR950000137B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음No content

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 트랜지스터의 단면도.2 is a cross-sectional view of a transistor of the present invention.

제3도는 본 발명의 트랜지스터의 제조 공정도.3 is a manufacturing process diagram of the transistor of the present invention.

Claims (1)

P형 실리콘 기판(1)상에 n형 매몰층(2), n형 에피텍셜층(3) 및 전계확산층 (4)이 순차적으로 형성되는 반도체장치를 제조하는데 있어서, (a) 상기 에피텍셜층 (3) 및 전계확산층(4)위에 높게 도우핑된 폴리실리콘막(8')과 첫번째 이산화실리콘막(9)을 순차적으로 증작하고, (b) 상기 이산화실리콘막(9)위에 저항패턴(14)을 형성한 후 이산화실리콘막(9)을 에칭하며, (c) 상기 첫번째 이산화실리콘막(9)에 의해 노출된 폴리실리콘막(8')을 선택적으로 에칭하고, (d) 저항패턴(14)을 제거한 후 어닐링하여 상기 폴리실리콘막(8')의 사이드 에칭부분을 제공하고, 또한, 베이스영역을 형성하기 위하여 상기 폴리실리콘막(8')에 포함된 P형 반도체물질을 n형 에피텍셜층(3)으로 확산시켜 베이스접촉영역(5)을 형성하며, (e) 기판의 전표면상에 질화실리콘막(11)과 두번째 이산화실리콘막(12)을 증착하고, (f) 상기 질화실리콘막(11)과 두번째 이산화실리콘막(12)을 에지부분만 남기고 순차적으로 에칭하며, (g) 두번째 이산화실리콘층(11)을 마스크로 하여 이온 주입법으로 P형 반도체물질을 n형 에피텍셜층(3)으로 주입하여 P형 활성베이스영역(6)을 형성하고, (h) 기판의 전표면상에 높게 도우핑된 폴리실리콘층(10')을 적층한 후 저항패턴을 형성하여 노출된 폴리실리콘층(10')을 식각하며, (i) 저항패턴을 제거한 후 상기 두번째 이산화실리콘층(11)을 통해 n형 반도체물질을 확산시켜 에미터영역(7)을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.In manufacturing a semiconductor device in which an n-type buried layer 2, an n-type epitaxial layer 3, and an electric field diffusion layer 4 are sequentially formed on a P-type silicon substrate 1, (a) the epitaxial layer (3) and the highly doped polysilicon film 8 'and the first silicon dioxide film 9 were sequentially deposited on the field diffusion layer 4, and (b) the resist pattern 14 was deposited on the silicon dioxide film 9; ) And then etch the silicon dioxide film 9, (c) selectively etch the polysilicon film 8 'exposed by the first silicon dioxide film 9, and (d) the resist pattern 14 N) and then annealed to provide a side etched portion of the polysilicon film 8 ', and to form a base region, the P-type semiconductor material included in the polysilicon film 8' is n-type epitec The base contact region 5 is formed by diffusing into the shir layer 3, (e) the silicon nitride film 11 and the second silicon dioxide on the entire surface of the substrate. The cone film 12 is deposited, and (f) the silicon nitride film 11 and the second silicon dioxide film 12 are sequentially etched leaving only an edge portion, and (g) the second silicon dioxide layer 11 is used as a mask. P-type semiconductor material is implanted into n-type epitaxial layer 3 by ion implantation to form P-type active base region 6, and (h) a highly doped polysilicon layer 10 'on the entire surface of the substrate. After forming the resistive pattern to form a resist pattern to etch the exposed polysilicon layer (10 '), (i) the resist pattern is removed, the n-type semiconductor material is diffused through the second silicon dioxide layer 11 to emitter region (7) The manufacturing method of the semiconductor device characterized by including the process of forming. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870010068A 1987-09-11 1987-09-11 Manufacturing method of semiconductor device KR950000137B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870010068A KR950000137B1 (en) 1987-09-11 1987-09-11 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870010068A KR950000137B1 (en) 1987-09-11 1987-09-11 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR890005883A true KR890005883A (en) 1989-05-17
KR950000137B1 KR950000137B1 (en) 1995-01-10

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Application Number Title Priority Date Filing Date
KR1019870010068A KR950000137B1 (en) 1987-09-11 1987-09-11 Manufacturing method of semiconductor device

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KR (1) KR950000137B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100332116B1 (en) * 1995-12-07 2002-07-31 주식회사 하이닉스반도체 Method for fabricating bipolar transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100332116B1 (en) * 1995-12-07 2002-07-31 주식회사 하이닉스반도체 Method for fabricating bipolar transistor

Also Published As

Publication number Publication date
KR950000137B1 (en) 1995-01-10

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